DSP Builder v5.1.0
October 2005
© 2005 Altera Corporation
Prerequisites
Understanding of DSP Builder
Understanding of Simulink
Understanding of SOPC Builder and
Avalon Interface Specification
Understanding of IP MegaCore Design
Flow
Understanding of Quartus II
© 2005 Altera Corporation - Confidential
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Agenda
DSP Builder Overview
New Features in DSP Builder v5.1.0
Enhancements
Known Issues
Conclusion
© 2005 Altera Corporation - Confidential
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Overview
© 2005 Altera Corporation
System Level Design Tool
Development
Implementation
System Level Simulation of
Algorithm Model
RTL Implementation
RTL Simulation
Algorithm
Modeling
Single Simulink Representation
Verification
System Level Verification of
Hardware Implementation
System-level
Verification
Synthesis, Place ‘n Route, RTL Simulation
MATLAB/Simulink
Leonardo Spectrum
Precision, Synplify
Quartus II, ModelSim
Hardware
System Algorithm Design and FPGA Design Integrated
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DSP Builder Overview
Creates HDL Code
Place and Route
Creates Simulation Testbench
HDL Synthesis
Download Design to DSP
Development Kits
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Creates SOPC
Builder Ready
Component
Verify in
Hardware
Version Compatibility
DSP
Builder
MATLAB/
Notes
*
Simulink
5.0.0
R13, R14,
R14SP1,
R14SP2
Recommends Quartus II v5.0
5.0.1
R13, R14,
R14SP1,
R14SP2
Recommends Quartus II v5.0
5.1.0
R14,R14SP1,
R14SP2,
R14SP3
Recommends Quartus II v5.1
Note (*) MATLAB/Simulink R13: Matlab v6.5, Simulink v5.0
MATLAB/Simulink R14: Matlab v7.0, Simulink v6.0
MATLAB/Simulink R14SP1: Matlab v7.0.1, Simulink v6.1
MATLAB/Simulink R14SP2: Matlab v7.0.4, Simulink v6.2
MATLAB/Simulink R14SP3: Matlab v7.1, Simulink v6.3
© 2005 Altera Corporation - Confidential
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New Features
© 2005 Altera Corporation
DSP Builder v5.1 New Features
HDL Import
Enhanced SOPC Builder Integration
Support Multiple Versions of IP MegaCores
Bit Width Parameterization
Name Propagation
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HDL Import
© 2005 Altera Corporation
HDL Import
 Import VHDL, Verilog
or Quartus II Project
 Simulink Simulation
Model is Automatically
Generated
 Allows Co-Simulation
 Does Not Require 3rd
Party Simulator
 Allow Multiple
Instantiations
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HDL Import Interface
 Supports Hierarchical
Designs with Multiple
Entities
 Add Verilog/VHDL Files or
Select Quartus II Project
 Set Top-Level Entity
(Verilog or VHDL only)
 Compile
 Generate Simulink
Model
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HDL Import Requirements
 Single Clock Domain
 Synchronous Design
 Supports Generic Memory and Logic Functions
 Logic Elements
 Memory
 DSP Blocks
 Does Not Support Device Specific Functions
 Examples - PLL, LVDS, WYSIWYG
 Refer to DSP Builder Reference Manual for
Complete List of Supported MegaFunctions
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Design Flow using HDL Import
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What About SubSystemBuilder?
 Import HDL File
 User Creates Own
Simulation Model
 Speed Up Simulation
Using Own Simulink
Model
 Can Use
SubSystemBuilder If
Design Contains
Unsupported
LPMs/MegaFunctions
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Comparison of HDL Co-Design
Features
Features
Design Effort
Simulation Speed
HDL Import
Low
Average
SubSystem Builder
High
Note(1)
Hardware in the Loop
(HIL)
Medium
Fastest
Link for ModelSim
Medium
Fast
Note: (1) User creates their own Simulink simulation model. Simulation speed
depends on the type of simulation model.
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Enhanced SOPC Builder
Integration
© 2005 Altera Corporation
SOPC Builder Integration
 User Can Build Any Avalon SOPC Component
 Dragging and Dropping Avalon Interfaces into DSP Builder Design
 Validate by Simulating in Simulink
 Export to SOPC Builder by Generating HDL and PTF from Signal
Compiler
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Enhanced SOPC Builder Integration
 Interface Blocks
 Avalon Slave
 Avalon Master
 Wrapped Blocks
 Avalon Read FIFO
 Avalon Write FIFO
 Multiple Slaves and
Masters
 Advanced Avalon Bus
Support
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Interface Blocks
 Low-level Access to
Avalon Signals
 All Ports have “PassThrough” Behaviour
 Allows Multiple
Slaves/Masters
 Mechanism for setting
PTF variables
 Dialog to Configure
Mode of Operation
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Avalon Slave
Avalon Master
Avalon Master
 User Configurable to
Allow Subset of
Signals
 Modes of Operation
 Flow Control
 Pipeline Transfers
 Burst Transfers
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Avalon Master Signals
Signal Type
Signals
Fundamental
clk, waitrequest, address, read,
readdata, write, writedata,
byteenable
Pipeline
readdatavalid, flush
Burst
burstcount
Flow Control
endofpacket
Other
irq, irqnumber
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Input
Avalon Master Example
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Output
Avalon Slave
 User Configurable to
Allow Subset of
Signals
 Modes of Operation
 Flow Control
 Pipeline Transfers
 Burst Transfers
© 2005 Altera Corporation - Confidential
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Avalon Slave Signals
Signal Type
Signals
Fundamental
clk, address, read, readdata, write,
writedata, byteenable
Wait-State
waitrequest
Pipeline
readdatavalid
Burst
burstcount, beginbursttransfer
Flow Control
readyfordata, dataavailable,
endofpacket
Other
irq
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Input
Avalon Slave Example
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Output
Wrapped Blocks
 Higher Level of
Abstraction
 Map Avalon Signals to
a “Standard” Subset
 Both Read/Write
FIFOs Handle
Streaming Data
 Test Avalon Interface in
Simulink Environment
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Avalon Write FIFO
Avalon Read FIFO
Avalon Write FIFO
 Hierarchical
Component
 Configuration Dialog
 Data Type
 Data Width
 FIFO Depth
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Avalon Write FIFO Internals
 Look Under Mask
 User Can Customize Functionality using Mask Editor
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Avalon Write FIFO Signals
Signal
Description
TestData
Pass through simulation data to DataOut one
cycle after Ready is asserted
Stall
Simulate stall conditions, and may cause
underflow to SOPC component. When asserted,
data provided by TestData is cached and no
Avalon writes take place.
Ready
When asserted, indicates downstream hardware
is ready for data.
DataOut
Output from FIFO
DataValid
Asserted when valid output is presented on
DataOut
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Avalon Read FIFO
 Hierarchical
Component
 Configuration Dialog
 Data Type
 Data Width
 FIFO Depth
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Avalon Read FIFO Internals
 Look Under Mask
 User Can Customize Functionality using Mask Editor
© 2005 Altera Corporation - Confidential
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Avalon Read FIFO Signals
Signal
Description
Stall
Simulate stall conditions, applying backpressure
to the SOPC Component. When asserted, data
provided on Data fills up FIFO but no Avalon
reads take place.
Data
Outgoing data from user’s design
DataValid
Asserted when valid signal is presented on Data
TestDataOut
Output from FIFO over Avalon Interface
TestDataValid
Asserted when valid output is presented on
TestDataOut
Ready
When asserted, indicates slave is ready to
receive data.
© 2005 Altera Corporation - Confidential
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Testing Blocks
Streaming Avalon Converter
 Provides Data to Avalon Write FIFO
 Collects Data from Avalon Read FIFO
Not Synthesizable
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Avalon Write/Read FIFO Example
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Simulink Simulation
Avalon Blocks Accept Simulink Data
 Use Standard Simulink Source/Sink Blocks
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HDL and PTF Generation
 Set Option to
Generate PTF in
Signal Compiler
 VHDL Entity/Port
Names Derived From
Block
 PTF File Automatically
Generated
 Needed for Import in
SOPC Builder
 Component Appears in
SOPC Suite
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SOPC Builder System Editor
Nios II
H/W
Core
+ DMAs
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What About Avalon Ports?
 Only For Legacy
Design
 Allow One Slave Per
Design
 Avalon Slave Block
Has Same
Functionality
 Except for Chip Select
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Other New Features
© 2005 Altera Corporation
IP MegaCore Support
 Access to Multiple Versions
of IP
 Versioned MegaCore
 Blue Color
 Recommended for New
Designs
 Legacy MegaCore
 Gray Color
 For Backwards Compatibility
 Warnings Will Be Generated
Example:
Warning: The block ‘test/csc' is
linked to 'MegaCoreAltr/csc',
which is a legacy block in the
library and should not be used in
new designs.
© 2005 Altera Corporation - Confidential
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Update IP MegaCore
Automatic Update
 Global Update
 Create Two Variables in MATLAB
 dspbuilder_reinstall_megacores = ‘on’
 dspbuilder_auto_update_megacore=‘on’
 Rerun setup_dspbuilder
 Update MDL (Edit Menu) or Ctrl-D
Manual Update
 Design Specific Update
 update_megacores [design_name]
© 2005 Altera Corporation - Confidential
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Design Parameterization Support
5.0
5.1
 User can explore design optimization possibilities
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Propagation of Signal Names
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Enhancements
© 2005 Altera Corporation
DSP Builder v5.1 Enhancements
Error Message Improvements
Simulation Performance Enhancements
Documentation Improvements
© 2005 Altera Corporation - Confidential
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Improved Error Messaging
Hyperlinks in MATLAB command window
Blocks causing error are highlighted
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IP Simulation
Simulation Time Speed Up
 Typically ~20% Faster
Improved Memory Usage
 Previously Memory Grew Linearly During
Simulation, Limiting Simulation Time
Less Variation in Simulation Time
 Previously > 2x Difference in Run-Time
Possible for Identical Simulations
 Now Always Minimum
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Documentation Improvements
 Integrated with Matlab help
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Known Issues
© 2005 Altera Corporation
HIL and HDL Import Using SBF
Simulation Mismatch Using HIL or HDL
Import Block with Signed Binary Fractional
(SBF) Format
Convert SBF to Signed Using Binary Point
Casting Blocks
SPR#189659
© 2005 Altera Corporation - Confidential
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Unique Entity Names
Option to Generate Unique Hierarchical
Names Cannot be Easily Unset
Option is Disabled by Default
To Enable:
 dspbuilder_enable_unique_hierarchy_name = true;
SPR#189491
© 2005 Altera Corporation - Confidential
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SignalCompiler Flow Shortcut
Shortcut for “Execute steps 1, 2 and 3”
Fails for 3rd Party Synthesis Tools
Run Steps Separately
SPR#190351
© 2005 Altera Corporation - Confidential
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Conclusion
© 2005 Altera Corporation
Conclusion
DSP Builder Offers a Complete Integrated
Platform with Seamless Flow From System
Design to Hardware Design
HDL Import Allows HDL Co-Design
Enhanced SOPC Builder Integration
Simulation Speed Improvements
Improved Usability
© 2005 Altera Corporation - Confidential
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Back-up Slides
© 2005 Altera Corporation
References
AN402: Black-Boxing in DSP Builder
AN403: Avalon Master/Slave Blocks in
DSP Builder
DSP Builder Reference Manual
DSP Builder User Guide
DSP Builder Release Notes
DSP Builder Errata Sheet
© 2005 Altera Corporation - Confidential
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DSP Builder Training
Previous Training Material on DSP
Builder
 Molson
 MAT
 https://go.altera.com/extranet2001/education/internal_training/pr
esentations/int-presentations.html
 AppsNet
 https://go.altera.com/extranet2001/support/iAPPS/specialty_sup
port/ip/dsp/app-spec_ip_dsp.html#dspBuilder
 DSP Technology Symposium
 https://go.altera.com/extranet2001/education/internal_training/int
ernal_tech_training/int-presentations/eduint_tech_presentations.html\
© 2005 Altera Corporation - Confidential
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DSP Builder Roadmap
2005
Q3
DSP

2006
Q4
Builder 5.1
HDL Import

Simulation Speed
Improvements

Enhanced SOPC Builder
Integration
© 2005 Altera Corporation - Confidential
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Q1
Q2
DSP
Builder 6.0
Q3
Q4
DSP

Multi-channel
management blocks


External Memory
Support



SOPC Datapath
Integration
Builder 6.1
Fixed-point data
type
Frame-based
simulation
HIL Improvements
Competitive Analysis
Features
System
Generator
V7.1.0
RTL Import
+

Co-Processor Strategy
+

Hardware CoSimulation

+
HDL Co-Simulation


Synthesis User
Interface
+

+ = Pro
= Neutral
N/A = Not Available
© 2005 Altera Corporation - Confidential
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DSP Builder
v5.1.0
Hardware in the Loop (HIL)
Simulation Acceleration
Instrumentation
Simple Hardware Interface
 JTAG Connector
Source
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Sink
HIL Design Flow
 Step 1 : HIL Block Configuration
 Step 2 : Quartus II Compilation, SOF Program
 Step 3 : Simulate
JTAG HDL
Wrapper
Configure
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Compile/Program
Simulate
Co-simulate HDL using ModelSim
Bidirectional Link Between
MATLAB/Simulink and ModelSim
Provided by Mathworks
System-Level Design Co-simulation and
and Simulation
Verification
MATLAB
Simulink
© 2005 Altera Corporation - Confidential
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Link to ModelSim
HDL Simulation
Modelsim
Link to ModelSim Design Flow




Step 1 : Insert HDL into Simulink as Black-Box
Step 2 : Configure VHDL Co-Simulation Block
Step 3 : Set Up ModelSim and Load Model
Step 4 : Start Simulation in Simulink
Configure
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Set Up ModelSim
Simulate
Subsystem Builder
 Import HDL Design and Black-Box
 Creates Simulink Symbol of Subsystem
 User Creates Simulation Model
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DSP Builder Path in MATLAB
Install Path Not Removed During Uninstallation of DSP Builder v5.0
Conflict Due to Multiple Paths to Library
Edit startup.m MATLAB Script to Comment
Out Path
 <MATLAB install dir>\toolbox\local\startup.m
 %path(path,'C:\altera\DSPBuilder\AltLib');
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