LZRW3 Decompressor
dual semester project
Part A Mid Presentation
Students:
Peleg Rosen
Tal Czeizler
Advisors:
Moshe Porian
Netanel Yamin
22.6.2014
Presentation Content
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Project Goals
Project Requirements
Algorithm Overview
Project Top Block Diagram
Decompression Core Top View
Decompression Core Design and Data Flow
Stages Overview
Problems and Solutions
Project Schedule and Gantt
Project Goals
Project Goals
• Implementation of LZRW3 data decompression core.
Project Goals
• Implementation of LZRW3 data decompression core.
• Implementation of a verification environment.
Project Requirements
Part A:
Project Requirements
• Core Requirements:
–
–
–
–
Process data at the speed of 1 Gbps.
Support data blocks with output of 2KB – 32KB.
Relay only on the FPGA’s internal memory.
VHDL Implementation.
Part A:
Project Requirements
• Core Requirements:
–
–
–
–
Process data at the speed of 1 Gbps.
Support data blocks with output of 2KB – 32KB.
Relay only on the FPGA’s internal memory.
VHDL Implementation.
• Full simulation environment (golden model and checkers).
Part A:
Project Requirements
• Core Requirements:
–
–
–
–
Process data at the speed of 1 Gbps.
Support data blocks with output of 2KB – 32KB.
Relay only on the FPGA’s internal memory.
VHDL Implementation.
• Full simulation environment (golden model and checkers).
Part B:
• Synthesis & implementation of FPGA device (Xilinx Virtex-5).
Part A:
Project Requirements
• Core Requirements:
–
–
–
–
Process data at the speed of 1 Gbps.
Support data blocks with output of 2KB – 32KB.
Relay only on the FPGA’s internal memory.
VHDL Implementation.
• Full simulation environment (golden model and checkers).
Part B:
• Synthesis & implementation of FPGA device (Xilinx Virtex-5).
• GUI implementation in VisualStudio.
LZRW3 compression algorithm
ABD
ABD
BAB
BABDACABDBCAA
Hash
Function
01 2 3 4 56
Slot address
 Output item (Copy item): [slot address , length ]
 In this case Output item = [
, ]
Send every 3 literals to the hash function
Slot address
Hash Table
Put offset in the hash table
If the slot is occupied and the literals match - make copy item
Algorithm Overview
Structure
Algorithm Overview
Structure
File header (8 byte)
Algorithm Overview
Structure
File header (8 byte)
Groups:
Algorithm Overview
Structure
File header (8 byte)
Groups:
- control bytes (2 bytes)
Algorithm Overview
Structure
File header (8 byte)
Groups:
- control bytes (2 bytes)
- data bytes (16 - 32 bytes)
* The last group might be smaller
Algorithm Overview
File header
Decode the header to
determine the file size and
whether it is compressed or
not.
Algorithm Overview
Control bytes
Decode control bytes to
determine the position and
type of the items in the
group, and where the next
control bytes are.
Algorithm Overview
Literal items
Write as is to
output file.
Algorithm Overview
Literal items
Write as is to
output file.
Algorithm Overview
Literal items
Write as is to
output file.
Algorithm Overview
Copy items
Decode to
determine the offset
and length of a
literal sequence to
be copied to the
output file.
Algorithm Overview
Copy items
Decode to
determine the offset
and length of a
literal sequence to
be copied to the
output file.
Algorithm Overview
Copy items
Decode to determine
the offset and length
of a literal sequence.
Write from the
output memory to
itself accordingly.
Project Top Block Diagram
WM1
WS-1
LZRW3
DECOMPRESSION
CORE
WM2
WS-3
WS-2
WM3
Decompression Core Top view
DECOMPRESSION
CORE
Decompression Core Design and Data Flow
CORE MANAGEMENT
STAGE
CORE
DATA IN
EOF IN
CLIENT READY
LZRW3 DONE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
COPY LENGTH
MODE
MODE
LZRW3 GO
DATA IN VALID
5 BYTES BUFFER
STAGE
HASH TABLE SELECT
CORE
MANAGEMENT
UNIT
HASH FUNC SELECT
OFFSET
ADDRESS MANAGER
STAGE
OUTPUT MAMORY
STAGE
WRITE
ADDRESS
COUNTER
5 BYTES BUFFER SELECT
NEW
OLDEST
DATA OUT VALID
DATA IN TAK EN
5 BYTES
BUFFER
INDEX
NEW
OLD
MID
NEW
MODE
DATA IN
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
ADDRESS
MANAGER
WRITE ENABLE
READ ADDRESS
READ ENABLE
MEMORY
BLOCK 1
DATA OUT
CORE
DATA OUT
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
LITERAL
BYTE
WRITE ADDRESS
WRITE
ADDRESS
OLD
READ
INDEX
DATA IN
READ
INDEX
MID
MODE
WRITE
INDEX
COPY 1
LITERAL
BYTE
FIRST 2
BYTES
OLD
MEMORY
BLOCK 18
COPY 2
BYPASS
READ
INDEX
BYPASS
MODE
DATA OUT
Stages Overview – Core Management Unit
Core Management Unit
• Goals:
• To communicate with the core's periphery.
• To receive the input data and parse it.
• To transmit the appropriate control signals to the next stages.
• Method:
• The unit starts with ‘clear’ mode, which initializes the core.
• The following 10 clock cycles are dedicated to Header and Control Bytes decoding.
• From this point on, the unit determines the Mode and sets the appropriate
controls according to the current byte and the previous 4 bytes.
Core Management Unit – Mode selection
Core Management Unit – Outputs
Stages Overview – 5 Bytes Buffer
CORE MANAGEMENT
STAGE
CORE
DATA IN
EOF IN
CLIENT READY
LZRW3 DONE
HASH FUNC
STAGE
COPY LENGTH
MODE
LZRW3 GO
DATA IN VALID
5 BYTES BUFFER
STAGE
HASH TABLE SELECT
CORE
MANAGEMENT
UNIT
HASH FUNC SELECT
5 BYTES BUFFER SELECT
NEW
OLDEST
DATA OUT VALID
DATA IN TAK EN
5 BYTES
BUFFER
BUSY
INDEX
NEW
OLD
MID
NEW
COPY 2
COPY 1
OLD
MID
NEW
WRITE
INDEX
READ
INDEX
HASH
FUNC
Five Bytes Buffer
New byte (8)
New
Byte
Register
New byte (8)
Mid
Byte
Register
Mid byte (8)
Old
Byte
Register
Old byte (8)
Older
Byte
Register
Older byte (8)
Oldest
Byte
Register
Oldest byte (8)
Stages Overview – Hash Function
CORE MANAGEMENT
STAGE
CORE
DATA IN
EOF IN
CLIENT READY
LZRW3 DONE
HASH FUNC
STAGE
COPY LENGTH
MODE
LZRW3 GO
DATA IN VALID
5 BYTES BUFFER
STAGE
HASH TABLE SELECT
CORE
MANAGEMENT
UNIT
HASH FUNC SELECT
5 BYTES BUFFER SELECT
NEW
OLDEST
DATA OUT VALID
DATA IN TAK EN
5 BYTES
BUFFER
BUSY
INDEX
NEW
OLD
MID
NEW
COPY 2
COPY 1
OLD
MID
NEW
WRITE
INDEX
READ
INDEX
HASH
FUNC
Stages Overview – Hash Function
5 BYTES BUFFER
STAGE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
NEW
OLDEST
5 BYTES
BUFFER
NEW
OLD
MID
NEW
MODE
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
WRITE ADDRESS
WRITE
ADDRESS
OLD
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
READ
INDEX
MID
MODE
COPY 1
FIRST 2
BYTES
COPY 2
BYPASS
READ
INDEX
WRITE ENABLE
READ ADDRESS
READ ENABLE
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
ADDRESS
MANAGER
BYPASS
MODE
OLD
#3 Hash Function Stage
TABLE INDEX = (((40543*(((*(PTR))<<8)^((*((PTR)+1))<<4)^(*((PTR)+2))))>>4) & 0xFFF)
PTR pointes to the first byte .
TABLE INDEX range: 0 to 4095.
a7 a6 a5 a4 , a3a2 a1a0 ,0000,0000

0000, b7b6b5b4 , b3b2b1b0 ,0000

0000,0000, c7 c6c5c4 , c3c2c1c0

a7 , a6 , a5 , a4 , a3  b7 , a2  b6 , a1  b5 , a0  b4 , b3  c7 , b2  c6 , b1  c5 , b0  c4 , c3 , c2 , c1 , c0
Stages Overview – Hash Table Stage
5 BYTES BUFFER
STAGE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
NEW
OLDEST
5 BYTES
BUFFER
NEW
OLD
MID
NEW
MODE
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
WRITE ADDRESS
WRITE
ADDRESS
OLD
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
READ
INDEX
MID
MODE
COPY 1
FIRST 2
BYTES
COPY 2
BYPASS
READ
INDEX
WRITE ENABLE
READ ADDRESS
READ ENABLE
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
ADDRESS
MANAGER
BYPASS
MODE
OLD
Block Overview – Write Address Counter
5 BYTES BUFFER
STAGE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
NEW
OLDEST
5 BYTES
BUFFER
NEW
OLD
MID
NEW
MODE
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
WRITE ADDRESS
WRITE
ADDRESS
OLD
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
READ
INDEX
MID
MODE
COPY 1
FIRST 2
BYTES
COPY 2
BYPASS
READ
INDEX
WRITE ENABLE
READ ADDRESS
READ ENABLE
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
ADDRESS
MANAGER
BYPASS
MODE
OLD
Write Address Counter
According to Mode signal:
• For Literal items increments by 1.
• For Copy items increments by Length.
• Else, doesn’t increment.
Block Overview – Hash Table
5 BYTES BUFFER
STAGE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
NEW
OLDEST
5 BYTES
BUFFER
NEW
OLD
MID
NEW
MODE
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
WRITE ADDRESS
WRITE
ADDRESS
OLD
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
READ
INDEX
MID
MODE
COPY 1
FIRST 2
BYTES
COPY 2
BYPASS
READ
INDEX
WRITE ENABLE
READ ADDRESS
READ ENABLE
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
ADDRESS
MANAGER
BYPASS
MODE
OLD
Hash Table
16 bits
Offset in
5 bits
11 bits
Memory
number
Memory
address
OFFSET
Read Index (12)
OFFSET
From Hash
Func
Write Index (12)
From Core
Mgmt
Hash Table
Select
Offset out
4096 rows
Write
Address
Counter
Hash Table – Default String
The LZRW3 algorithm dictates that the
5 bits
11 bits
string “123456789012345678” is set as
Memory
number
Memory
address
default.
OFFSET
OFFSET
4096 rows
16 bits
The Default String
Hash Table – Default String
The LZRW3 algorithm dictates that the
5 bits
11 bits
string “123456789012345678” is set as
Memory
number
Memory
address
default.
OFFSET
Meaning, when a sequence starting
“123..” is received, a copy item is
created, even if it is the first time the
sequence appears.
OFFSET
4096 rows
16 bits
The Default String
Hash Table – Default String
The LZRW3 algorithm dictates that the
5 bits
11 bits
string “123456789012345678” is set as
Memory
number
Memory
address
default.
OFFSET
Meaning, when a sequence starting
“123..” is received, a copy item is
OFFSET
created, even if it is the first time the
sequence appears.
The index ‘1264’ is initialized with
zeroes, which stand for the default
string.
1264
00000
00000000000
4096 rows
16 bits
The Default String
Hash Table – Default String
The LZRW3 algorithm dictates that the
5 bits
11 bits
string “123456789012345678” is set as
Memory
number
Memory
address
default.
OFFSET
Meaning, when a sequence starting
“123..” is received, a copy item is
OFFSET
created, even if it is the first time the
sequence appears.
The index ‘1264’ is initialized with
zeroes, which stand for the default
string.
1264
00000
00000000000
4096 rows
16 bits
The Default String
Block Overview – First 2 Bytes
5 BYTES BUFFER
STAGE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
NEW
OLDEST
5 BYTES
BUFFER
NEW
OLD
MID
NEW
MODE
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
WRITE ADDRESS
WRITE
ADDRESS
OLD
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
READ
INDEX
MID
MODE
COPY 1
FIRST 2
BYTES
COPY 2
BYPASS
READ
INDEX
WRITE ENABLE
READ ADDRESS
READ ENABLE
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
ADDRESS
MANAGER
BYPASS
MODE
OLD
Why is First 2 Bytes needed?
Why is First 2 Bytes needed?
• In the original file:
ABCXYZABC
• In the compressed file: ABCXYZC1C2
Why is First 2 Bytes needed?
• In the original file:
ABCXYZABC
• In the compressed file: ABCXYZC1C2
• If we wish to keep our Hash Table identical to
the Hash Table of the compressor, we must
somehow fetch AB instead of C1C2.
First Two Bytes
Bypass Read Index (12)
From Hash
Func
Write Index (12)
From Core
Mgmt
Hash Table
Select
Two bytes out
8 bits
8 bits
First byte
Second byte
OFFSET
4096 rows
Old byte & Mid byte
16 bits
Block Overview – First 2 Bytes
X
Y
Z
A
B
Block Overview – First 2 Bytes
X
Y
Z
A
B
Block Overview – First 2 Bytes
X
Y
Y
Z
Z
C1
INDEX
A
B
Block Overview – First 2 Bytes
X
Y
Y
Z
Z
C1
INDEX
A
B
Block Overview – First 2 Bytes
X
Y
Y
Z
Z
C1
X
Y
Z
A
B
INDEX
Block Overview – First 2 Bytes
Z
X
Y
Y
Z
C1
X
Y
INDEX
Z
A
B
INDEX
Block Overview – First 2 Bytes
Z
X
Y
Z
Y
C1
INDEX
A
B
INDEX
Block Overview – First 2 Bytes
XY
YZ
C1
Z
B
A
Y
X
INDEX
Stages Overview – Address Manager
5 BYTES BUFFER
STAGE
HASH FUNC
STAGE
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
NEW
OLDEST
5 BYTES
BUFFER
NEW
OLD
MID
NEW
MODE
COPY
LENGTH
COPY 2
COPY 1
MID
NEW
WRITE ADDRESS
WRITE
ADDRESS
OLD
HASH
FUNC
MODE
HASH
TABLE
READ
ADDRESS
READ
INDEX
MID
MODE
COPY 1
FIRST 2
BYTES
COPY 2
BYPASS
READ
INDEX
WRITE ENABLE
READ ADDRESS
READ ENABLE
WRITE ADD SELECT
WRITE
INDEX
WRITE
INDEX
ADDRESS
MANAGER
BYPASS
MODE
OLD
Stages Overview – Address Manager
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
MODE
HASH
TABLE
READ
ADDRESS
DATA IN
COPY
LENGTH
LITERAL
BYTE
WRITE ADDRESS
WRITE
ADDRESS
MODE
OUTPUT MAMORY
STAGE
ADDRESS
MANAGER
WRITE ENABLE
READ ADDRESS
READ ENABLE
MEMORY
BLOCK 1
DATA OUT
CORE
DATA OUT
WRITE ADD SELECT
WRITE
INDEX
READ
INDEX
DATA IN
MID
MODE
WRITE
INDEX
COPY 1
LITERAL
BYTE
FIRST 2
BYTES
OLD
MEMORY
BLOCK 18
COPY 2
BYPASS
READ
INDEX
BYPASS
MODE
DATA OUT
Stages Overview – Output Memory
HASH TABLE
STAGE
COPY LENGTH
MODE
OFFSET
ADDRESS MANAGER
STAGE
WRITE
ADDRESS
COUNTER
MODE
HASH
TABLE
READ
ADDRESS
DATA IN
COPY
LENGTH
LITERAL
BYTE
WRITE ADDRESS
WRITE
ADDRESS
MODE
OUTPUT MAMORY
STAGE
ADDRESS
MANAGER
WRITE ENABLE
READ ADDRESS
READ ENABLE
MEMORY
BLOCK 1
DATA OUT
CORE
DATA OUT
WRITE ADD SELECT
WRITE
INDEX
READ
INDEX
DATA IN
MID
MODE
WRITE
INDEX
COPY 1
LITERAL
BYTE
FIRST 2
BYTES
OLD
MEMORY
BLOCK 18
COPY 2
BYPASS
READ
INDEX
BYPASS
MODE
DATA OUT
IN DATA
NEW BYTE
COPY
LENGTH
3
MODE
ENABLE WRITE
ADDRESS READ
COPY MODE
WRITE
ADDRESS
ENABLE READ
MEMORY
BLOCK 1
OUT DATA
DATA 1
SELECT ADD WRITE
2 - 25
READ
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
3 - 25
4 - 25
IN DATA
1-7
2-7
3-7
ADDRESS
MANAGER
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 2
OUT DATA
DATA 2
SELECT ADD WRITE
IN DATA
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
SELECT ADD WRITE
MEMORY
BLOCK 3
DATA 3
OUT DATA
CORE
OUT DATA
IN DATA
NEW BYTE
COPY
LENGTH
3
MODE
ENABLE WRITE
ADDRESS READ
COPY MODE
WRITE
ADDRESS
ENABLE READ
MEMORY
BLOCK 1
OUT DATA
DATA 1
SELECT ADD WRITE
2 - 25
READ
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
3 - 25
4 - 25
IN DATA
1-7
2-7
3-7
ADDRESS
MANAGER
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 2
OUT DATA
DATA 2
SELECT ADD WRITE
IN DATA
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
SELECT ADD WRITE
MEMORY
BLOCK 3
DATA 3
OUT DATA
CORE
OUT DATA
IN DATA
NEW BYTE
COPY
LENGTH
3
MODE
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
COPY MODE
WRITE
ADDRESS
1-7
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 1
OUT DATA
DATA 1
SELECT ADD WRITE
2 - 25
3 - 25
4 - 25
IN DATA
READ
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
ADDRESS2 - 7
MANAGER
ENABLE WRITE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 2
OUT DATA
DATA 2
SELECT ADD WRITE
IN DATA
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
3-7
ADDRESS READ
ENABLE READ
SELECT ADD WRITE
MEMORY
BLOCK 3
DATA 3
OUT DATA
CORE
OUT DATA
IN DATA
NEW BYTE
COPY
LENGTH
3
MODE
WRITE
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
COPY MODE
1-7
READ ENABLE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 1
OUT DATA
DATA 1
SELECT ADD WRITE
IN DATA
READ
ADDRESS
2 - 25
WRITE ENABLE
ADDRESS2 - 7
MANAGER
READ ENABLE
1
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 2
OUT DATA
DATA 2
SELECT ADD WRITE
IN DATA
3 - 25
WRITE ENABLE
3-7
READ ENABLE
2
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
SELECT ADD WRITE
MEMORY
BLOCK 3
DATA 3
OUT DATA
CORE
OUT DATA
IN DATA
NEW BYTE
COPY
LENGTH
3
MODE
WRITE
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
COPY MODE
1-7
READ ENABLE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 1
OUT DATA
DATA 1
SELECT ADD WRITE
IN DATA
READ
ADDRESS
2 - 25
WRITE ENABLE
ADDRESS2 - 7
MANAGER
READ ENABLE
1
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 2
OUT DATA
DATA 2
SELECT ADD WRITE
IN DATA
3 - 25
WRITE ENABLE
3-7
READ ENABLE
2
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
ENABLE READ
SELECT ADD WRITE
MEMORY
BLOCK 3
DATA 3
OUT DATA
CORE
OUT DATA
IN DATA
NEW BYTE
COPY
LENGTH
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
MODE
ENABLE READ
WRITE
ADDRESS
MEMORY
1-7
BLOCK 1
READ ENABLE
CORE
OUT DATA
OUT DATA
DATA 1
SELECT ADD WRITE
IN DATA
READ
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
2 - 25
ADDRESS
MANAGER
ENABLE
WRITE
WRITE
ENABLE
ADDRESS READ
ENABLE READ
MEMORY
2-7
BLOCK 2
READ ENABLE
OUT DATA
DATA 2
SELECT ADD WRITE
1
IN DATA
LITERAL
BYTE
ADDRESS WRITE
3 - 25
ENABLE
WRITE
WRITE
ENABLE
ADDRESS READ
ENABLE READ
MEMORY
3 - 7 BLOCK 3
READ ENABLE
OUT DATA
DATA 3
SELECT ADD WRITE
2
IN DATA
NEW BYTE
COPY
LENGTH
LITERAL
BYTE
ADDRESS WRITE
ENABLE WRITE
ADDRESS READ
MODE
ENABLE READ
WRITE
ADDRESS
MEMORY
BLOCK 1
CORE
OUT DATA
OUT DATA
SELECT ADD WRITE
IN DATA
READ
ADDRESS
LITERAL
BYTE
ADDRESS WRITE
2 - 25
ADDRESS
MANAGER
ENABLE
WRITE
WRITE
ENABLE
ADDRESS READ
ENABLE READ
MEMORY
BLOCK 2
OUT DATA
DATA 1
SELECT ADD WRITE
IN DATA
LITERAL
BYTE
ADDRESS WRITE
3 - 25
ENABLE
WRITE
WRITE
ENABLE
ADDRESS READ
ENABLE READ
SELECT ADD WRITE
MEMORY
BLOCK 3
OUT DATA
DATA 2
Timing Considerations
• The project requirements dictates clock frequency of 125 MHz.
Timing Considerations
• The project requirements dictates clock frequency of 125 MHz.
• Our concern was that the memory stage’s muxes will limit the frequency.
Timing Considerations
• The project requirements dictates clock frequency of 125 MHz.
• Our concern was that the memory stage’s muxes will limit the frequency.
• After writing the VHDL code for the memory stage we synthesized it and ran a timing
analysis, which provided the following result:
Timing Considerations
• The project requirements dictates clock frequency of 125 MHz.
• Our concern was that the memory stage’s muxes will limit the frequency.
• After writing the VHDL code for the memory stage we synthesized it and ran a timing
analysis, which provided the following result:
• Conclusion: The timing requirements will be met.
Primary vs Final Design
Controller
Fetch
stage
Address
Manager
Write Read
address address
Decode
stage
3 Byte
3
Byte
buffer
Calc Address
stage
Hash
Function
12 Bit
Hash
Table
Offset
Offset
out
4 Kbyte
FIFO
Data in
1 Byte
To Output
Block
Index
in
1 Byte
Data in Data out
Copy
Counter
Header
Decoder
1 Byte
Control
Bytes
Decoder
1 Byte
Copy Item
Decoder
Write Address
Counter
Index
Length
Output
Memory
32 Kbyte
Read Address
Write Address
Write Address
From
Input Block
Output Memory
stage
4 Bit
Problems and Solutions
Problem #1: Preforming a copy procedure
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
The problems:
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
The problems:
- Wasting copy length clock cycles in order to copy item.
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
The problems:
- Wasting copy length clock cycles in order to copy item.
- Must stop the pipe and store the incoming data in a FIFO
located at the core’s beginning while copying.
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
The problems:
- Wasting copy length clock cycles in order to copy item.
- Must stop the pipe and store the incoming data in a FIFO
located at the core’s beginning while copying.
- Demands a very complicated controller.
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
The problems:
- Wasting copy length clock cycles in order to copy item.
- Must stop the pipe and store the incoming data in a FIFO
located at the core’s beginning while copying.
- Demands a very complicated controller.
The solution:
Problems and Solutions
Problem #1: Preforming a copy procedure
In the initial design: only 1 output memory.
The problems:
- Wasting copy length clock cycles in order to copy item.
- Must stop the pipe and store the incoming data in a FIFO
located at the core’s beginning while copying.
- Demands a very complicated controller.
The solution:
18 different memory blocks, which enable us to preform
every copy in 2 clock cycles: 1 for reading the data from all
the required memories, and the second for writing the data
back to the right memories. No dependency on copy length!
Problems and Solutions
Problem #2: Ignoring the Control Bytes
Problems and Solutions
Problem #2: Ignoring the Control Bytes
In the initial design: 3 bytes buffer.
Problems and Solutions
Problem #2: Ignoring the Control Bytes
In the initial design: 3 bytes buffer.
The problem:
Problems and Solutions
Problem #2: Ignoring the Control Bytes
In the initial design: 3 bytes buffer.
The problem:
the Control Bytes are needed for the core management unit
to operate correctly, but must be ignored in the data flow
(they mustn't be written in the hash table, and we need to
remember the preceding items). The problem was how to
ignore them without losing data.
Problems and Solutions
Problem #2: Ignoring the Control Bytes
In the initial design: 3 bytes buffer.
The problem:
the Control Bytes are needed for the core management unit
to operate correctly, but must be ignored in the data flow
(they mustn't be written in the hash table, and we need to
remember the preceding items). The problem was how to
ignore them without losing data.
The solution:
Problems and Solutions
Problem #2: Ignoring the Control Bytes
In the initial design: 3 bytes buffer.
The problem:
the Control Bytes are needed for the core management unit
to operate correctly, but must be ignored in the data flow
(they mustn't be written in the hash table, and we need to
remember the preceding items). The problem was how to
ignore them without losing data.
The solution:
Enlarging the buffer from 3 bytes to 5 bytes which enables
us to remember the items that preceded the Control Bytes.
This done, we can select the preceding items and 'bypass'
the Control Bytes with the 5 bytes buffer mux.
Problems and Solutions
Problem #3: Maintaining the Hash Table Correctly
Problems and Solutions
Problem #3: Maintaining the Hash Table Correctly
In the initial design: No First 2 Bytes memory.
Problems and Solutions
Problem #3: Maintaining the Hash Table Correctly
In the initial design: No First 2 Bytes memory.
The problem:
Problems and Solutions
Problem #3: Maintaining the Hash Table Correctly
In the initial design: No First 2 Bytes memory.
The problem:
Before acting on a copy item, the first two bytes of the
literal sequence represented by the copy should be
concatenated with the previous literal items.
Problems and Solutions
Problem #3: Maintaining the Hash Table Correctly
In the initial design: No First 2 Bytes memory.
The problem:
Before acting on a copy item, the first two bytes of the
literal sequence represented by the copy should be
concatenated with the previous literal items.
The solution:
Problems and Solutions
Problem #3: Maintaining the Hash Table Correctly
In the initial design: No First 2 Bytes memory.
The problem:
Before acting on a copy item, the first two bytes of the
literal sequence represented by the copy should be
concatenated with the previous literal items.
The solution:
Maintaining the First 2 bytes memory, which holds the first 2
bytes of each literal sequence whose offset is written to the
hash table. This way, concatenation is possible by extracting
the necessary bytes from the first 2 bytes memory.
New Problem
Problem #4: Copy adjacent to the sequence it points to
New Problem
Problem #4: Copy adjacent to the sequence it points to
The problem:
New Problem
Problem #4: Copy adjacent to the sequence it points to
The problem:
When trying to concatenate the first 2 bytes of a copy, there
is a problem if the copy item arrives straight after the literal
sequence that created it. The first 2 bytes are not yet stored,
thus cannot be retrieved.
New Problem
Problem #4: Copy adjacent to the sequence it points to
The problem:
When trying to concatenate the first 2 bytes of a copy, there
is a problem if the copy item arrives straight after the literal
sequence that created it. The first 2 bytes are not yet stored,
thus cannot be retrieved.
The proposed solution:
New Problem
Problem #4: Copy adjacent to the sequence it points to
The problem:
When trying to concatenate the first 2 bytes of a copy, there
is a problem if the copy item arrives straight after the literal
sequence that created it. The first 2 bytes are not yet stored,
thus cannot be retrieved.
The proposed solution:
Comparator, which determines if the index of the copy item
is the last index written to in the Hash Table. If so, the
relevant data is bypassed.
Project Schedule 1/2
Date
Goals
21/3/2014 – 5/4/2014
Project Characterization
Algorithm interpreting
6/4/2014
Characterization Presentation
7/4/2014 – 2/6/2014
Full Characterization of all blocks
3/6/2014 – 21/6/2014
•System blocks VHDL
•Design
22/6/2014
Mid presentation
23/6/2014 – 25/7/2014
Work on project paused for exams
&
Project Schedule 2/2
Date
Goals
30/7/2014 – 4/9/2014
VHDL design Cont.
21/9/2014 – 20/10/2014
Building a simulation environment
21/10/2014 – 21/11/2014
Simulation run & debug
22/11/2014
Part A - Final presentation
23/11/2014 – 10/12/2014
FPGA synthesis & implementation
11/12/2014 – 25/12/2015
GUI implementation
26/12/2014 – 24/1/2015
Tests & debug
25/1/2015
Final project presentation
Project Gantt
Weeks:
 Characterization &
interpretation
0-5
6 – 12
13 – 19
20 - 26
27 - 32
4
 Characterization …….........
presentation
 Blocks
characterization
 VHDL blocks
implementation
8
2
 Mid presentation ....………...……………
 Exams
 VHDL Cont.
4
4
2
 Part A - Final pres. ……...….…….……………………………………
 Building Sim Env
 Sim & Debug
 FPGA synthesis
 GUI implementation
 Tests & debug
3
3
2
2
2
….…….……………………………………………………….…............
 Final presentation
 Writing portfolio