Topics
Basic fabrication steps.
 Transistor structures.
 Basic transistor behavior.
 Latch up.

Modern VLSI Design 4e: Chapter 2
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Our technology

We will study a generic 180 nm technology.
– Assume 1.2V supply voltage.
Parameters are typical values.
 Parameter sets/Spice models are often
available for 180 nm, harder to find for 90
nm.

Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
Fabrication services

Educational services:
–
–
–
–

U.S.: MOSIS
EC: EuroPractice
Taiwan: CIC
Japan: VDEC
Foundry = fabrication line for hire.
– Foundries are major source of fab capacity
today.
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
Fabrication processes

IC built on silicon substrate:
– some structures diffused into substrate;
– other structures built on top of substrate.
Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
 Wires made of polycrystalline silicon
(poly), multiple layers of aluminum (metal).
 Silicon dioxide (SiO2) is insulator.

Modern VLSI Design 4e: Chapter 2
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Simple cross section
SiO2
metal3
metal2
metal1
transistor
via
poly
n+
Modern VLSI Design 4e: Chapter 2
p+
n+
substrate
substrate
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Photolithography
Mask patterns are put on wafer using photosensitive material:
Modern VLSI Design 4e: Chapter 2
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Process steps
First place tubs to provide properly-doped
substrate for n-type, p-type transistors:
p-tub
p-tub
substrate
Modern VLSI Design 4e: Chapter 2
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Process steps, cont’d.
Pattern polysilicon before diffusion regions:
poly
p-tub
Modern VLSI Design 4e: Chapter 2
gate oxide
poly
p-tub
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Process steps, cont’d
Add diffusions, performing self-masking:
poly
n+
p-tub
Modern VLSI Design 4e: Chapter 2
poly
n+
p+
p-tub
p+
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Process steps, cont’d
Start adding metal layers:
metal 1
metal 1
vias
poly
n+
p-tub
Modern VLSI Design 4e: Chapter 2
n+
poly
p+
p-tub
p+
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Transistor structure
n-type transistor:
Modern VLSI Design 4e: Chapter 2
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0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
Modern VLSI Design 4e: Chapter 2
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Transistor layout
n-type (tubs may vary):
L
w
Modern VLSI Design 4e: Chapter 2
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Drain current characteristics
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
Drain current

Linear region (Vds < Vgs - Vt):
– Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2)

Saturation region (Vds >= Vgs - Vt):
– Id = 0.5k’ (W/L)(Vgs - Vt) 2
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
180 nm transconductances
Typical values:
 n-type:
– kn’ = 170 A/V2
– Vtn = 0.5 V

p-type:
– kp’ = 30 A/V2
– Vtp = -0.5 V
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
Current through a transistor
Use 180 nm parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
 Vgs = 0.7V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 5.3 A

Vgs = 1.2V:
Id = 62 A
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
Basic transistor parasitics
Gate to substrate, also gate to source/drain.
 Source/drain capacitance, resistance.

Modern VLSI Design 4e: Chapter 2
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Basic transistor parasitics, cont’d
Gate capacitance Cg. Determined by active
area.
 Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.

– Cgs = Col W

Gate/bulk overlap capacitance.
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR
Latch-up
CMOS ICs have parastic silicon-controlled
rectifiers (SCRs).
 When powered up, SCRs can turn on,
creating low-resistance path from power to
ground. Current can destroy chip.
 Early CMOS problem. Can be solved with
proper circuit/layout structures.

Modern VLSI Design 4e: Chapter 2
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Parasitic SCR
circuit
Modern VLSI Design 4e: Chapter 2
I-V behavior
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Parasitic SCR structure
Modern VLSI Design 4e: Chapter 2
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Solution to latch-up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.
Modern VLSI Design 4e: Chapter 2
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Tub tie layout
p+
metal (VDD)
p-tub
Modern VLSI Design 4e: Chapter 2
Copyright  2009 Prentice Hall PTR