Instructions: Language of the
Computer
Chapter 2
Sections 2.1 – 2.10
Dr. Iyad F. Jafar
Outline
 A Word on Binary
 The Von Neumann Architecture
 Busses & Memory
 Program Execution
 The Computer Language
 Instruction Set Architecture
 The MIPS ISA
 MIPS Design Principles
 Fallacies and Pitfalls
 Further Reading
 More Examples
2
A Word on Binary
 Computers are digital devices that encode
everything in binary; 0 and 1
 A binary string could represent signed number,
unsigned number, character, floating number …
 A single binary digit is called a bit
 4 bits  nibble
 8 bits  byte
 16 bits  half word
 32 bits  word
 Given N bits, the maximum number of elements
that can be represented/encoded is 2N
3
A Word on Binary
 Representing numbers
 Unsigned numbers
Given N binary bits that are
used to represent an unsigned
number
BN-1 BN-2 …….. B1 B0
 The value in decimal
(value) = BN-1x2N-1+ BN-2x2N-2 +
… + B0x20
4
 The minimum value is 0
 The maximum value is 2N - 1
Decimal
Binary
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
A Word on Binary
 Representing numbers
 Signed numbers
Given N binary bits that are
used to represent a signed
number
BN-1 BN-2 …….. B1 B0
 Signed two’s complement
 BN-1 is used to represent the sign
0  positive number
1  negative number
 The value in decimal


(value) = (-1)xBN-1x2N-1+ BN-2x2N-2 +
… + B0x20
5
 The minimum value is -2N-1
 The maximum value is 2N-1 - 1
Decimal
Binary
-4
100
-3
101
-2
110
-1
111
0
000
1
001
2
010
3
011
A Word on Binary
 Representing numbers
 Signed numbers
How to compute the two’s complement (negative)
of a number ?
 Method 1  complement the bits then add 1
(+5)  0 101  1 010  1 011  (-5)
(-6)  1 010  0 101  0 110  (+6)
 Method 2  scan the bits from right to left and
6
preserve the bits until the first 1, then complement
the remaining bits
(+5)  0 101  1 011  (-5)
(-6)  1 010  0 110  (+6)
A Word on Binary
Decimal
Binary
Hex.
0
0000
0
1
0001
1
2
0010
2
 Octal
 Hexadecimal
3
0011
3
4
0100
4
5
0101
5
hexadecimal
6
0110
6
7
0111
7
8
1000
8
9
1001
9
10
1010
A
11
1011
B
12
1100
C
13
1101
D
14
1110
E
15
1111
F
 Writing and reading binary
patterns is not easy
 Representing binary patterns in
higher bases is easier
 Conversion from binary to
 Group bits in 4’s
 (0110 1100 1001 0001)2  0x6C91
 Conversion from hexadecimal
to binary
 Expand each hex digit into four
7
bits
 0xFDB2  (1111 1101 1011
0010)2
The Von Neumann Architecture
 John Von Neumann,1945
 A computer consists of
 Processor
 Memory
 Input and Output
 Stored-program concept as
opposed to programcontrolled computers !
 Programs and data are loaded
into memory prior to
execution
 Different components are
connected via set of shared
wires called Busses for
information exchange
 Compare to Harvard
8
Architecture!
Devices
Processor
Datapath
Control
Memory
Input
Output
Busses
 In any computer, there is usually three types of
busses
 Data
 Used to exchange data between components
 Bidirectional
 Typical size 8, 16, 32, and 64 bits
 Address
 Used to specify the source/destination
 Unidirectional
 The size of the bus specifies the number of entities (memory
locations,I/O) that can be addressed
 Control
 Used to specify the operation requested by the CPU (READ,
WRITE, and other handshaking operations)
9
Memory
M-1
Bn-1
B1
B0
Data
(n bits)
0
Address
(Log2 M bits)
Control
10
2
Bn-1
B1
B0
1
Bn-1
B1
B0
0
Bn-1
B1
B0
n bits
(Memory Width)
Program Execution
 Program = Instructions + Data
 Programs are loaded into memory
prior to execution
 In order to execute the instructions,
the CPU
Fetch
 Fetches the instruction
Read the instruction from memory
(Control Unit)
 Decodes the instruction
 Understand what should be done
(Control Unit)
 Executes the instruction
 Perform the required task (Datapath)

 This is done repeatedly until the
end of program !
11
Decode
Execute
The Computer Language
 Commanding computers requires
speaking their language; Binary electric
signals at the hardware level (Machine
Language)
 Tedious, time consuming, error-prone,
knowledge about processor architecture
 Make it easier!
 Represent binary instruction by words
(Assembly Language).
 Convert words to binary manually or
using Assemblers
 Tedious, time consuming, error-prone,
knowledge about processor architecture
 One line corresponds to one instruction!!
 Make it even easier!
Suppose we want to perform two
operations
1) Add two numbers X and Y and
store the result in Z
2) Assign element 5 from array ARR
to W
00001 0011 0001 0010
00101 0010 0000 0111
ADD
READ
Z, X, Y
W, ARR[5]
 Make expressing instructions closer to the
way humans express operations (Highlevel Languages)
 Conversion to machine language is done
automatically using Compilers
12
Z=X+Y
W = ARR[5]
Instruction Set Architecture
 Designing processors requires specifying the type and
number of instructions the processor is supposed to
support and how a programmer can use it
 This is specified by the instruction set architecture
(ISA) of the processor which includes
 Instructions (type, encoding, operation …)
 Memory and I/O access
 Registers (Why do we need registers !)
 Different processors have different ISA
 IA-32, MIPS, SPARC, ARM, DEC, HP, IBM, …
 The same ISA can be implemented in different ways
to achieve different goals
13
 Single-cycle, multi-cycle, pipelining, …
Instruction Set Architecture
 Generally, the design of ISA could follow one of two schools
 CISC - Complex Instruction Set Computers
 RISC - Reduced Instruction Set Computers (~1980s )
14
CISC
RISC
Many instructions and addressing
modes
Few instructions and addressing
modes
Instructions have different levels of
complexity
(different size and execution time)
Simple instructions of fixed size
Shorter programs
Longer programs
Relatively slow
Relatively fast
Expensive !!! (not really)
Cheaper !! (not really)
Intel, AMD, Cyrix
MIPS, Sun SPARC, HP PA-RISC,
IBM PowerPC
The MIPS ISA
 Historical Facts
 Microprocessor without Interlocked Pipeline Stages
 First MIPS processor by John Hennessey in 1981
at Stanford University
 MIPS Technologies, Inc. 1984
 First commercial model R2000 1985
 General Features
 RISC
 32-bit and 64-bit
 Register-Register Architecture (Load-Store)
 ISA revisions  MIPS I, MIPS II, MIPS III, MIPS
15
IV, MIPS V, MIPS32, and MIPS64
 Different processor models R2000, R3000,
R4000, R10000
The MIPS ISA – Register File
5
Read Addr 1
31
B31
B1
B0
5
Read Addr 2
32
Read Data 1
5
Write Addr
32
Write Data
Read/Write
0
2
B31
B1
B0
1
B31
B1
B0
0
B31
B1
B0
32 bits
16
• Inside the CPU
• SRAM !!
• Hold data temporarily
• Some sort of caching of data
• Why two read ports ?
32
Read Data 2
The MIPS ISA – Register File
 When writing assembly, these registers can be referenced by
their address (number) or name
 General purpose and special purpose registers
17
#
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$10
$11
$12
$13
$14
$15
Name
$zero
$at
$v0
$v1
$a0
$a1
$a2
$a3
$t0
$t1
$t2
$t3
$t4
$t5
$t6
$t7
Purpose
Constant zero
Reserved for assembler
Function return value
Function parameter
Temporary – Caller-saved
#
$16
$17
$18
$19
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$30
$31
Name
$s0
$s1
$s2
$s3
$s4
$s5
$s6
$s7
$t8
$t9
$k0
$k1
$gp
$sp
$fp
$ra
Purpose
Temporary – Callee-saved
Temporary – Caller-saved
Reserved for OS
Global pointer
Stack pointer
Frame pointer
Function return address
The MIPS ISA – Register File
 There are other registers !
 Not directly accessible (no address)
 PC: Program counter
 Instruction sequencing
 LO and HI
 Used with multiplication and division instructions
PC
LO
HI
18
32 bits
The MIPS ISA - Instructions
 Different categories
 Arithmetic, logical, memory, flow control
 All instructions are encoded in binary using
32 bits (Fixed Size!!!)
 Three different formats depending on the
number and type of operands, and operation
 R-type
 I-type
 J-type
19
 Instruction encoding
 Opcode  operation code that specifies the
operation in binary
 Operands  the ins and outs of the instruction
The MIPS ISA - Instructions
 Arithmetic instructions
A=B+C
ADD
A, B, C
ADD
$s0, $s1, $s2 #$s0 = $s1 + $s2
F=C-A
SUB
F, C, A
SUB
$t2, $s6, $s4 #$t2 = $s6 - $s4
Operation
Destination, Source1, Source2
destination  source1 op source2
•
•
•
•
20
Each arithmetic instruction performs one operation
Each instruction has three operands
The operands are in the file registers of the datapath
The order of operands is fixed
The MIPS ISA - Instructions
 Arithmetic instructions
Example 1.
Given the following piece of C code, find the equivalent assembly
code using the basic MIPS ISA given so far.
a=b–c
d=3*a
Solution: assume that the variables a, b, c, and d are associated with
registers $s0, $s1, $s2, and $s3, respectively, by the compiler.
sub $s0, $s1, $s2
add $s3, $s0 ,$s0
add $s3, $s3, $s0
21
# $s0 contains b – c
# $s3 contains 2*a
# $s3 contains 3*a
The MIPS ISA - Instructions
 Arithmetic instructions
Example 2.
Given the following piece of C code, find the equivalent
assembly code using the basic MIPS ISA given so far.
f = (g + h) – (i + j)
Solution: assume that the variables f, g, h, i, and j are
associated with registers $s0, $s1, $s2, $s3, and $s4,
respectively, by the compiler.
More efficient translation!???
22
add $t0, $s1, $s2
add $t1, $s3 ,$s4
sub $s0, $t0, $t1
# $t0 contains g + h
# $t1 contains i + j
# $s0 contains (g+h) – (i+j)
The MIPS ISA - Instructions
 Arithmetic Instructions Machine Language
 Any instruction has to be encoded using 32 bits including the
operation and its operands
ADD
R-type
23
$t0,
$s1, $s4
op
rs
rt
rd
shamt
funct
6
5
5
5
5
6
op
6-bits
opcode that specifies the operation
rs
5-bits
register file address of the first source operand
rt
5-bits
register file address of the second source operand
rd
5-bits
register file address of the result’s destination
shamt
5-bits
shift amount (for shift instructions)
funct
6-bits
function code augmenting the opcode
The MIPS ISA - Instructions
 Arithmetic Instructions Machine Language
 Example 3. What is the machine code for ADD $s0, $t0, $s4
ADD
s
$s0,
$t0,
$s4
000000
01000
10100
10000
00000
100000
6
5
5
5
5
6
0000 0001 0001 0100 1000 0000 0010 0000 B
24
0
1
1
4
8
0
2
0
H
The MIPS ISA - Instructions
 Arithmetic Instructions Machine Language
 Example 4. What is the machine code for SUB $s1, $s2, $s3
SUB
s
$s1,
$s2, $s3
000000
10010
10011
10001
00000
100010
6
5
5
5
5
6
0000 0010 0101 0011 1000 1000 0010 0010 B
25
0
2
5
3
8
8
2
2
H
The MIPS ISA - Instructions
 Logical Instructions
 AND, OR, NOR
 Operation is performed between corresponding bits (bitwise)
 R-type instruction format
AND
OR
$s4,
$s0,
$s3, $t4 # $s4 = $s3 & $t4
$t7, $s3 # $s0 = $t7 | $s3
NOR
$s2,
$t6,
$s3 # $s2 = ~($t6 | $s3)
 Example 5. What is the machine code for AND $s1, $t2, $s2
op = 0x0 rs = $t2 = 0x0A rt = $s2= 0x12
rd = $s1 = 0x11 shamt = 0x00 funct = 0x24
26
op
rs
rt
rd
shamt
func
000000
01010
10010
10001
00000
100100
The MIPS ISA - Instructions
 Arithmetic and Logic Instructions with Immediate
 In many occasions, we encounter high-level statements such
as
X=Y+5
Z=W–4
F = 514 x R
If (C>-3) …
 This implies that the operation is between a register and some
constant !
 Can we do this with ADD and SUB instructions?
 Where do these constants come from?
 MIPS ISA specifies a new set of instructions that deal with
immediate data
 ADDI, ORI, ANDI, XORI, …
27
The MIPS ISA - Instructions
 Arithmetic and Logic Instructions with
Immediate
ADDI
ADDIU
I-type
$t5,
$s1,
op
rs
rt
6
5
5
Immediate Addressing!
Instruction
$s3, 130
$s2, 15
Immediate
16
16
Sign
Extension
32
Register
File
28
Reg[rs]
+
The MIPS ISA - Instructions
 Arithmetic and Logic Instructions with
Immediate
ANDI
ORI
I-type
$t1,
$s3,
op
rs
rt
6
5
5
Immediate Addressing!
Instruction
$t3, 12
$a0, 123
Immediate
16
16
Zero
Extension
32
Register
File
29
Reg[rs]
&
The MIPS ISA - Instructions
 Arithmetic and Logic Instructions with
Immediate
 What if the immediate is greater than 16 bits?
 In MIPS, this is achieved in two steps using the Load
Upper Immediate (LUI) and ORI instructions
LUI
$t0, 1000 1111 0001 0010
# loads the upper 16 bits of $t0 and sets the lower 16 bits to 0
 Suppose we want to add the constant
(0000 0010 0100 0010 0001 0011 1100 1100)2 to $s0
LUI
ORI
30
$t0, (0000 0010 0100 0010)2
$at, $t0, (0001 0011 1100 1100)2
The MIPS ISA - Instructions
 Memory instructions
 MIPS ISA address bus is 32 bits, i.e. it can address up to
232 (4 G) locations
 Memory width is usually 8 bits (byte)
0xFF FF FF FF
Address Bus (32 bits)
MIPS CPU
32-bit
Data Bus (32 bits)
Read
Write
0x00 00 00 02
0x00 00 00 01
0x00 00 00 00
31
8 bits
The MIPS ISA - Instructions
 Memory instructions
 Most memories are byte addressable !
 Every four consecutive locations (8 bits each) form a word (32 bits) !
 In other words, the addresses of two consecutive locations differ by 4
0x00 00 00 0E
0x00 00 00 0D
0x00 00 00 0C
0x00 00 00 0B
0x00 00 00 0A
0x00 00 00 09
0x00 00 00 08
0x00 00 00 07
0x00 00 00 06
0x00 00 00 05
0x00 00 00 04
0x00 00 00 03
0x00 00 00 02
0x00 00 00 01
0x00 00 00 00
32
8 bits
0x00 00 00 20
0x00 00 00 1C
0x00 00 00 18
0x00 00 00 14
0x00 00 00 10
0x00 00 00 0C
0x00 00 00 08
0x00 00 00 04
0x00 00 00 00
32 bits
The MIPS ISA - Instructions
 Memory instructions
 Reading from memory requires specifying the address
to read from and a register to store the read data
 Writing to memory requires specifying an address to
write to and a register whose content will be written to
memory
 Simple ! However, addressing a memory location
requires 32 bits
 Where do these bits come from ?!
 Are they stored in memory?!
 Are they part of the instruction ?!
33
 Displacement Addressing
 In MIPS the address is formed by adding the content of
some register (the base register) to 16-bit signed constant
(offset or displacement) that is part of the instruction itself.
 The offset is sign-extended to 32 bits to match the size of
the register.
The MIPS ISA - Instructions
 Memory instructions
 The Load instruction – reads 32 bit value (A word)
into a register
lw
$t0 , 4 ($s4)
Operation Destination Offset Base Register
Reg[$t0] = MEM[Reg[$s4]+sign_extend(4)]
Memory Data
Register
File
32
Register Content
32
Memory
Address
+
32
32
34
Instruction
16
offset
Sign Extension
The MIPS ISA - Instructions
 Memory instructions
 The Store instruction – writes the 32 bits (A word)
found in a register into a memory location
sw
$t5 , -12 ($t1)
Nemunic Destination Offset Base Register
MEM[Reg[$t1]+sign_extend(-12)] = Reg[$t5]
Register Content
Register
File
32
Register Content
32
Memory
Address
+
32
32
35
Instruction
16
offset
Sign Extension
The MIPS ISA - Instructions
 Memory instructions
 The memory is byte-addressable.
 However, the load and store instructions deal with
words (4 bytes)!
 Reading from memory is effectively reading four
bytes! How these bytes are ordered in the 32 bit
register ?
 Storing to memory is storing 32 bits in four
consecutive locations. What is the order by which
these bits are stored in 4 different locations?
 Two approaches
 Little endian: the least significant byte is associated with
36
the location of lowest address (Intel)
 Big endian: the most significant byte is associated with the
lowest address (MIPS)
The MIPS ISA - Instructions
Big Endian
Little Endian
Reading a word from memory
37
Byte 3
0xFD
Register
Byte 2 Byte 1
0x43
0x33
Byte 0
0x10
32 bits
Byte 3
0x10
Register
Byte 2 Byte 1
0x33
0x43
32 bits
Memory
0xFD
0x43
0x33
0x10
Byte 0
0xFD
8 bits
0x00 00 00 F5
0x00 00 00 F4
0x00 00 00 F3
0x00 00 00 F2
The MIPS ISA - Instructions
 Memory Instructions
 Example 7. Convert the following high-level statements to
MIPS assembly language
G=2*F
A[17] = A[16] + G
Solution assume that the variables F and G are associated with
registers $s4 and $s5, respectively, and the base address of the
array A is in $s0. All values are 32-bit integers.
38
add $s5, $s4, $s4
# $s5 contains 2*F
lw $t0, 64($s0)
add $t0, $t0, $s5
sw $t0, 68($s0)
# $t0 contains A[16] (note the offset is 64)
# $t0 contains A[16] + G
# store $t0 in A[17] (note the offset is 68)
The MIPS ISA - Instructions
 Memory Instructions - Machine Language
lw
sw
I-type
39
$t0,
$t2,
4 ($s4)
-6 ($at)
Offset (displacement)
op
rs
rt
6
5
5
16
op
6-bits
opcode that specifies the operation
rs
5-bits
register file address containing the base address
rt
5-bits
register file address of destination register (LW)
or the source register (SW)
Offset
16-bits
displacement or offset (number of bytes to move,
positive or negative)
How far can we move in memory when using LW and SW?
The MIPS ISA - Instructions
 Memory Instructions
6 bits
5 bits
5 bits
16 bits
Opcode
rs
rt
Offset
 Example 6
 Machine code for lw $s5, 4($s1) in hexadecimal
op = 0x23 rs = $s1 = 0x11 rt = $s5 = 0x15
offset = 0x0004
100011
10001
10101
0000 0000 0000 0100
 Machine code for sw $s0, 16($s4) in hexadecimal
op = 0x2b rs = $s4 = 0x14 rt = $s0 = 0x10
offset = 0x0010
40
101011
10100
10000
0000 0000 0001 0000
The MIPS ISA - Instructions
 Memory Instructions
 MIPS ISA defines memory instructions that can
load/store bytes (8 bits) and half words (16 bits)
lb
lbu
sb
$t0, 1($s3)
$t0, 1($s3)
$t0, 6($s3)
#load byte from memory (sign extention)
lh
lhu
sh
$t0, 1($s3)
$t0, 1($s3)
$t0, 6($s3)
#load half word from memory (sign extension)
#load byte from memory (zeros extension)
#store byte to memory
#load half word from memory (sign extension)
#store half word to memory
 When loading a byte into 32-bit register, where is it stored?
 Lower 8 bits of the register ! What about remaining bits?
 When loading a half word into 32-bit register, where is it stored?
 Lower 16 bits of the register ! What about remaining bits?
41
 How about sb and sh instructions?
The MIPS ISA - Instructions
 Memory Instructions
LBU
$s0, 2 ($s4)
# assume Reg[$s4] = 0x00 00 00 F0
Memory
$s0
Byte 3
Byte 2
Byte 1
Byte 0
0x00
0x00
0x00
0xD0
32 bits
LB
$s0, 2 ($s4)
$s0
# assume Reg[$s4] = 0x00 00 00 F0
Byte 3
Byte 2
Byte 1
Byte 0
0xFF
0xFF
0xFF
0xD0
0xFD
0x43
0xC3
0xD0
0x30
0x04
8 bits
32 bits
42
What if the instructions are LH and LHU?
0x00 00 00 F5
0x00 00 00 F4
0x00 00 00 F3
0x00 00 00 F2
0x00 00 00 F1
0x00 00 00 F0
The MIPS ISA - Instructions
 Flow Control Instructions
 Instructions are loaded in memory!
 The normal execution of programs is sequential; one
instruction after another!
 Keeping track of execution is done through a special
register called the Program Counter (PC)
 32 bits (Why???)
 It is incremented automatically by 4 (why!) after an instruction
is fetched
 Thus, its contents always holds the address of the next
instruction!
 It is not directly accessible !!! (Why)
 However, in our programs, we often write statements
that skip some parts of the program, conditionally or
unconditionally !! (IF, SWITCH, WHILE, GOTO … )
 How is this implemented in the hardware !?
43
The MIPS ISA - Instructions
 Flow Control Instructions
 How to skip instructions in memory to execute
others?
 Basically, this requires using instructions that
change the contents of the PC to point to the
address where the target instructions are loaded
(branch/jump address)!
 In MIPS, there are no instructions that can modify
the PC directly!
 Alternatively, we have two conditional and three
unconditional flow control instructions!
 These instructions can change the contents of the
PC indirectly!
44
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 Branch If Equal Instruction (BEQ)
 Checks if two registers are equal!
 If true, then the PC (containing the address of next instruction) is
incremented or decremented by adding a signed 16-bit offset (that
is part of the instruction) after it is multiplied by 4 (WHY?).
 If false, program execution continues normally from the address in
PC.
 This is called PC-relative addressing!
45
BEQ
$t0 , $t1, 15
Operation
Tested Registers
Offset
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 Branch If Equal Instruction (BEQ)
Reg1
=?
Sign
Extension
Reg2
+
Branch Address
MEM
M
U
X
PC
BEQ
….
….
Address of instruction
following BEQ
x4
16 bit offset
Instruction
46
32 bit instruction from branch address (two registers are equal)
32 bit instruction next to BEQ (Two registers are not equal)
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 Branch If Not Equal Instruction (BNE)
 Checks if two registers are not equal!
 If true, then the PC (containing the address of next instruction) is
incremented or decremented by adding a signed 16-bit offset (that
is part of the instruction) after it is multiplied by 4 (WHY?)).
 If false, program execution continues normally from the address in
PC.
 This is called PC-relative addressing!
47
BNE
$t0 , $t1, -23
Operation
Tested Registers
Offset
The MIPS ISA - Instructions
 Flow Control Instructions (Conditional)
 Branch If Not Equal Instruction (BNE)
Reg1
=?
Sign
Extension
+
Branch Address
MEM
M
U
X
PC
Address of instruction
following BNE
x4
16 bit offset
Instruction
48
Reg2
32 bit instruction from branch address (Two registers are
not equal)
32 bit instruction next to BNE (Two registers are equal)
BNE
….
….
The MIPS ISA - Instructions
 Flow Control Instructions
 Example 8. Convert the following high-level statements to
MIPS assembly language
if (x == y)
x=x+y
end
Solution assume that the variables x and y are associated with registers
$s4 and $s5, respectively.
BNE
ADD
…
$s4, $s5, 1
$s4, $s4, $s5
# if $s5 ~= $s4, skip one instruction
# add x and y if they are equal
OR, we can use labels instead of counting how many instructions to skip!
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SKIP:
BNE
ADD
….
$s4, $s5, SKIP
$s4, $s4, $s5
# if $s5 ~= $s4, skip one instruction
# add x and y if they are equal
The MIPS ISA - Instructions
 Flow Control Instructions -Machine Language
BEQ
BNE
I-type
50
$t0,
$t2,
$t1 ,
$v1,
Offset (displacement)
op
rs
rt
6
5
5
4
-214
16
op
6-bits
opcode that specifies the operation
rs
5-bits
first register file address to be compared
rt
5-bits
second register file address to be compared
Offset
16-bits
displacement or offset (number of instructions
to skip, positive or negative!)
How many instructions can we skip when using BNE and BEQ?
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 Example 9.
 Machine code for BEQ $s5, $s1, 20 in hexadecimal.
op = 0x04 rs = $s5 = 0x15 rt = $s1 = 0x11
offset = 0x0014
000100
10101
10001
0000 0000 0001 0100
 Machine code for BNE $s0, $s1, -13 in hexadecimal
op = 0x05 rs = $s0 = 0x10 rt = $s1 = 0x11
offset = 0xFFFD
000101
51
10000
10001
1111 1111 1111 0011
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 BEQ and BNE instructions can check for equality
only?
 How about >
, < , <= , >= ???
 There are no instructions such bgt, bls, bge, ble!!
 In MIPS ISA, this can be done with the aid of
 The Set On Less than Instructions (SLT and SLTU)
 Compares if one register is less than another one
 If so, a third register is loaded with 1
 Otherwise, the third register is loaded with 0
 The $Zero register
 Register number zero
 Hardwired to zero
 Can be read only!
52
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 SLT Instruction
SLT
$s1, $s2, $s3 #set $s1 if $s2 < $s3, else clear $s1
Yes
$S1 = 1
$S2
-
$s2-$s3<0
??
$S3
53
No
$S1 = 0
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 SLT Instruction – Machine Language
SLT
R-type
54
$t0,
$s1, $s4
op
rs
rt
rd
shamt
funct
6
5
5
5
5
6
• Opcode for SLT is 0x00 and the func field is 0x2a
• How about comparing with constants?
• SLTI
• How about comparing unsigned numbers?
• SLTU and SLTIU
The MIPS ISA - Instructions
 Conditional Flow Control Instructions
 So, how can we execute blt $s1, $s2, L1 ?
slt
$at, $s1, $s2
bne
$at, $zero, L1
……….
……….
blt
$s1, $s2, L1
……….
……….
L1:
L1:
 Such instructions are included in the ISA as pseudo
instructions (fake).
 The assembler takes the job of converting them to
actual assembly instructions through using the $at
register
 How about other branch instructions?
55
The MIPS ISA - Instructions
 Unconditional Flow Control Instructions
 Occasionally, we might need to skip part of the
program unconditionally!
 In MIPS, this is achieved by jump instruction which
loads the PC with the 32-bit address of the jump
location
J
label #go to label
 The 32-bit jump address is formed by
 Extracting the upper four bits of the PC (Address of next
instruction)
 Appending them to a 26-bit number found in the
instruction after multiplying it by 4 (WHY!!!)
 This is called Pseudo-direct Addressing
56
The MIPS ISA - Instructions
 Unconditional Flow Control Instructions
 The Jump Instruction
Instruction
PC
Address Field
26 bits
Shift left by 2
4 bits
57
=
28 bits
32 bits
The MIPS ISA - Instructions
 Unconditional Flow Control Instructions
 The Jump Instruction – Machine Language
J
Label
J-type
op
Address Field
6
26
 Opcode 0x02
 How far can we move using the jump instruction?
 What is the machine code for j 136 ? What is the
jump addres if the address of the instruction is
0x32001011?
58
The MIPS ISA - Instructions
 Branching Far Away !
 In programs, branches are local usually!
 What if we need to skip more than -215 or 215-1
instructions !
 The assembler utilizes the Jump instruction and
inverts the condition
beq $s0, $s1, L1
……….
……….
……….
……….
……….
L1:
59
bne $s0, $s1, L2
j
L1
L2: …………
…………
…………
…………
…………
L1:
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 High-level languages support
procedures/functions
 Modularity and code reuse !
 Calling a procedure requires
 Changing the program flow to
the place where the procedure is
located in memory (branching!!!)
 Passing arguments !
 Storing return values!
 Returning to the calling
program!
 How is this implemented in
60
the MIPS ISA?
Procedure
Program
Memory
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 The Jump and Link (JAL) instruction!
 This instruction loads the PC with the 32-bit address of the
procedure
 The procedure address is formed in the same way the jump
address is formed in the Jump instruction (Pseudo
Addressing)
 Additionally, the instruction saves the contents of the PC in
the Return Address register ($ra) ! (WHY!!)
JAL
Operation
61
ProcedureX
Part of the procedure address
(26 bits from the instruction)
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 The Jump Register (JR) instruction!
 When the execution of the procedure is finished, it is
assumed that the CPU should go back to where it was before
invoking the procedure
 This is done by using the JR instruction
 Basically, the instruction loads the PC with the contents of
some register! In procedures, this register is $ra
JR
R-type
62
$t0
# Return
op
rs
rt
rd
shamt
funct
6
5
5
5
5
6
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 How to pass procedure arguments ?
 The argument registers !
 Registers $a0, $a1, $a2, and $a3
 Where to store return values ?
 The value registers !
 Registers $v0 and $v1
 What if the procedure uses registers in the caller?
What if the procedure calls another one?
 Temporarily save these registers in memory during
procedure execution
 Retrieve these values upon procedure completion!
 The STACK !
63
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 The Stack
 An area of memory used for temporary storage
 It is a last-in-first out queue
 Can be accessed like other memory location using Load and
Store instructions!
 However, the base register is a special register called the
Stack Pointer ($SP)
 By convention, the stack grows from high to low address!
(WHY!)
 The SP always points to an occupied location (Top of Stack)
 Two basic operations on Stack
 Saving (PUSH)  write data to stack
 Reading (POP)  read data from stack
64
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 The Stack
 Push Operation
1) $sp = $sp – 4
2) Store data (word) starting at
location pointed by SP!
High Address
SP
ZZ
YY
New SP
XX
WW
Low Address
 Pop Operation
1) Read data (word) starting at
location pointed by SP!
2) SP = SP + 4
65
High Address
New SP
ZZ
YY
SP
XX
WW
Low Address
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 Example 10. Convert the following code fragment to
MIPS assembly (Leaf Procedure)
int func1 (int g, h)
{
int f ;
f = (g + h) ;
return f ;
}
 Assumptions
Argument variables g and h are in argument registers $a0 and
$a1, respectively
 f is assigned to $s0 (need to be saved in stack!)
 Return value in $v0

66
The MIPS ISA - Instructions
 Instructions for Accessing Procedures
 Example 10.
func1:
addi $sp, $sp, -4
sw
$s0, 0($sp)
add
$s0, $a0, $a1
add
$v0, $s0, $zero
lw
$s0, 0($sp)
addi $sp, $sp, 4
jr
67
$ra
Push $s0 to stack
The procedure
Put return value
in $v0
Pop $s0 from
stack
Return
MIPS Design Principles
1) Simplicity favors regularity
• Fixed instruction size
• Few instruction formats
• Opcode is the first 6 bits
2) Good design demands good compromise
• Three instruction formats
3) Smaller is faster
• Limited instruction set
• Small register file
• Few addressing modes
4) Make the common case fast
• Operands are from register file
• Instructions contain immediate data
68
Further Reading
 Non-leaf procedures
 Example in section 2.8
 Translating and Starting a Program
 Section 2.12
 The Intel x86 ISA
 Section 2.17
69
MIPS Organization So Far
Processor
Memory
Register File
src1 addr
src2 addr
dst addr
write
data
5
5
5
32
registers
($zero - $ra)
32
1…1100
src1
data
32
read/write
addr
src2
data
32
branch offset
32
PC
Fetch
PC = PC+4
Execute
32 Add
4
32 Add
read data
32
32
32
write data
32
Decode
230
words
32
32 bits
32
32 ALU
32
32
4
0
5
1
6
2
32 bits
byte address
(big Endian)
7
3
0…1100
0…1000
0…0100
0…0000
word address
(binary)
Review of MIPS Addressing Modes
 Register addressing – operand is in a register
op
rs
rt
rd
funct
Register
word operand
 Base (displacement) addressing – operand is at the
memory location whose address is the sum of a register
and a 16-bit constant contained within the instruction
op
rs
rt
offset
Memory
word or byte operand
base register
 Register relative (indirect) with
 Pseudo-direct with
0($a0)
addr($zero)
 Immediate addressing – operand is a 16-bit constant
contained within the instruction
op
rs
rt
operand
Review of MIPS Addressing Modes
 PC-relative addressing –instruction address is the sum of
the PC and a 16-bit constant contained within the
instruction
op
rs
rt
offset
Memory
branch destination instruction
Program Counter (PC)
 Pseudo-direct addressing – instruction address is the 26-
bit constant contained within the instruction
concatenated with the upper 4 bits of the PC
op
Memory
jump address
=
Program Counter (PC)
jump destination instruction
Fallacies
 Powerful instruction  higher performance
 Fewer instructions required in programming?!?!?
 But complex instructions are hard to implement!
 May slow down all instructions, including simple ones
 Compilers are good at making fast code from simple
instructions
 Use assembly code for high performance
 But modern compilers are better at dealing with
modern processors
 More lines of code  more errors and less
productivity
73
Pitfalls
 Sequential words are not at sequential addresses
 Increment by 4, not by 1 since instructions are 32
bits and memory is word addressable!
 The offset in branch instructions is the number
of instructions
 It is multiplied in hardware by 4 to convert it to
bytes
74
Reading Assignment
 Assignment 1. Load-store (register-register) is
not the only ISA ! Other ISAs are also available
 Accumulator
 Stack
 Register-Memory
 Memory-Memory
Search the web and read more about these ISAs
 Assignment 2. Read Section 2.17 – Real Stuff :
x86 Instructions
75
More Examples
 Example 11. Convert the following high-level
code into MIPS assembly language. Make your
own association for registers. Assume array to
contain signed 32-bit values.
A=5;
B=2*A;
if B < array[12] then
array[12] = 0
else
array[12] = -20
end
76
More Examples
 Example 12. Assume that the following assembly
code is loaded in memory. Draw the memory and
show its contents assuming that the program
counter starts at 0x00000400.
Next:
77
add
beq
lw
lw
$s0, $s1, $s2
$s0, $s3, Next
$s0, -15($s5)
$s0, 5($s6)
More Examples
 Example 13. What is the assembly language
instruction that corresponds to each of the
following machine codes
 0x00af8020
 0x0c001101
78
More Examples
 Example 14. The address of the instruction being
executed is 0x00000008, then
79

If this instruction is add $s0, $t9, $zero, then what is the
address of the instruction executed after this
instruction?

If this instruction is j 256, then what is the address of
the instruction executed after this instruction?

If this instruction is jal 100, then what is the content of
the $ra register after executing this instruction?

If this instruction is beq $s1, $s2, 25 and the condition
evaluates to true, then what is the address of the
instruction executed after this instruction?
More Examples
 Example 15. Convert the following high-level
statements into MIPS assembly language.
int x ; 32-bit signed number
short unsigned int Array[32] ; 16-bit unsigned
for (x=0; x=31; x++)
{
Array[x] = 2 * Array[x] ;
}
80
More Examples
 Example 16. Convert the following function into
MIPS assembly language. Assume that the
variable i is in $s0.
void strcpy (char x[ ], char y[ ])
{
int i ;
i = 0 ;
while ((x[i] = y[i]) != ‘\0’)
i += 1 ;
}
81