DAC2001 Panel Proposals 8, 7
Andrew B. Kahng
January 18, 2001
#8: Is Nanometer Design Under Control?
• Issues
– 130nm and below in 2001, 100+M xtors, many nanometer (“VDSM”) effects:
timing/SI closure, power/thermal analysis, variability, reliability, …
– Retooling and new methodologies for both vendors and users
– Is the situation under control? (Vendors: “sort of” vs. Designers: “in crisis”)
• Example questions and perspectives
– Do more back-end physical destails need to be included in the design creation
loop? Have enough “unifications” been made? Physical synthesis is enough vs.
Detailed routing must be considered.
– Is there really a one-pass working flow for SOC? War stories tell us no vs. Tool
capacity and speed are already proven sufficient.
– Are nanometer effects such as IR drop, crosstalk noise, ground bounce,
self/mutual inductance, etc. properly handled by today’s tools? Definitely not yet
handled at full-chip scale vs. There are solutions in hand for all the problems that
actually matter, if only designers would use them.
– Possibility: “Real Debate” format (Oxford Union; Presidential Debate…)
#8: Is Nanometer Design Under Control?
Organizer: Bing Sheu Nassda
Moderator: Andrew Kahng* UC San Diego
Lou Scheffer, Cadence “designs are being done, but done ugly”; report card on nanometer
issues
Ed Cheng, Synopsys “synthesis-placement, STA, verif/test, extraction in good shape”,
“analysis based on layout-extracted parasitics, *RCs, pipeline for technology data, data
capacity are not in good shape”
Sang Wang, Nassda “vendors have a long way to go: capacity, M/S verification, back-end
analysis…; key problem is layout extraction (more than simulation/analysis)”
John Cohn, IBM “surprisingly little focus from CAD vendors on overall chip cost… what
we do for TAT leads to larger dies, higher costs… need help finding ‘sweet spot’ between
integration complexity and manufacturing cost”
Nancy Nettleton, Sun “two primary CAD deficiencies are hierarchy and handling signal
integrity issues due to cross-capacitance… Every viable solution we use today has more
home-brew than EDA industry content. With cross-cap, problems unaddressed by
accuracy of extraction, noise modeling, error filtering, avoidance tactics, and repair algs
have forced us to sacrifice schedule to assure silicon quality.”
Steve Schultz, TI (methodologist) or Shekhar Borkar, Intel (circuits perspective)
#7: Thinking Inside the Box: Package
Solutions Today and Tomorrow
• Issues
– Anyone involved with high-speed design today experiences impact of increasing
number of IC packaging issues. These issues will affect mainstream design and
induce performance metrics – across the IC/package/PCB system supply chain.
– Challenges: dispersive effects, tight timing budgets, complex structure (“black
holes” between three stovepipe design environments)
– Solutions: Methodologies, integrations, workarounds – today and tomorrow
• Example perspectives (overall goal = “tutorial”, not “debate”)
– Die-package codesign required to address cost and performance, and discover
advantages over SOC
– What-if collaborative design needs to involve IC, package, board teams (issues
include IP as well as usual formats/etc.)
– How granular should co-design be? What should be in the co-design tools
environment? How does this change design team composition and schedules?
– Again: what are the best available integrations today, and in the future?
#7: Thinking Inside the Box: Package
Solutions Today and Tomorrow
Organizer: Heidi Vantulden Armstrong-Kendall, Inc.
Moderator: 4. John Baliga Associate Editor, Semiconductor International (Cahners)
(summary, and co-design/collaborative design / IP issues)
1. Paul Franzon, NCSU Key issues and tradeoffs; future technology trends. Tool needs
for modeling/sim, timing/noise tradeoffs, prevention of package-related failures
2A. Donald Hawk, CMTS, Tech Strategy, Lucent Complete cross-functional approach
(“new type of designer needed”). Real examples of cost, manufacturability, density, etc.
effects of front-end package descisions. Design for SI analysis. Thermal constraints.
2B. Gaurang Choksi, Mgr, Assembly Tech Dev, Intel Look at entire interconnect
hierarchy and analyze opportunities for global physical and electrical optimizations.
What does IC-package co-design really entail? Synchronization of design dependencies.
Thermal challenges. Futures such as 3-D and direct attach (still in concept stage…).
3A. Kevin Reinbold, Prod Mgr Adv Packaging, Innoveda A specific IC-package
codesign methodology, using multiple vendors…
3B. Jonathan Smith, Prod Mktg Mgr SI Solutions, Ansoft Characterization of complex
structures using 3-D field solvers; integration directly into package design / layout tool
3C. Joel McGrath, Mktg Mgr Adv Pkg Tech, Cadence PCB Future system design flow
that is cohesive, and facilitates concurrent design