Alpha AXP Architecture
Dr. Richard L. Sites
Presented By
Udaykumar Batchu
Wednesday, 26 January 2005
Dr. Richard L. Sites


Employment
 IBM
 Hewlett-Packard
 Burroughs
 Digital Equipment Corporation (1980) significant contributor
to the Alpha AXP architecture
Education
 B.S. in Mathematics form MIT
 Ph.D. in Computer Science from Stanford University
 Post-doctoral work at the University of North Carolina
(computer architecture)
Architectural Goals
1. High Performance.
2. Longevity.
3. Capability to run both VMS and Unix
Operating Systems.
4 Easy migration from VAX and MIPS
architectures.
1.
Open VMS AXP and DEC OSF/1 and Windows NT
operating systems all run on Alpha AXP implementations
successfully.
PAL Code
It is a Privileged Architecture Library (PAL Code)
1. Contains a set of privileged subroutines that are
specific to a particular Alpha AXP operating system
Implementation.
2. Provides operating system primitives like context
switching , interrupts , exceptions, memory
management and more.
3. Is written in a standard machine code language and it is
accessible by implementation hardware or
CALL_PAL instructions.
Performance And Longevity
Performance :
Alpha AXP architecture is listed in Guinness Book of
World Records as the world’s fastest single-chip
Microprocessor.
Longevity :
In order the Alpha AXP be 1000 times faster over the next
25 years, three factors are considered:
1.
2.
3.
Increasing the raw clock rates by a factor of 10
Another factor of 10 by using multiple instruction issue
Last factor of 10 from using multiple processors
Key Design Issues
1. RISC.
2. Full 64-bit design.
3. Register File.
4. Multiple Instruction Issue (MII).
5. Shared Memory Multiprocessing.
RISC
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Alpha is a load-store machine, i.e. all data is moved between
memory and register without computation; all computation is
done between values in registers
assumed that memory operands are aligned
assumed that implementation latency of many operations would
be important
Multiple Instruction Issue

MII : Starting more than one instruction at once
No Branch Delayed Slots.
No Suppressed Instructions.
No Byte Load/Store Instructions and Implicit
Unaligned accesses and no Partial Register Writes.
No Arithmetic Exceptions.
1.
2.
3.
4.
•
•
Cray-1 Model of Arithmetic Exceptions are adopted in
first AXP architecture (Exceptions are reported at the end
of the event).
Explicit TRAPB ( TRAP Barrier) Instruction.
Shared-memory Multiprocessing
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implements mutual exclusion
uses a sequence of instructions: load-locked, in-register modify,
store-conditional and test.
if the sequence completes with no interrupts, no exceptions and
no interfering: store-conditional stores the result and test reports
success, otherwise the order repeats.
has no strict multiprocessor read/write ordering
VAX avoids pipelined writes to preserve strict read/write
ordering and avoid out-of-order writes
Data Representation in Alpha AXP
Data Characteristics :


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All operations are done using 64-bit Registers.
Memory is accessed via 64-bit virtual addresses, using
the little-endian or big-endian byte numbering
convention.
There are 32 integer registers(R31=0) and 32 floatingpoint registers (F31=0).
Longword(32-bit) and Quadword (64-bit) integers are
supported.
Data Types
1.
Four Integer data types are supported :
•
•
•
•
2.
Byte
Word
Longword
Quadword
Five floating point data types are supported :
•
VAX Floating Point Formats


•
VAX F_floating (32-bit)
VAX G_floating(64-bit)
IEEE Floating Point Formats



IEEE single (32-bit)
IEEE double (64-bit)
IEEE extended (128-bit)
Alpha Register Data Representation

Data Types (32-bit and 64-bit)



Integer
IEEE floating point
VAX floating point
64-bit Data Types
(4) (5) (6)
(3)
(2)
32-bit Data Types
(1)
Alpha Memory Load/Store
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
No instructions operate directly on memory, data
manipulation done between 64-bit registers
Memory access


(1) Reads = Load instruction
(2) Writes = Store instruction
→
←
→
←
32-bit store
32-bit load
→
←
Alpha AXP Instruction Formats
1.
Four Fundamental Instruction formats are there in Alpha AXP.
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
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1.
2.
3.
4.
Operate Instructions.
Memory Instructions.
Branch Instructions.
CALL_PAL Instructions.
All Instructions are 32-bit wide.
They reside aligned long word addresses.
Each Instruction contains 6-bit Opcode. And zero to three 5-bit
Register-number fields, RA,RB,RC.
The remaining bits contains function (opcode extension), Literal,
or Displacement fields. RB is never Written and RC is never
Read.
Operate Instructions
Instruction format:
 There are five groups of register-to-register operate instructions : Integer, Arithmetic,
logical, byte manipulation and miscellaneous instructions.
 All Operate Instructions are three-operand register- to-register instructions and
operate on 64-bit Quadwords unless otherwise specified.
 The Instruction is in the form of RC=RA Operate RB.
 In Integer operates , the opcode and a 7-bit function field specify the exact operation.
 Integer operates may have an 8-bit zero-extended literal instead of RB.
Integer Arithmetic: add, subtract, multiply, compare
Floating-point Arithmetic: add, subtract, multiply, compare, convert
Logical Instructions: AND, OR , XOR, ANDNOT, ORNOT, XORNOT
Memory Instructions

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Memory Format Instructions are used for loads, stores, and a few
miscellaneous operations.
Loads /Store are two operand Instructions, Specifying Register RA and a
base-displacement virtual byte address.
The effective address calculation sign extends the 16-bit displacement to 64
bits and adds the 64-bit RB register.
The resultant virtual byte address is mapped to the physical address.
The miscellaneous instructions makes the other uses of RA,RB registers.
Instruction Format:
Branch Instruction

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Branch Instructions specify a single
register RA and a signed PC-Relative
Longword displacement.
The branch target calculation shifts the
21-bit displacement left by 2 bits to
make it long word displacement then
sign extends it and adds to the updated
PC.
Conditional branch instructions test
register RA, and unconditional
branches write the updated PC to RA
for subroutine linkage.
Calculated jump instructions write the
updated PC to RA and then jumps to
the target address in RB.
CALL_PAL Instruction
31
26
0
Function
OP
6
26
Instruction Format
 Call privileged architecture library functions.
 The CALL_PAL Instructions has only a 6-bit opcode and a 26-bit function
field.
 The function field is a small integer specifying one of a few dozen privileged
architecture library routines.
More about Alpha AXP in Business

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Compaq purchased DEC and Tandem
 Compaq server groups supported Alpha, MIPS
and Pentium Xeon
June 2001, Compaq announced the end of Alpha
 Alpha processor development cancelled after 2003
 Alpha-based system development cancelled after
2004
Alpha software teams at Compaq slated to target
Intel’s Itanium
References and Acknowledgements
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Sites, R.L., “Alpha AXP Architecture”, Digital
Technical Journal, Vol.4, No.4, 1992.
Oliver Hampton, CS 573 Spring 2003
Shyam Bukha, CS 573 Spring 2004
http://www.cs.panam.edu/7Emeng/Course
/CS4335/Notes/master/node95.html
Questions