HARDROC 3 for SDHCAL
02 / 02 / 2014 - HGC4ILD Workshop
OMEGA microelectronics group
Ecole Polytechnique CNRS/IN2P3 , Palaiseau (France)
Organization for Micro-Electronics desiGn and Applications
ROC chips for ILC prototypes
SPIROC2
Analog HCAL (AHCAL)
(SiPM)
36 ch. 32mm²
 ROC chips for technological prototypes: to
study the feasibility of large scale,
industrializable modules (Eudet/Aida funded)
June 07, June 08, March 10, Sept 11
HARDROC2 and MICROROC
Semi Digital HCAL (sDHCAL)
(RPC, µmegas or GEMs)
64 ch. 16mm²
Sept 06, June 08, March 10
 Requirements for electronics
 Large dynamic range (15 bits)
 Auto-trigger on ½ MIP
 On chip zero suppress
 108 channels
 Front-end embedded in detector
 Ultra-low power : 25µW/ch
SKIROC2
ECAL
(Si PIN diode)
64 ch. 70mm²
March 10
2
From
nd
2
generation…
 2nd generation chips for ILD
 Auto-trigger, analog storage and/or digitization
 Token-ring readout (one data line activated by each
chip sequentially)
Time between two bunch crossing: 337 ns
 Common DAQ
Time between two trains: 200ms (5 Hz)
 Power pulsing : <1 % duty cycle
time
0e
v
nt
1e
ve
Chip 2
nt
Chip 1
0e
ve
en
t
ts
en
Chip 0
3e
v
5e
v
en
ts
Train length 2820 bunch X (950 µs)
Chip 3
Chip 4
Data bus
Acquisition
A/D conv.
DAQ
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
198ms (99%)
99% idle cycle
1% duty cycle
Chip 0
Acquisition
A/D conv.
Chip 1
Acquisition
A/D conv.
IDLE
Chip 2
Acquisition
A/D conv.
IDLE
IDLE MODE
Chip 3
Acquisition
A/D conv.
IDLE
IDLE MODE
Chip 4
Acquisition
A/D conv.
IDLE
DAQ
IDLE MODE
IDLE MODE
DAQ
IDLE MODE
DAQ
IDLE MODE
3
…To
rd
3
generation
 3rd generation chips for ILD
 Independent channels (zero suppress)
 I2C link (@IPNL) for Slow Control parameters and triple voting
- configuration broadcasting
- geographical addressing
 HARDROC3: 1st of the 3rd generation chip to be submitted
– Received in June 2013 (SiGe 0.35µm) (AIDA funded)
– Die size ~30 mm2 (6.3 x 4.7 mm2) - Packaged in a QFP208
RPC cross section
1m2 RPC [IPNL]
4
HR3: Simplified schematics
64 ch a n n e ls
H o ld
64 channels with current preamplifiers

Trigger less mode (auto trigger 15fC up
to 10pC)


Gain correction (max factor 2)
Gain co rre ctio n
8 b its /ch a n n el
Cte st ch< j>
Slow Ctrl
B ipo la r FAST
Sha pe r 0
2pF
R e ad
V th 0
V th 0 : 1 0 fC to 1 0 0 fC
B ipo la r FAST
Sha pe r 1
Cte st_Chj
V th 1
La tch
RS
D0
D iscri.
B ipo la r FAST
Sha pe r 2
V th 2
I2C link for Slow Control
R e ad
m as k 1
m as k 2
trig g er0
trig g er1
trig g er2
trig g er1< j>
R e ad C h j_trig 2
La tch
RS
D2
C h j_trig 1
n o r6 4 _1 _<j>
D iscri
V th 1 : 1 0 0 fC to 1 p C
3 shapers + 3 discriminators (encoded in
2 bits for readout)
trig g er0< j>
La tch
RS
D1
C h j_trig 0
n o r6 4 _0 _<j>
m as k 0
V th 2 : 1 p C to 1 0 p C

M u ltip le x
C h arg e o u tp u t
S LO W S h ap er
V ariab le
G ain P A
Chj
R e ad
+

n o r6 4 _2 _<j>
trig g er2< j>
e n co d 0 <j>
RAM
E N CO D E R
e n co d 1 <i>

Independent channels with zero
suppress
trig g er0< j>
1 2 B it co u n te r B C ID
trig r0< j>
v a lid _ trig 0
trig g er1< j>
W R _ M E M < j>
trig r1< j>
v a lid _ trig 1
trig g er2< j>


Max 8 events / channel with 12-b time
stamping
Integrated clock generator: PLL
Power pulsing mode
1 D ig ita l M e m o ry/ ch
trig r2< j>
v a lid _ trig 2
D IG ITA L PA R T
Com m on to the 6 4 channe ls
n o r6 4 _0 <0 :6 3 >

8 e v e n ts
x
(1 2 + 2 ) b its
n o r6 4 _1 <0 :6 3 >
n o r6 4 _2 <0 :6 3 >
OR64
D AC2
1 0 b its
V th 2
D AC1
1 0 b its
V th 1
D AC0
1 0 b its
V th 0
5
Analog Part: FSB Linearity
Fast shaper outputs (mV) vs Qinj (fC)
50% trigger efficiency (DAC units) vs
Qinj (fC)
FSB0: 5s noise limit= 15 fC
FSB0
FSB1
FSB2
Up to 10 pC
Dynamic range: 15fC - 50 pC
Up to 50 pC
6
Gain correction / Scurves
Qinj=100fC
HR2 gain
correction
50% point
± 25fC
50% point
± 5fC
HR3: extracted
50% Scurves
point vs Channel
number
Before: ± 17 DACU
After: ± 8 DACU
(± 6 fC)
7
New Slow Control: I2C
•
I2C standard protocol access (max 127 chip / line)
•
•
Possibility to broadcast a default configuration to all the chips
Read and write access to a specific chip with its geographical address
•
•
Triple voting for each parameter (redundancy)
Read back of control bit (even if the chip is running / copy)
Master
Slave
Slave
Slave
Slave
1
2
3
x
Clock
Data
Write frame:
S
Slave address
W A Reg address
A
S
Slave address
W A Reg address
A P
S
Slave address
R A
A P
data
A P
Read frame:
data
8
I2C measurements
- I2C Write acces : Chip number (ID): 0xE2 / Reg @: 0x73 / WrData: 0x83
- I2C Read acces : Chip number (ID): 0xE2 / Reg @: 0x73
9
PLL measurements
 2 clocks are needed to start the chip
 Slow Clock (1-10 MHz) related to the beam train
(for Time stamping and data readout)
 Fast clock (40-50MHz) for internal the state
machines
5MHz  40 MHz
 A PLL (clock multiplier) has been designed
to generate the fast clock
 Multiplication factor is (N+1) / N is a SC
parameter (1 to 31)
 Full chain tested using PLL
PowerOnD
50
Duty Cycle in % vs OutFreq in MHz
Freq input fixed @ 5MHz
Tlock = 260 µs
Duty Cycle in %
49
48
Out_PLL
47
46
45
10
20
Output
frequency in30MHz
40
1
0
Zero suppress: Memory mapping
•
•
Chip ID is the first to be outputted during
readout (MSB first)
MSB of each word indicates type of data:
–
•
B C ID + C ha rge
of C H 62 : m a x 8 w ords
A parity bit/word
B C ID + C ha rge
of C H 1 : m a x 8 w ords
•
•
Up to 9232 bits (577x16) during readout
B C ID + C ha rge
of C H 0 : m a x 8 w ords
Example of number of bits during
readout:
HR2
HR3
1 chn hit
160
48
8 chn hit
1280
272
4 chn hit @ same time
160
144
10 chn hit @ same time
160
336
G e ne ra l da ta :
m a x 64 w ords
0
B C ID c hn 63 : 12 bits
E 1 E 0 P 576
0
0
B C ID c hn 63 : 12 bits
B C ID c hn 62 : 12 bits
E1 E0 P
E1 E0 P
0
B C ID c hn 62 : 12 bits
E1 E0 P
0
B C ID c hn 1 : 12 bits
E1 E0 P
0
0
B C ID c hn 1 : 12 bits
B C ID c hn 0 : 12 bits
E1 E0 P
E1 E0 P
0
B C ID c hn 0 : 12 bits
E1 E0 P
1 0
C hn # (6 bit)
# e vt 4b
0 0 0
P
1 0
C hn # (6 bit)
# e vt 4b
0 0 0
P
1 1 0 0 0 0 0
15
0
7-bit C hipID
7
R E A D (re a d o u t)
–
“1”: general data (Hit ch number and number of
events)
“0”: BCID + encoded data
B C ID + C ha rge
of C H 63 : m a x 8 w ords
P
0
0
Zero suppress: Tests
•
Zero suppress (only hit channels are readout): test OK
Signal injected ch 20 and ch 43
•
Roll mode SC : test OK
–
If RollMode = “0”  Backward compatibility with 2Gen ROC chips behavior
•
–
Only the N first events are stored
If RollMode = “1”  3Gen ROC chips behaviour
•
•
Use the circular memory mode
Only the N last events are stored
• “Noisy Evt” SC: 64 triggers => Noisy event => no data stored : test OK
• “ARCID” SC (Always Read Chip ID): test OK
–
–
If ARCID = 0  Backward compatibility:
If ARCID= 1  New behavior:
No event  No readout
No event  Read CHIP ID
12
Power pulsing in HR chips

•
Power pulsing:
 Bandgap + ref Voltages + master I: switched ON/OFF
 Shut down bias currents with vdd always ON
Compared to HR2, HR3 power consumption is higher due
to:
–
–
•
The extended dynamic range (from 15pC to 50pC)
The integration of the zero suppress algorithm
PWR ON
If the PLL is used, the power consumption is increased by
3% (due to the PLL VCO)
HR3 with LVDS
HR2 with LVDS
(5M + 40M)
µW / channel
(5M + 40M)
µW / channel
PowerOnA (Analog)
1650
1325
Only PowerOnDAC
55
50
Only PowerOn D
725
50
Power-On-All
2430
1425
Power-On-All
@ 0,5% duty cycle
12,2
7,5
Power supply
25 µs
HR2
Trigger
DAC output (Vth)
1
3
Power pulsing: Testbeam HR2
– SDHCAL technological proto with up to 50
layers (7200 HR2 chips) built in 2010-2011.
– Scalable readout scheme successfully tested
– Complete system in TB with 460 000 channels,
AUTOTRIGGER mode and power pulsing (5%)
1m2 RPC [IPNL] – 144 ASICS
1 m3 RPC detector, 40 layers
370 000 channels
Vth0 Vth1 Vth2
@IPNL Lyon
1
4
Summary and next steps
 Good analog performances
 Dynamic range extended up to 50 pC
 Circuit is able to work with only 1 external clock (thanks to PLL)
 New I2C tested successfully
 New digital features validated on testboard
 Zero suppress, roll mode, ARCID mode and Noisy event mode
 External trigger available to be able to check the status of each channel
 Next steps
 Production run (HR3 + 11 others chips) will be submitted mid-February 2015
 2-3m long RPC chambers to be built and equipped with HR3 in 2015
 Moving SPIROC / SKIROC to 3rd generation
 Much more complicated due to internal ADC / TDC / SCA management
 Integration and tests of HR3 on the 2-3m long RPC will be very helpful
15