DØ RunIIb Trigger Upgrade
Vivian O’Dell, FNAL
for the DØ Trigger Upgrade Group
1
DØ Collaboration Meeting
October 10, 2003
Run IIb Trigger Upgrades
 Strategy and Motivation


Latest Luminosity Predictions
Basic trigger upgrade strategy
 Technical progress
 Installation/Commissioning plans
 Summary
2
DØ Collaboration Meeting
October 10, 2003
Run IIb Luminosity
Projections
Peak Luminosity (x1030cm-2sec-1)
300
~2.8e32
Accelerator draft plan:
Peak luminosities
250
200
You are here
Peak FY03 ~4.5e31
~1.6e32
150
100
50
0
3
3
4
5
6
7
8
9
Start of Fiscal Year
10
DØ Collaboration Meeting
October 10, 2003
Core Trigger Menu
Simulations
1E32
Trigger
EM
(1 EM TT > 10 GeV)
Di-EM
(1 EM TT > 7 GeV, 2 EM TT > 5
GeV)
Muon
(muon pT > 11 GeV + CFT Track)
Di-Muons
(2 muons pT > 3 GeV + CFT
Tracks)
Electron + Jets
(1 EM TT > 7 GeV, 2 Had TT > 5
GeV)
Muon + Jet
(muon pT > 3 GeV, 1 Had TT > 5
GeV)
Jet+MET
(2 TT > 5 GeV, Missing E T> 10
GeV)
Muon + EM
(muons pT > 3 GeV+ CFT track +
1 EM TT > 5 GeV)
Single Isolated Track
(1 Isolated CFT track, pT > 10
GeV)
Di-Track
(1 isolated tracks pT > 10 GeV, 2
tracks pT > 5 GeV, 1 matched with
EM energy)
4
Total rate:
Example Physics
Channels
W  e , SUSY,
WH  ejj
Z  ee, W ,
SUSY

ZH
eejj
W  
WH  jj
Z J
2E32
2E32
L1 Rate
(kHz)
(no upgrade)
L=1E32
0.65
L1 Rate
(kHz)
(no upgrade)
L=2E32
1.3
L1 Rate
(kHz)
(with
upgrade)
0.7
Total L1 bandwidth
budget= ~3 kHz
0.25
0.5
0.1
Additional
headroom
available from
3
6
0.4
0.2
0.4
< 0.1
0.4
0.8
0.2
WH  +jets
tt  +jets
<0.1
< 0.1
< 0.1
ZH   bb ,
1.1
2.1
0.8
<0.1
< 0.1
< 0.1
8.5
17
1.0
0.6
0.6
<0.1

ZH jj
WH  e+jets
tt  e+jets
SUSY
HWW, ZZ
H W  
H  
• topological
cuts available in
upgraded L1cal
•Higher mu pT
threshold with
upgraded CTT
SUSY
~15kHz ~30kHz ~3.2kHz
DØ Collaboration Meeting
October 10, 2003
Ingredients of the Trigger
Upgrade
 Level 1

Calorimeter trigger upgrade



more topological cuts
Calorimeter track-match



sharpens turn-on trigger thresholds
fake EM rejection
tau trigger
L1 Tracking trigger upgrade


improved tracking rejection esp. at higher occupancies
inputs to Calorimeter track-mathc
 Level 2


L2 Processor upgrades for more complex algorithms
Silicon Track Trigger expansion


More processing power
use trigger inputs from new silicon layer 0
 Upgrade/maintain DAQ/Online systems
5
DØ Collaboration Meeting
October 10, 2003
The L1Cal Team
Saclay


Physicists:
Engineers:
Columbia/Nevis


Physicists:
Engineers:
Michigan State


Physicists:
Engineers:
Northeastern

Physicists:
Fermilab

Engineers:
ADFs/ADF Timing/Splitters
J.Bystricky, P.LeDu*, E.Perez
D.Calvet, Saclay Staff
TABs/GABs/VME-SCL
H.Evans*, J.Parsons, J.Mitrevski
J.Ban, B.Sippach, Nevis Staff
M.Abolins*
D.Edmunds, P.Laurens
Framework/Online Software
Online Software
D.Wood
Test Waveform Generator
G.Cancelo, V.Pavlicek, S.Rapisarda
* L1Cal Project Leaders
6
DØ Collaboration Meeting
October 10, 2003
Run IIa Limitations

Poor Et-res. (Jet,EM,MEt)

slow turn-on curves


5 Gev TT thresh  80%
eff. for 40 GeV jets
low thresholds 
unacceptable rates at
L = 21032
Trigger
Rate (kHz)
EM Trigger
W  ev
1.3
Jet Trigger
ZH  vvbb
2.1
(L = 2e32)
1 TT>10 GeV
2 TT>5 GeV
+ MEt>10 GeV
7
Phys. Chan
L1 Rate Limit
<5 kHz
DØ Collaboration Meeting
October 10, 2003
Run IIb Solutions (2)
 Solution for Rates:
Sliding Windows Algorithm





Et cluster local max. search
on 4032 () TT grid
Jet, EM & Tau algo’s
Better calc of missing Et
Topological Triggers
Jet, EM clust output for
matching with L1 Tracks
Data Needed for
Declustering
Jet Algo
ET Cluster
Region


8
ZHvvbb Rate:
2.10.8 kHz
Similar gains for EM & Tau
MEt, Topological Triggers
under study
O
O
O
O
O
O
O
O
O
O
X
O
O
O
O
O
O
O
O
O
O
O
O
EM Algo
2.5–3 Jet Rate reduction
at constant efficiency

O
Cand. RoI center
 Benefits

O
RoI
RoI center used for
compares
Tau Algo
Had Isolation
X
EM + Had
Isolation
X
EM Isolation
RoI / EM cluster
RoI / Tau cluster
DØ Collaboration Meeting
October 10, 2003
Technical progress: L1Cal
ADC+digital filtering
Clustering
Global sums &
topological
9
DØ Collaboration Meeting
October 10, 2003
Signal Splitter
 Access to Real TT Data
using “Splitter” Boards




designed/built by Saclay
active split of analog
signals at CTFE input
4 TTs per board
installed: Jan. 2003
 Splitter Data


10
no perturbation of Run
IIa L1Cal signals
allows tests of digital
filter algorithm with real
data
DØ Collaboration Meeting
October 10, 2003
ADF Prototype
VME
Digital Out
Analog In
Channel Link
Serializers
VME interface
& glue logic
Analog
Section
and
ADCs
Core FPGA
logic
DC/DC
converters
~1300 components on both sides of a 14-layer class 6 PCB
11
DØ Collaboration Meeting
October 10, 2003
TAB Prototype
Channel Link Receivers (x30)
Sliding Windows
Chips (x10)
power
VME/SCL
Output to GAB
ADF Inputs (x30)
L2/L3 Output
(optical)
Output to
Cal-Track (x3)
Global Chip
Internal Functions ~Fully Tested
12
DØ Collaboration Meeting
October 10, 2003
VME/SCL Board

New Comp. of TAB/GAB system



proposed:
change control:
Interfaces to



not enough space on TAB for
standard VME
D0 Trigger Timing (SCL)
(previously part of GAB)
Why Split off from GAB



simplifies system design &
maintenance
allows speedy testing of
prototype TAB
Prototype at Nevis: May 12

main VME & SCL functionality
tested & working
serial out x9
(VME & SCL)
13
VME
interface
VME (custom protocol)


Feb 03
Mar 03
local osc’s & f’out
(standalone runs)
SCL
interface
Fully Tested
DØ Collaboration Meeting
October 10, 2003
TAB/GAB Test Card
TAB/GAB Data Rates

TAB: LVDS


(channel link)
GAB: LVDS

(stratix)
424 MHz
636 MHz
Test Card at Nevis




14
power
Cyclone
TAB
(ADF sim)
VME /
SCL
Start Design
mid-Aug
Board at Nevis 29-Sep
Cost
~$2K
 Status

Channel Link
ADF-to-TAB xmit tested
before integration
Will test TAB-to-GAB
before sending out GAB
for fabrication
Stratix S10
LVDS
xmit/rcvr
Loopback
TAB
(GAB in sim)
DØ Collaboration Meeting
October 10, 2003
Prototype Integration Tests
 Want to start “System Tests” asap

need to check cross-group links early
 First Tests with Prototypes starting now



SCL  VME/SCL  TAB, ADF
BLS Data (split)  ADF  TAB
Flexible, staged schedule allows components to be included
as they become available
 Set up semi-permanent Test Area (thanks to J.
Anderson’s group at FNAL)



15
outside of Movable Counting House
connection to SCL, split data signals
allows L1Cal tests without disturbing Run IIa data taking
DØ Collaboration Meeting
October 10, 2003
Technical progress:
L1Cal-Track Trigger
 University of Arizona







J. Steinberg
D. Tompkins
C. Leeman
N. Wallace
B. Gmyrek
K. Johns
E. Varnes
 Exploit new L1Cal
trigger
 Improve Run IIa 
matching granularity x8
 Needed in triggers for
Higgs searches


electrons in WH and H
W*W modes
taus in H  and H+

 Fake EM rejection is
improved by ~x2
 Fake  rejection is
improved by ~x10
16
DØ Collaboration Meeting
October 10, 2003
Hardware Progress
 Block diagram of new
Univeral Flavor Board:
only really new board
needed for L1 caltrack Flavor board (daughter)
MTCxx (mother)
17
DØ Collaboration Meeting
October 10, 2003
L1CalTrack Status
 MTCxx (Trigger Cards)



Preproduction design complete
Layout and final checks in progress
Goal is to submit in November 03
 UFB (Flavor Board)





Prototypes in hand
Boundary scan and downloading OK
Receiver/transmitter testing in progress
L1MU “05” algorithm implemented in Stratix
EP1S20F780C7 (simulated but not tested)
H   algorithm implementation in progress
 MTCM (Crate Manger)

18
Not started, but only minimal changes to the existing
design
DØ Collaboration Meeting
October 10, 2003
L1CalTrack Status
 Infrastructure



VME crates, processors, power supplies, cables in hand
L1CTT to L1CalTrack cables being installed this weekend
(not terminated)
Rack space in MCH1 identified (but not settled)
 Commissioning


Plan is to use spare L1MU cards in L1CalTrack crates to
establish communication with TF and L3
Replace spares with L1CalTrack cards as available
 Simulator

19
Work has started writing the L1CalTrack package and
integrating it into the D0 Trigger Simulator
DØ Collaboration Meeting
October 10, 2003
L1CTT Upgrade
 Boston Univ



M. Narain
G. Redner
S. Wu
 Fermilab



M. Johnson
J. Olson
F. Borcherding
 Notre Dame

20
M. Hildreth
 Manchester


L. Han
T. Wyatt
 Kansas

G. Wilson
 Brown

R. Partridge
 Indiana

K. Stevenson
DØ Collaboration Meeting
October 10, 2003
Technical Progress:
L1Central Tracking Trigger
 Tracking trigger
rates sensitive to
occupancy
 Upgrade stategy:
 Narrow tracker
roads by using
individual fiber
hits (singlets)
rather than
pairing adjacent
fibers (doublets)
 Cal-track
matching
21
DØ Collaboration Meeting
October 10, 2003
L1 CTT Implementation

Digital Front End Axial (DFEA) daughter cards get replaced with new
layout with larger FPGA’s (Xilinx Virtex-II XC2V6000)



Only 80 daughter cards get replaced;
rest of Run IIa system remains intact
Baseline algorithms compiled; occupy ~40% of the resources of the
XC2V6000’s.
4.125”
40 mm
(1.57”)
7.8”
DFEA layout with
new FPGA
footprints
22
DØ Collaboration Meeting
October 10, 2003
Run IIb L1CTT Progress
 Implemented prototype firmware (Boston U)

Includes equation files from all 4 momentum bins

pT>10 GeV, 5<pT<10 GeV, 3<pT<5 GeV, 1.5<pT<3 GeV
 Resources used:

DFEA logic is implemented in two FPGAs
Prototype DFEA:
•10/17/03 prototype PCB
returned
•10/31/03 first prototype
assembled.
•11/30/03 prototype fully
tested
23
DØ Collaboration Meeting
October 10, 2003
•Run IIb strategy:
purchase additional,
more powerful
commercial
processors as late as
reasonably possible.
9U board
6U board
Compact PCI
64 bit
<2MHz
VME
J5
J4
Drivers
L2beta Upgrade
UII
J3
J2
ECL Drivers
J1
24
Clk(s)/
roms
FPGA
Drivers
64 bits
33 MHz
PCI
32 bits
66 MHz (max)
PLX Local bus
9656
128 bits
~20 MHz
MBus
DØ Collaboration Meeting
October 10, 2003
Silicon Track Trigger for Run
IIb

STT upgrade needed to

accommodate new L0?



New L0 fits within baseline Run IIb
upgrade
even without L0, increase
processing power for higher
occupancy
Modest STT upgrade requires small
quantity of same boards that are
used in Run IIa.
Readout layers 0,1,2,3,5
25
Technical Progress:
 VME Transition
Modules procured

Concern about
obsolescence
 Other procurements
awaiting Layer 0
decision
DØ Collaboration Meeting
October 10, 2003
Installation
 Words here about trigger installation

want to install as early as possible


most benefits
want to install during machine shutdown

where do we need the most access
 also repeat a little what we have in “the document”
on installation
26
DØ Collaboration Meeting
October 10, 2003
Summary
 Lots of trigger progress and potential
 Trigger workshop this weekend (Saturday/Sunday)

url
 trigger upgrade is being redefined in light of run2b
prospects



27
installation schedule
new project approval will be happening in the next month
workshop this weekend
DØ Collaboration Meeting
October 10, 2003
Backup slides follow
28
DØ Collaboration Meeting
October 10, 2003
Fake rate vs.luminosity
(1 high pT track)
Nominal 2E32
@ 396 ns
4E32 @ 396 ns
(1 high+1 medium pT)
Green
points =
Run IIa
CTT
Red
points =
Run IIb
CTT
 Even at modest occupancies, the high-pT
single track trigger would fire at >15 kHZ
29
DØ Collaboration Meeting
October 10, 2003
Run IIb L1CTT: Granularity
Run IIa
Run IIb
 Use full fiber resolution to restrict roads
30
DØ Collaboration Meeting
October 10, 2003
L1CalTrack System

31
Uses largely same hardware as existing L1muon
 modest cost and effort required
DØ Collaboration Meeting
October 10, 2003