The Stored Program Computer
Intro MIPS 1
1945: John von Neumann
–
–
Wrote a report on the stored program concept, known as the First Draft of a Report on
EDVAC
also Alan Turing… Konrad Zuse… Eckert & Mauchly…
The basic structure proposed in the draft became known as the “von Neumann machine”
(or model).
–
–
–
a memory, containing instructions and data
a processing unit, for performing arithmetic and logical operations
a control unit, for interpreting instructions
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von Neumann Model
Intro MIPS 2
stores both
program
instructions
and data
implements
a next state
function
Abstraction of von Neumann
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Memory
Intro MIPS 3
2k x m array of stored bits
Address
–
unique (k-bit) identifier of location
Contents
–
m-bit value stored in location
Basic Operations
LOAD
– read a value from a memory location
0000
0001
0010
0011
0100
0101
0110
1101
1110
1111
00101101
•
•
•
10100010
STORE
– write a value to a memory location
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Interface to Memory
Intro MIPS 4
How does processing unit get data to/from memory?
MAR: Memory Address Register
MDR: Memory Data Register
To LOAD a location (A):
–
–
–
Write the address (A) into the MAR.
Send a “read” signal to the memory.
Read the data from MDR.
M
E
M
O
R
Y
M
A
R
M
D
R
To STORE a value (X) to a location (A):
–
–
–
Write the data (X) to the MDR.
Write the address (A) into the MAR.
Send a “write” signal to the memory.
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Computer Organization I
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Hardware Level Organization
CPU
Major components:
- memory
- central processing unit
- registers
Intro MIPS 5
Main Memory
0
PC
MAR
IR
MBR
System
Bus
Instruction
I/O AR
Ex Unit
Instruction
Instruction
I/O BR
- the fetch/execute cycle
(the hardware process)
Data
I/O Module
Data
Data
n-1
buffers
PC
IR
MAR
MBR
I/O AR
I/O BR
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=
=
=
=
=
=
program counter
instruction register
memory address register
memory buffer register
I/O address register
I/O buffer register
©2006-09 McQuain, Feng & Ribbens
Central Processing Unit
Intro MIPS 6
Control
- decodes instructions and manages CPU’s internal resources
Registers
- general-purpose registers available to user processes
- special-purpose registers directly managed in fetch/execute cycle
- other registers may be reserved for use of operating system
- very fast and expensive (relative to memory)
- hold all operands and results of arithmetic instructions (on RISC systems)
- save bits in instruction representation
Data path or arithmetic/logic unit (ALU)
- operates on data
CS@VT September 2009
Computer Organization I
©2006-09 McQuain, Feng & Ribbens
Stored Program Concept
Intro MIPS 7
Instructions are collections of bits
Programs are stored in memory, to be read or written just like data
Main Memory
CPU
0
memory for data, programs,
compilers, editors, etc.
Instruction
PC
MAR
IR
MBR
Instruction
I/O AR
Instruction
Ex Unit
I/O BR
Data
Data
Data
n-1
Fetch & Execute Cycle
Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Fetch the “next” instruction and continue
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Stored Program Concept
Intro MIPS 8
Of course, on most systems several programs will be stored in memory at any given time.
On most contemporary systems instructions of only one of those will be executed at any
given instant.
Main Memory
CPU
PowerPoint pgm
(machine code)
PC
MAR
vim
IR
MBR
(machine code)
I/O AR
GIS source code
(data)
Ex Unit
I/O BR
g++
(machine code)
The operating system will rapidly switch among the eligible
processes, producing the illusion that several programs are
executing at the same time.
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Computer Organization I
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Fetch/Execute Cycle
Intro MIPS 9
Sometimes called the hardware process… executes continuously.
START
Fetch Stage
Execute Stage
Fetch Next
Instruction
Execute
Instruction
HALT
Steps:
- fetch an instruction from memory to the instruction register
- increment the program counter register (by the instruction length)
- decode the instruction (in the control unit)
- fetch operands, if any, usually from registers
- perform the operation (in the data path); this may modify the PC register
- store the results, usually to registers
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Simplified MIPS Datapath
Intro MIPS 10
ALU
Memory
Register File
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Memory
Computer Organization I
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Finite State Machine
Intro MIPS 11
So, where's the FSM?
Next
Instruction
Input
Execute
Instruction
Input
devices
Current
State
Output
devices
Contents of
registers and
memory
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Control Unit State Diagram
Intro MIPS 12
Here's a state machine diagram for the
MIPS control logic we'll be studying:
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©2006-09 McQuain, Feng & Ribbens