The Operating System and
the Central Processing Unit
4
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Although CS420 is not a hardware course, the OS
and the CPU are highly interdependent and indeed
must be designed with one another in mind, so you
need to know a little bit about the CPU and interrupts
(but only a very little bit, trust me ;-) to help make sense
of much of the OS, which is the actual point of CS420
Overview
the
CPU
IVT
the
OS
• A CPU-centric view of life and how it both supports and
controls the OS, including deciding when it gets to run
• The
hardware architecture
and instruction
• The
Interrupt
Vector Table
(IVT) –execution
where the CPU and
• Interrupts
and the System Status Register (SSR)
the
OS meet
• A complete biography of the CPU in one page of pseudo-code
• An OS-centric view of life on a CPU, including how it
both supports and controls the CPU
• Summary
MSJ-2
Architecture of a Simple CPU
4
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Cycle 1: Instruction Fetch
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cycle, the Program
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to memory
the CPU’s
Instruction
contains the
address
of theRegister (IR),
sometimes
known
as the Instruction
next instruction
we want
to execute
Decode Register (IDR)
MSJ-4
Cycle 2: Instruction Decode and Register Fetch
4
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Lots of other
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they’re
CPU’s functional units to control
theafter
rest that;
of thebut
execution
irrelevant
to usofhere
of this instruction − e.g., some
of the bits
the in CS420
instruction contain the operations code (opcode), which
tells the ALU whether it is to do an addition, subtraction,
multiplication, division, left shift, right shift, etc, etc
MSJ-5
Cycle 3: Execution or Address Calculation
4
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execution or
address calculation
• The ALU does not work directly with
data in memory; it only manipulates
data from the general purpose
registers, the Imm, or the NPC
MSJ-6
Cycle 4: Memory Access
4
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MSJ-7
Cycle 5: Write Back
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During write back, the results of the current
instruction’s calculations are written into the
execution or
instruction
decode &
appropriate
registers:
address calculation
register fetch
memory access
write
write
back
back
• The address of the next instruction we want
to execute is always written into the PC
After its write back, the execution of
• Results
from theinstruction
current instruction
canand
be
the current
is complete
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usually
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the address
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thatwant
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next register
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execute
for future instructions to use
MSJ-8
So Where and How Do Interrupts Fit
Into This Picture?
• Most of the time, a CPU just executes the instructions from
some program one instruction after another
• Sometimes, however, we need to interrupt a program to
handle something else right away − e.g., even though some
student program is contentedly grinding away in an infinite
loop, happily consuming 100% of the CPU time for the next
trillion years, we really need to shutdown the nuclear reactor
in the next few milliseconds or Los Angeles may disappear
• Interrupts will lead to all sorts of interesting issues for us
later in CS420
• To handle them, the OS will need some help from the
System Status Register (SSR), part of the CPU’s hardware
MSJ-9
Overview of a Simplified
System Status Register (SSR)
help me
disk controller
•
• Privileged software
can set a
user
nuclear
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timer
reactor
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areto generate
an interrupt
potentially so disruptive
to the efficient operation
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the
computer
system
that
they aretimer
only
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or
an
I/O
controller)
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•••Theof
•••
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that
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the
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see
how
in
a
few
slides
to
identify
the
specific
interrupt
so
the
the CPU
know or
when
code
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instruction
do aprivileged
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the
term
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•a Ifsystem
an
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byCS420
theto
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inisthe
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privileged
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an
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and
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bit
has
been
• The• An
SSR
bits
provide
the
OS
and
the
CPU
control
over
notthe
set,attention
the“interrupt”
CPU
will
declare
an error
reminder
for itself
to
do
the
attention
ofby
the
•isSometimes
orOS
“external
interrupt”
merely sets an IRQbitto
get
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the
previously
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the
OS
certain
of each
status
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to
(which
the OS
will have
toand
handle)
something
in
the
future
isother’s
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refer
only
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being
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when
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in which
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asbut
we’ll
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to may
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see an
on
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slide,
it only
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butSSC
ordoes
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setting
IRQ
the OSsee
running
cleared by the other,starts
etc;
these
• Thewe’ll
end resultexamples
is the same,ofhowever
various possibilities here and on the next slide
MSJ-10
A Complete Biography of the CPU in One
Page of Pseudo-code, Including Interrupts
while ( ! powerReady );
Nothing can happen until the
PC = startAddressOfBootProgram;
power supply reports that the
power is stable by setting the
clearInterruptsEnabledBit;
powerReady bit in the SSR
setPrivilegedModeBit;
The PC
is at
thethe
Program
in the (more or less non-fiction ;-)
• Let’s
look
more orCounter
less complete
• the
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else
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earlier
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be
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save
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animations
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interrupts
along
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way
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( ! (IRQ
&&
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)
completing
most
boot program
•ofWe
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want
to
get
interrupted
byof
a the
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we
were
just
about
to
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before
second
interrupt
right
at
the
startinof
{ CPU we’ll
/*the
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instruction
normally
*/
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The
here
is initializing
the
PCan
to
code
and
hence
needs
towill
describe
CPU’s
logic
here
pseudo-code,
since
we
got
interrupted
•
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boot
program
itself
eventually
servicing
apreparation
prior
one
Once
the
interrupt
processing
isan
the
start
address
of
the
boot
program,
execute
in
privileged
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there
instructionFetch(PC);
is •an
enabled
IRQ
present
justfor
before
theexecute
CPU
issues
easier
to
understand
than
logic
diagrams,
it is
not
software
figure
out
when
it’s
safe
to
enable
So
what
instruction
should
the
CPU
next?
Why,
complete,
the
CPU
continues
on
with
its
boring
•
Exactly
where
it’s
saved
is
hardware
which
is
the
first
set
of
instructions
we
instruction,
the
CPUinstruction
won’t
issue
that
instruction
but
instead
interrupts
andhardware
use
awill
software
instructionDecodeAndRegisterFetch();
• When
dodependent;
interrupts
get
re-enabled?
Why,
the
first
in
the
appropriate
ISR,
of
course,
so
•
Only
the
CPU
instruction
execution
loop,
having
just
set
the
•reconfigure
It
is
either
literally
hardwired
circuitry
or,
in
some
types
of
CPU
but
it
has
to
be
saved
want
to execute
after
power-up
•
Although
the
IRQ
bit
can
be
set
by
external
instruction
to
do
so
a couple
ofthat
bits
in
the
CPU
before
issuing
the first
that’s
up
to
software,
ofstart
course,
the
CPU
will
getthe
theISR
correct
ISR’s
address
from
anCPU
executionOrAddressCalculation();
can
set
this
bit
so
it
must
PC
so
the
next
instruction
issued
for
implementations,
microcode
–
but
that’s
not
a
CS420
concern
somewhere
so
the
operating
system
•
The
ISR
about
to
run
is
OS
software
so
the
hardware
at
any
time,
the
CPU
hardware
itself
whenever
the
ISR’s
programmer
decided
instruction
of
the
appropriate
interrupt
service
routine
(ISR),
an
OS
data
structure
called
the
Interrupt
Vector
Table
(IVT)
• We’ll
take
a
quick
look
at
the
boot
do
so
here,
before
itcontrol
issues
execution
will
be
the
start
of
the
correct
ISR
memoryAccess();
can
get
to
it
later
to
restore
to
must
turn
on
the
privlegedMode
bit
for
it
only
checks
for
interrupts
just
before
it
issues
itlater
wasitjob
safe
–program
and
we’ll
have
lots
think
and
put
(the
ISR’s
start
address)
intointerrupted
the
PC,
which means
OS
function
whose
is to
respond
to
(service)
some
particular
program
on
a
slide
the
first
instruction
ofbits
the
the
that
just
got
writeBack();
Once
the
control
and
status
and
the PC
a
new
instruction
to
start
its
execution
about
later
in
CS420
it will
be down
the
next
instruction
issued
•here
The
ISR
itself
will
turn
this bit offas
later
interrupt, e.g.,
shut
the
reactor
boot
program
and
let
it
resume
its
execution
if
have been initialized, the entire life of the CPU,
}
• But•even
if
the
IRQ
is step
set,
the
interrupt
willmore
not
nothing
had
happened
from
then
until
the
power
goes
off,be
consists
We’ll
look at this
and
the
IVT
in
detail
on
the of*/
else be serviced
/* Prepare
for
interrupt
processing
first
Instruction
execution
itself
must
atomic:
unlesslooping
the interruptsEnabled
gazillions
of times
through
the 5tocycles
next slide
Once
an
instruction
has
been
issued
the
clearInterruptsEnabledBit;
bit is also set
ofCPU
instruction
execution
which
we
saw
at the start of the instructionFetch
setPrivilegedModeBit;
animated
earlier;
even
thecomplete
boot program
itself
• Otherwise, the IRQcycle,
will beall
ignored
and
the
5
cycles
must
without
any
is
just
a
perfectly
ordinary
set
of
instructions
interruptedPC
=
PC;
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current
programor
will
be has been an a as
sort
of
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as
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CPU
concerned
and executed
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interrupt)
PC issued
= interruptVectorTable[interruptNumber];
or failure
some sort
}
MSJ-11
Roadmap
• A CPU-centric view of life and how it supports the OS
• The Interrupt Vector Table (IVT) – where
the CPU and the OS meet
• An OS-centric view of life on a CPU, including a clever analogy about how an OS is
like Sleeping Beauty and the CPU is Prince Charming
• Summary
MSJ-12
The Interrupt Vector Table (IVT)
How the CPU Launches an ISR for the Operating System
• The IVT is just a 1-dimensional array whose base
•• Note
that since
the interrupt
CPU hardware
starts an ISR
Thetake
CPU
uses
the
number
address
in a
memory
is known
to the
hardware
Let’s
more
detailed
look
at CPU
the last
step
of the CPU’s
executing
in
privileged
mode,
it
is
important
that
the
from thepreparation
SSR
as thesomeplace
index
into
(perhaps
it’s
stored
the
SSR by the
interrupt
from(offset)
the like
last
slide:
IVT
IVT
be
protected
from
unauthorized
modification
the
IVT,
so
in
this
last
step
of
at bootup,
hardwired,
but that’s
a
• OS
In summary,
theperhaps
IVT is an it’s
ordinary
array whose
contents
address of ISR0
toplace
service
an
interrupt,
the
• Ifpreparing
you
could
the
address
of one
of your
functions
CPU
design
issue,
not
a
CS420
one)
are
maintained
by
the
OS
and
used
by
the
CPU
PC = interruptVectorTable[SSR.interruptNumber];
CPU
setting
Program
Counter
so ISR
in
the isIVT,
code,
running
mode,
could
hardware
to your
find its
the
address
of in
theprivileged
correct
to start
that the
next
instruction
be
issued
• Each
entry
theorIVT
is to
aan
pointer
to IRQ
a function*, one
then
circumvent
modify
the
OS itself
whenever
theinCPU
detects
enabled
interruptNumber
be the
start ofinterrupt
the correct
ISR one ISR
forwill
each
different
– e.g.,
for the
•
So
the
OS
must
store
the
IVT
in
memory
that
user
• printer,
The IVT one
is thus
atthe
thenuclear
very heart
of the etc
integration
of the
for
reactor,
• mode
If the
were 6,
for usually in RAM, not
programs
can’t modify
– still
OS
withinterrupt
the CPUnumber
example,
the CPU
would
go tothat
thefurther
6th
ROM,
however
(we’ll
discuss
in a minute)
• The
OS,
any
of software,
consists
* Pointers
justother
addresses,
remember;
and although
you may of
or may
entry
inlike
theare
IVT
to
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the
starting
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memory
toinprovide
that
protection
not have
covered
them
CS125,
pointers
to
functions
arenot
legitimate
algorithms
and
data
structures;
and
you’ve
just
metonly
its
address
for
ISR
,
perhaps
the
one
that
6
data
types
in
C,
so
an
array
of
pointers
to
functions
is
a
perfectly
impacts
the hardware
design
butrather
will also lead to major
first
important
data
structure
shuts
down
the
nuclear
reactor
ordinary data structure in C, the language most OS’s are written in.
requirements
on
thethe
OS,
which
we’ll
cover in some
thanThe
thenext
one
to
tell
operator
the
slide
contains
a very
short demo
program that you can
detail
later
incompile,
CS420
download,
and execute, if you like; although we won’t be
printer
is out
of
paper
doing any programming of this sort this semester
address of ISR1
address of ISR2
address of ISR3
address of ISR4
address of ISR5
address of ISR6
address of ISR7
• Here we’re declaring an array of 3 function pointers; the name of the
Demo
Program for Function Pointers
array has no particular significance, of course, but since we were
about
the interrupt
vector
table,
letsthat
callthere’s
this demo
• Atalking
constant
theme
for CS420
is going
to be
no array
magic‘IVT’
• Note the difference between the expressions ISR1 and ISR1()
The
syntax
looks
odd, but
after
a like
while
oneit’s
gets
used
to itare usually
A real
ISRone
would
never
be
called
this;
started
by
••With
only
exception,
below,
OS
functions
these
days
ISR1
is perfectly
an
address
constant
the
CPU
hardware,
not
byarray
other
software,
ascomprehensibility
we are
in
ordinary
C,
although
is clearly
•••coded
Here
we’re
initializing
our
with
thetheir
addresses
of of
ourdifferent
3 demo
#include<stdio.h>
In
C,
one
can’t
declare
an
array
containing
variables
types,
affected
by
doing
in
this
demo
program
ISR
functions
/*
Simulated
ISR
(it
needn’t
be
named
‘ISR’
of
course);
it’s
address
in
memory
will
be
the
entry
for
IVT[0]
void
ISR0(void)
• so
ISR1()
isaddresses
the value in
(if an
any)
returned
by calling
the function
at to in ‘main’ */
all
the
array
of
function
pointers
must
point
printf("\n
from
ISR0,much
called
as (*IVT[0])()
\n");
}
• I{ don’t
want
toHello
spend
overly
time
on
this
code
in very
lecture,
although
address
ISR1
with
the
arguments
(if
any)
inside
the
parentheses
1.
The
comprehensibility
of
C
syntax
itself
(not
good,
actually)
functions
that
have
the
same
signature
–
i.e.,
the
same
type
• Just
Butgo
the
purpose
of
this
little
demo
program
is
just
to
•we’ll
asover
an
array
name
[with
no
square
brackets
after
it]
is
an
it briefly; but you won’t be writing code like this in of
CS420; I’ve
voidaddress
ISR1(void)
returned
value,
and
thedoes
same
number,
type,
and
order
parameters
show
you
that
Cdemonstrate
really
support
function
pointers,
/*address
This
one’s
address
inthe
memory
will beof
theso
entry
for IVT[1]
in ‘main’
constant
equal
to
the
base
of
array,
too
just
2.
The
skill
of
their
programmers
• included
If,
for
example,
for
some
odd
reason,
you
wanted
to
see
exactly
it
just
to
that
C
does
support
function
pointers
and */
{ printf("\nSimilarly,
Hello from
ISR1,
called
as
(*IVT[1])()
\n");
}
an(no
ISRargument
typically
doesn’t
arrays
of
function
pointers,
etc;
so here
are
calling like
the
name
of
a
function
list we
in parentheses
afterwill
it) is
where
in
memory
some
function
were
stored,
something
they’re
just
addresses
• Since
an
IVT
is
an
array
of
ISR
addresses,
this
demo
array
contain
3.ISR
The
extent
to
which
those
programmers
considered
have
parameters.
Who
would
•
An
typically
doesn’t
return
a
value;
there’s
our
functions
not
by
name
but
by
dereferencing
pointers
an
address
constant
for
the
first
instruction
of
the
function,
which
is
void
ISR2(void)
printf(“%d”,
ISR1)
would
doathe
aaddress
function
name
like
/* trick;
Thisno
one’sparameters
in memory will
be the entry
for IVT[2]no
in ‘main’
*/
only
addresses
of
functions
that
have
and
return
comprehensibility
to
be
virtue
(or
a
requirement)
supply
the
arguments?
• All
pointer
values
in
C
are
just
addresses,
of
course;
it’s
what
they
point
nojust
one
toHello
return
it to,
since
an
ISR
isn’t
called
{
from
ISR2,
called
as IVT
(*IVT[2])()
\n"); }
toprintf("\n
them,
each
pointer
being
anany
in an
array
exactly
what
we
want
in
aelement
real
ISR1
being
a would
constant
like
other
constant
values;
other
arrays
of
function
pointers
could
have
other
signatures
toBut
(their
type,
in function,
other
that
the compiler
to handle
by
another
which
is tells
the
normal
waynot
a how
that’s
true
of anywords)
C code,
OS
functions
are
unique
in this them:
regard
main()
•
Download,
compile,
and
run
this
program
to
see
that
it
de-referencing
integer
pointer
right
of(itan
assignment
operator
(=)
below, declares
and initializesto
whatthe
could
a real IVT
doesn’t
have to be named ‘IVT’,
of course);
function/*inThean
aline,program
consisting
of be
multiple
{ • Anyway,
the
only
other
“trick”
probably
haven’t
seenmakes
yetsense
in your
itexpected;
may look
strange, but
it's legal
Cyou
and ifcalls
you
thinkour
hard about
it, its syntax ISR
ultimately
*/
all
works
as
this
loop
3
demo
produces
an
integer
value;
dereferencing
a
function
pointer
anywhere
functions
gets
started
void
(*IVT[3])(void)=
{
ISR0,
ISR1,
ISR2
};
experience
withafter
C isthe
how
to insert
assembly
code – like, for
functions
one
other,
and
they
each language
printout
athen
produces
a
transfer
of
control
to
some
function
–
which
oramay
/* We'll use this integer
as the counter
in the SSC
'for' loop, –
below,
to call
each middle
of the may
functionsof
defined
above */
int
functionNumber;
example,
a uniquely
single
instruction
such
as an
into
the
C
•
Instead,
an
ISR
is
started
“automatically”
by
single
line
identifying
themselves
not
eventually
return
a dereferencing
value,
depending
on the
function
but
for
CS420,
we
won’t
doing
anything
/* function;
The 'for' loop, below,
just
demonstrates
of function be
pointers
in C; although
that’s not howlike
the CPUthat;
hardwareCS420
calls an ISR, of
the
CPU
hardware
to
get
an
enabled
interrupt
course.
To
actually
service
an
interrupt,
the
CPU
hardware
just
takes
the
contents
of
an
IVT
entry
and
stores
it
in
the
PC
so
it is the next
isinstruction
an OS
theory
course,
not a Con or
assembly
language
programming
issued.
As
we
saw
in
the
hardware
pseudocode
the
previous
two
slides,
no
software
is
involved
in
setting
the
PC
that way,
• Ifcourse;
you
like,it “byyou
can
download
code
from
thefunction
Blackboard
for
serviced
by
the
OS
only
reason
putthis
thisthat
stuff
in inhere
all byisdereferencing
just tosite
the CPU does the
itself”.
The code,
below justI demonstrates
C code can
fact call aat
a buttress
(function) pointer to it . */
CS420,
and
then
compile
itmagic;
and run
just
fun;beeach
of any
the three
for
= 0;no
functionNumber
< 3; for
functionNumber++)
my(functionNumber
point
that
there’s
butit you
won’t
doing
codingtrivial
like
(*IVT[functionNumber])();
ISR
functions
will
run
and
print
out
its
“Hello
from
ISR
…”
message
/*
This
line
picks
an
array
element
and
dereferences
it.
Since
the
compiler
knows
that
this (i.e., assembly language
or arrays of function pointers)
i in CS420 the
pointer being dereferenced is a function pointer (as opposed to, say, an integer pointer),
and none of this code or anything
it transfers
will be
on
any
exam
the compiled like
code then
control
to that
address,
thus calling that function
*/
}
MSJ-14
Roadmap
• A CPU-centric view of life, and the hardware it devotes to supporting the OS
• The Interrupt Vector Table – where the CPU and the OS meet
• An OS-centric view of life on a CPU
or
How the Operating System is like Sleeping Beauty
to the CPU’s Prince Charming
• Summary
• A one
page biography of the life of the OS
• The boot program and subsequent initializations
• Interrupt servicing
• Other important stuff to do after an interrupt
(like all the rest of CS420, in other words)
MSJ-15
A One Page Biography of the OS
• At this level of abstraction (one page), the OS’s life story
looks even simpler than the earlier, one page, pseudo-code
description of the CPU’s logic
• Here’s an abridged version of the entire life story of the OS:
1. Boot-up – load the OS into memory
2. Go to sleep and wait for an interrupt to wake up
(like Sleeping Beauty waiting for a kiss)
A. Service the interrupt
B. After servicing the interrupt but before returning the CPU to the
interrupted code, look around for other interesting things to do
MSJ-16
Boot-Up
ROM
instr.
memory
?
RAM
boot disk
data
memory
IVT
There’s
also an
optional,
not
particularly
standard,
but also not
•• As
we
saw
during
the
earlier
instruction
animation,
particularly interesting, initialization phase that some OS’s may
• The ROM portion
of the bootmust
programfetched
is fairly simple-minded;
instructions
to be
executed
sometimes allow
called
sysgen (systembe
generation);from memory
• The
program
seem
more complicated
than
it really
merely
all boot
it does
is go may
out to
a predetermined
place
(the
bootissector)
because
it aislot
often
quite
time-consuming
•• Since
high
speed
RAM
is(the
volatile,
the contents
There
of parameters
that
a knowledgeable
sysadmin
can are
on aare
predetermined
disk
boot
disk)
and load
aof RAM
fiddle
with to
control
thebecause,
behavior
of an
– portion
e.g.,
maximum
ofOS
right
power-up;
soOS
no
OS
predetermined
amount
of code
from
there
into
aofpredetermined
• undefined
Boot
times
can
be after
long
among
other
reasons,
itthe
cannumber
takecan
the
users
to logsomething
in what
concurrently
–are
some
of these
parameters
can
some
time
to discover
devices
connected
so itor
knows
location
in
RAM
be
in allowed
RAM
until
loads
itactually
there
from
a disk
other
be
adjusted
at
any
time,
others
only
during
boot-up
what ISR’s to load
and have their addresses inserted into the IVT
non-volatile
device
• The newly
loaded
OS
software
now
in RAM then
does
the to
more
(“Helllloooo,
printer,
are
you
there?
Say
waaiiiiting.”)
• Sysgen
essentially
just
involves
giving
a something.
sysadmin
anI’m
opportunity
complicated
jobOS
ofisfinding
the program
rest
of thebe
necessary
OS
• That
“something”
the boot
and
at least
the normal
first
fiddle
with any key
parameters
that can’t
adjusted
during
functions
ononly
the
disk, during
loading
them
into
and initializing
operations
but
early
boot-up
−memory,
e.g., non-volatile
for Windows,
part
of it must
therefore
be OS
stored
in
some
(ROM)
any data
structures
the
IVT, for
example)
thatyou
require
holding
down
theinstruction
F8 key(like
during
bootup
tells
the OS that
want to do
portion
of the
memory
dynamic
initialization
some
sysgen-like
thing before finishing the boot process
MSJ-17
Sidebar: Origin of the Phrase “Booting”
• Since the ROM code that starts the load of the
(rest of) the OS from disk is itself part of the OS,
it apparently seemed to the founding fathers of
OS theory that, in its loading of itself, the OS
was “lifting itself up by its own bootstraps”
• That’s not really technically correct, of course; but that little
piece of the OS in ROM needs to be called something and
“boot program” is both semi-apt and picturesque; it obviously
caught on and is hence here to stay, accurate or not
MSJ-18
Another Sidebar: The OS and ROM
• Why not just put all the OS in ROM and simplify the startup
process? (Be better for security, too; wouldn’t it?)
• So why do you even need to ask that question? Either:
1. You haven’t noticed Microsoft issuing “critical security updates”
to XP about once a week or so for the last 10 years, or
2. You have happily been prying the OS ROMs out of their
sockets on your mother board once a week and running down
to your local Microsoft dealership for replacements
• Electrically erasable, programmable, read-only memory
(EEPROM) solves this problem, but it’s too slow for use as
the instruction memory for a high performance OS for general
purpose computer systems, although it’s obviously good
enough for cell phones and the like
MSJ-19
Anyway, Moving On: Sleeping Beauty
and the Life of the OS After the Boot
boot
OS not running,
(user code running)
Sleeping Beauty
ISR
interesting
and important
OS stuff
The very last thing an ISR does is to reset
After it’s
done
servicing
its
justas
the important
stuff
all
• A modern,When
general
purpose
OS
thus
often
described
the all
PC
toisis
the
address
ofinterrupt,
the instruction
before
it completely
terminates,
an ISR
will
done,program
control
returns
to the
ISR
that
was
just
about
to beinitializing
issued
just
prior
• being
After the
boot
finishes
loading
and
all the
“interrupt
driven”
often
call
other
OS
functions
to
look
around
so that it can restore
the
CPU to thus resuming execution
to the
interrupt,
necessary
pieces,
the
OS
becomes
a and
Sleeping
Beauty
will
be
an
interrupt
Prince
Charming
and
see
if
there’s
other
important
OS
stuff
to do
the there
interrupted
code
•Eventually,
Even though
the really
interesting
and
important
stuff
we’ll
be
of the interrupted program, which
is studying
also
waiting
for
an
interrupt
to
wake
it“restoring”
up,
meanwhile
letting
the
(likehas
everything
else
this
ininterrupts,
CS420
(the
CPU)
will
dispatch
some
thus
awakening
the
the rest
of this
semester
nothing
to do
withsemester
servicing
known
asISR,
or
“returning”
the ;-)
CPU
be
used
tothe
run
user
code
OS
to service
interrupt
CPU
to the interrupted
(which
is
actually
only
a small,
though
important, program
part of the OS’s job),
it nonetheless
is justuser
codecode
and it to
only
actually
runs
after an interrupt
• If there
is no “real”
run,
there
is usually
a built-in
system
idle
of some
sortfact
– that
but it’s
it presumably
runs
in
• The OS
justprogram
takes advantage
of the
already running
to see
user
mode,
so whether
or notstuff
it isit really
reallyought
part toofdo
the OS is
if there’s
other,
more important
probably a pointless question
• An OS runs once at boot-up and then only after an interrupt;
that’s it
MSJ-20
But the Sleeping Beauty Metaphor Aside,
Interrupt Driven Does Not Mean That the
OS is Purely Passive
• One of the “interesting and important” things the OS can
do is to use a privileged mode instruction to set a
countdown timer in the SSR (or someplace equivalent) to
generate a future interrupt
• The point being that even though the post-boot OS is
interrupt driven, it would be misleading to think of it as
merely a slave to the external world
• It can schedule interrupts of its own to ensure that it also
runs at times of its own choosing, as well as in response to
truly random external events
MSJ-21
Roadmap
• A CPU-centric view of life and how it supports the OS
• The Interrupt Vector Table (IVT) – where the CPU and the OS meet
• An OS-centric view of life on a CPU, including a clever analogy about
how an OS is like Sleeping Beauty and the CPU is Prince Charming
• Summary
MSJ-22
Summary: The OS and the CPU
Are Highly Interdependent
• The CPU is what starts the OS running and sets up SSR
bits so that the OS starts properly – e.g., in privileged mode
• The OS sets bits in the SSR that control how the CPU
works (e.g., will it accept interrupts) and sets up the IVT so
that the CPU starts the right ISR whenever an interrupt
needs to be serviced
• The OS can use a countdown timer in the CPU to schedule
itself for whenever it calculates it needs to run, as well as
running whenever something else needs it to run
• Other than after power-up, the CPU only runs the OS in
response to interrupts/traps, which can be generated:
1. By hardware events both internal and external to the CPU
2. By user mode software whenever it needs OS services
MSJ-23
Summary (cont’d)
Often, most of the OS processing that actually takes place
after an interrupt really has nothing to do with servicing the
interrupt; the OS just uses the fact that it’s already running
to look around and see if there’s something else important it
ought to do, like all the stuff we’ll be discussing for the rest
of a semester of CS420
MSJ-24