A Design Approach for
Radiation-hard Digital
Electronics
Rajesh Garg
Nikhil Jayakumar
Sunil P Khatri
Gwan Choi
Department of Electrical and Computer Engineering,
Texas A&M University, College Station, TX-77840
1
Outline
Introduction
 Objective
 Previous Approaches
 Our Approach
 Results
 Conclusions

2
Introduction

There has been significant interest in the radiation
immunity of electronic circuits



Historically mainly used for space and military electronics
Higher levels of radiation in space and combat
environments
More recently, terrestrial electronics are also
becoming vulnerable



Shrinking feature size and supply voltages
Reduced capacitances means less charge is required to flip
node voltage
This has led to a renewed interest in radiation tolerant circuit
design
3
Introduction (contd.)

Effects of radiation particle strike





Neutron, proton and heavy cosmic ions
Ions strike diffusion regions
Deposit charge
Results in a voltage spike
What is Single Event Upset (SEU)?

Interaction of a radiation particle with VLSI circuits can
produce a charge deposition in critical regions of the
circuit, leading to a bit reversal error, or single event upset.
4
Introduction (contd.)

Charge deposited (Q) at a node is given by
where: L is Linear Energy Transfer (MeV/cm2/mg)
t is the depth of the collection volume (mm)

Resulting current pulse is modeled as
where: ta is the collection time constant
tb is the ion track establishment constant
5
Objectives



Radiation particles cause SEU
Terrestrial electronics are also susceptible to
SEU
Therefore, need circuit level protection against
SEU even for consumer electronics


To make circuit radiation tolerant
Delay and area overhead should be minimized
6
Previous Approaches

Transistor sizing is done to improve the radiation
tolerance of the design (Zhou et. al)





Ensure that capacitance of any node is sufficient to make
the circuit radiation tolerant.
SEU event is detected using built in current sensor
(BICS) (Gill et. al)
Triple modulo redundancy based approach
(Neumann et. al)
Error correction codes (Gambles et. al)
More detailed references can be found in the paper
7
Our Radiation Hardening
Approach

Part 1: Gate Level SEU protection



Approach A: PN Junction Diode based SEU Clamping
Circuits
Approach B: Diode-connected Device based SEU
Clamping Circuits
Part 2: Logic Block Level Protection



Radiation hardening for all gates
Fixed depth protection
Variable depth protection
8
Our Radiation Hardening
Approach

Approach A - PN Junction Diode based SEU
Clamping Circuits
V (out)
Radiation
Strike
1V
in
out
G
0V
D2
1.4V
GP
Shadow Gate
0.8
0.6
0.4
0.2
0
D1
V (outP)
outP
-0.4V
time
Higher VT
device
0.8
0.6
0.4
0.2
0
-0.4
time
9
Our Radiation Hardening
Approach

Approach B - Diode-connected Device based
SEU Clamping Circuits
V (out)
Radiation
Strike
1V
in
0.8
0.6
0.4
0.2
0
out
G
0V
D2
Ids
1.4V
GP
D1
V (outP)
outP
-0.4V
time
Higher VT
device
0.8
0.6
0.4
0.2
0
-0.4
time
10
Our Radiation Hardening
Approach

Compared approaches A and B




Performed layout and spice level simulation
Approach A has higher area penalty than B
But performance of approach A is slightly better than B
Therefore, selected approach B
11
Simulating a Radiation Strike


Circuit simulation is performed in SPICE
65nm BPTM model card is used



VDD = 1V
VTN = | VTP| = 0.22V
The radiation strike was modeled as current
source



As commonly done in this field (Zhou et. al)
Varied the value of Q and ta
tb is chosen to be 5ps (Gill et. al)
12
Simulating a Radiation Strike

Injected Current as a function of Q and ta
13
Protection Performance - Example

Radiation
strike at
output node.
Q = 4 fC
 ta = 10ps
Approach B
is used


14
Block Level Radiation Hardening

Individual gate protection



But our goal is to protect the entire logic circuit


Approach B is selected
Area overhead is more than 100%
We call it as block level protection
To understand block level protection

Critical depth of a gate
15
Critical Depth of a Gate


Consider 2 input AND gate
Computed for each hardened cell
Produces
glitch
Magnitude of
Radiation glitch reduces
Strike
Glitch magnitude is
1
1
tolerable
1
1
1
Critical Depth =3
16
Critical Depth of a Gate

Spice simulations were
performed using
Q = 5 fC, ta = 10ps, tb = 5ps

Tolerable glitch magnitude
is 0.35*VDD
Gate Name
Critical Depth (Δ)
inv2AA
5
inv4AA
1
nand2AA
1
nand3AA
1
nand4AA
1
nor2AA
1
nor3AA
1
nor4AA
1
and2AA
2
and3AA
1
and4AA
1
or2AA
1
or3AA
1
or4AA
1
17
Block Level Radiation Hardening

Simple approach – radiation hardening for
all gates
Very inefficient approach
 Large delay and area overhead

Primary
Primary
Inputs
Outputs
18
Block Level Radiation Hardening

Better approach – Fixed depth protection
Let Δmax= maxC(Δ(C))
 Assume Δmax = 2 then

Radiation
Strike
Radiation
Strike
Primary
Primary
Inputs
Outputs
19
Block Level Radiation Hardening

Further improvement – Variable depth
protection
Primary
Primary
Inputs
Outputs
20
Variable Depth Protection


Let Δ(INV2AA) = 4, Δ(NAND2AA) = 1 and Δ(AND2AA) = 2
Maximum depth of protection required is 4
8
Primary
3
6
9
Inputs
1
4
Primary
Outputs
7
10
5

2
More details of the algorithm can be found in the
paper
21
Experiments




Used our approach on some benchmark circuits.
Used SIS for synthesis and technology mapping.
Circuits were mapped for both delay and area.
Used the “sense” package in SIS to find circuit
delays.


sense reports the largest sensitizeable delay.
To get accurate area estimates, circuits were
placed and routed using SEDSM from Cadence.

QPLACE for placement, WROUTE for routing
22
Delay Characteristics of the Cells
Cell
Regular (ps)
Hardened (ps)
% Ovh
Critical
Depth
inv2AA
24.614
28.012
3.4
5
inv4AA
23.914
23.576
-0.34
1
nand2AA
31.416
34.993
3.58
1
nand3AA
44.92
48.39
3.47
1
nand4AA
62.436
66.259
3.82
1
nor2AA
45.617
49.902
4.29
1
nor3AA
77.151
82.786
5.64
1
nor4AA
92.80364
95.38472
2.58
1
and2AA
57.476
61.911
4.44
2
and3AA
76.902
82.722
5.82
1
and4AA
98.752
107.329
8.58
1
or2AA
71.161
74.678
3.52
1
or3AA
112.871
116.304
3.43
1
or4AA
125.165
128.543
3.38
1
AVG
3.97
23
Block Level Delay Results
Delay Overhead
Area Mapped
Ckt.
Regular

Delay Mapped
Hardened
% Ovh
Regular
Hardened
%Ovh
alu2
1057.99
1068.913
1.03
959.113
976.987
1.86
alu4
1318.652
1357.851
2.97
1247.762
1259.695
0.96
C1355
887.619
920.186
3.67
711.149
720.345
1.29
C1908
1301.522
1349.072
3.65
1085.28
1093.79
0.78
C3540
1546.819
1625.472
5.08
1414.443
1424.782
0.73
C499
887.619
920.186
3.67
711.149
720.345
1.29
C880
1489.53
1643.51
10.34
1405.322
1554.847
10.64
dalu
1167.817
1252.608
7.26
1056.534
1077.134
1.95
frg2
825.852
912.605
10.5
792.849
836.477
5.5
i2
451.879
463.949
2.67
363.611
382.298
5.14
i3
172.865
184.777
6.89
172.865
184.777
6.89
C7552
2012.924
2100.094
4.33
2005.371
2070.491
3.25
i10
1997.302
2253.81
12.84
1931.211
2002.74
3.7
AVG
5.76
Delay overhead
primarily due to
increased
capacitive load
from hardended
cells.
3.38
24
Block Level Area Results
Area Overhead
Area Mapped

Delay Mapped
Ckt.
Regular
Hardened
% Ovh
alu2
1045.88
1728.9
65.31
alu4
2019.6
2830.24
C1355
1592.01
C1908
C3540
Hardened
%Ovh
1439.44
1728.9
20.11
40.14
2470.09
3343.15
35.35
2252.45
41.48
1728.9
2279.11
31.82
1569.74
2252.45
43.49
1799.46
2279.11
26.66
3136
4763.76
51.91
4022.1
5077.99
26.25
C499
1569.74
2265.76
44.34
1728.9
2279.11
31.82
C880
1045.88
1883.56
80.09
1397.26
2252.45
61.2
dalu
2470.09
3540.25
43.32
3310.85
3986.66
20.41
frg2
1994.52
4725.19
136.91
2611.21
4057.69
55.4
i2
686.61
745.29
8.55
872.61
948.64
8.71
i3
495.51
586.61
18.39
495.51
566.44
14.32
C7552
7032.5
12638.26
79.71
7953.07
9576.58
20.41
i10
6845.9
9604
40.28
7705.32
11291.18
46.53
AVG
53.37
Regular

Area overhead is
larger for circuits
mapped for
minimum area
Area overhead is
also large for circuits
with smaller logic
depth (such as frg2)
30.68
25
Conclusions, Future Work

We have presented a novel circuit design approach for
radiation hardened circuit design.

We use shadow gates and protecting diode-connected
devices to protect the primary gate from a radiation
strike.

We presented techniques to replace fewer gates to help
minimize the area and delay penalties.


Only 30% area penalty and 4% delay penalty on average for
circuits mapped for minimum delay.
In the future we hope to be able to incorporate radiation
hardening in the technology mapping step itself.
26
Thank You!!
27
Our Radiation Hardening
Approach


Radiation strike at the output of the shadow gate
Output is protected upto 0.4+0.6+0.35 V glitch
Radiation
Strike
1V
in
out
G
0V
D2
1.4V
GP
Shadow Gate
V (out)
outP
-0.4V
D1
0.8
0.6
0.4
0.2
0
time
V (outP)
0.8
0.6
0.4
0.2
0
-0.4
time
28
Our Radiation Hardening
Approach

Radiation strike at the output of the shadow gate
Radiation
Strike
1V
in
out
G
0V
D2
1.4V
GP
Shadow Gate
V (out)
outP
-0.4V
D1
0.8
0.6
0.4
0.2
0
V (outP)
time
0.8
0.6
0.4
0.2
0
-0.4
time
29