School of Electrical, Computer and Energy Engineering
PhD Final Oral Defense
Methodical Design Approaches to Multiple Node Collection Robustness for Flip-flop
Soft Error Mitigation
by
Sandeep Shambhulingaiah
April 15 2015
9:00 am
GWC 208c
Committee:
Dr. Lawrence Clark (chair)
Dr. Keith Holbert
Dr. David Allee
Dr. Jae-sun Seo
Abstract
The space environment comprises of cosmic ray particles, heavy ions and high
energy electrons and neutrons. Microelectronic circuits used in space applications such as
satellites and space stations are prone to upsets induced by these particles. With transistor
dimensions shrinking due to continued scaling, terrestrial integrated circuits are also
increasingly susceptible to radiation upsets. Hence radiation hardening is a requirement
for microelectronic circuits used in both space and terrestrial applications.
This work begins by exploring the different radiation hardened flip-flops that
have been proposed in the literature and provides flip-flop taxonomy based on the
different hardening techniques.
A reduced power delay element for the temporal hardening of sequential digital
circuits is presented. The delay element single event transient tolerance is demonstrated
by simulations using it in a radiation hardened by design master slave flip-flop. Using the
proposed delay element saves up to 25% total FF power at 50% activity factor. The delay
element is used in the implementation of a 8-bit, 8051 designed in the TSMC 130nm bulk
CMOS.
A single impinging ionizing radiation particle is increasingly likely to upset multiple
circuit nodes and produce logic transients that contribute to the soft error rate in most
modern scaled process technologies. The design of flip-flops is made more difficult with
increasing multi-node charge collection, which requires that charge storage and other
sensitive nodes be separated so that one impinging radiation particle does not affect
redundant nodes simultaneously. We describe a correct by construction design
methodology to determine a-priori which hardened FF nodes must be separated, as well
as a general interleaving scheme to achieve this separation. We apply the methodology to
radiation hardened flip-flops and demonstrate optimal circuit physical organization for
protection against multi-node charge collection.
Finally, the methodology is utilized to provide critical node separation for a new
hardened flip-flop design that reduces the power and area by 31% and 35% respectively
compared to a temporal FF with similar hardness. The hardness is verified and compared
to other published designs via the proposed systematic simulation approach that
comprehends multiple node charge collection and tests resiliency to upsets at all internal
and input nodes. Comparison of the hardness, as measured by estimated upset crosssection, is made to other published designs. Additionally, the importance of specific
circuit design aspects to achieving hardness is shown.