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Department of Electronics Engineering

Sahand University of Technology

NMOS inverter with an n-channel enhancement-mode mosfet with the gate connected to the drain

Farshad Gozalpoor

Professor : Dr Najafi Aghdam

winter 93

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Abstract

 We will analyze the dc voltage transfer characteristics of this inverter in this figure.

 We will also define and develop the noise margin of this digital circuit in terms of the inverter voltage transfer curve.

 We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels.

 A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits.

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Diode connected transistor

The drain current is zero.

A nonzero drain current is induced in the device.

We can see that the following condition is satisfied :

A transistor with this connection always operates in the saturation region when not in cutoff.

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Some definitions

 VIH = minimum HIGH input voltage

 VIL = maximum LOW input voltage

 VOH= minimum HIGH output voltage

 VOL = maximum LOW output voltage

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HINT:

In the following analysis, we neglect the body effect and we assume all threshold voltages are constant. These assumptions do not seriously affect the basic analysis or the inverter characteristics.

VTC computations

The driver is cut off and the drain currents are zero.

M1 : Off

M2 : Sat

Assumptin :

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M1: Sat

M2: Sat

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Computing Vin1 and Vo1 :

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c)

M1 : Triode

M2 : Sat

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Assumption :

Vin=1.5

K1=20

K2=10

Vth=0.41v

VO+ = 2.069

VO - = 0.31

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Computing VIH :

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Analysis of the transient behavior of the gate

Drain diffusion capacitances of the NMOS transistors, the capacitance of the connecting wires, and the input capacitance of the fan-out gates decreasing the on-resistance of the transistor.

 A fast gate is built either by keeping the output capacitance small or by C

L

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Switching Threshold

We solve the case where the supply voltage is high so that the devices can be assumed to be velocity-saturated

Where

13 k V

V r n 1

M

 k V n 1 2

Tn

k V

1

 

V

V

DSATn

2 n 1 DSATn 1

2

1

1

V

W v n

2

W v n

2

1 1

(

1

) r

, 1

2

V

Tn

2

2

(

V

V

DSATn

M

2

V )

V

Tn 2

V

DSATn 2

2

)

0

For large values of VDD

 It is considered to be desirable for VM to be located around the middle of the available voltage swing.

 To move VM upwards, a larger value of r is required.

 Increasing the strength of the NMOS, on the other hand, moves the switching threshold closer to GND.

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V

(

M

W L rV

1 n 2 n 1

 r k V k V ( V n 1 DSATn 1 M

V

Tn 1

V

DSATn 1 n 2 DSATn 2

/ 2)

( V

DD

V

M

V

Tn 2

V

DSATn 2

/ 2)

Design Technique — Maximizing the noise margins

To balance the driving strengths of the transistors and maximize the noise margins and obtain symmetrical characteristics use this equation:

Example: Switching threshold

VM is sensitive to variations in the device ratio

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( / ) n 2

( / ) n 1

 k V k V ( V n 1 DSATn 1 M

V

Tn 1

V

DSATn 1 n 2 DSATn 2

/ 2)

( V

DD

V

M

V

Tn 2

V

DSATn 2

/ 2)

We have sweeped the W of load transistor to see the effect of change in transistors size ratio on the VM

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 This means that small variations of the ratio do not disturb the transfer characteristic that much.

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The usage of shifting the transient region of the VTC by changing VM

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Another example for VTC

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Scaling the Supply Voltage

 Continuing technology scaling forces the supply voltages to reduce at rates similar to the device dimensions.

 At the same time, device threshold voltages are virtually kept constant.

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 At a voltage of 0.2 V the width of the transition region measures only 10% of the supply voltage while it widens to 25% for 2.5 V

 So, given this improvement in dc characteristics

 why do we not choose to operate all our digital circuits at these low supply voltages?

 reducing the supply voltage has a positive impact on the energy dissipation, but is detrimental to the performance on the gate.

 The dc-characteristic becomes increasingly sensitive to variations in the device

 parameters such as the transistor threshold, once supply voltages and intrinsic voltages become comparable.

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D

ELAY DEFINITIONS

t

P

t

PHL

t

PHL

2

22

First-Order Analysis

Integrate the capacitor (dis)charge current:

i the (dis)charging current

v the voltage over the capacitor

v1 and v2 the initial and final voltage

 Equivalent resistance when (dis)charging a capacitor:

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 Equivalent resistance, averages the resistance of the device over the interval:

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Example

Assume that a driver with a source resistance of 10 kW is used to drive a 10 cm long, 1 mm wide Al1 wire with total lumped capacitance for this wire equals 11 pF

The operation of this simple RC network is described by the following ordinary differential Equation:

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When applying a step input, the transient response of this circuit is

 The time to reach the 50% point: t = ln(2)t = 0.69t

 To get to the 90% point: t= ln(9)t = 2.2t

Where:

 proportional to the time-constant of the network.

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R

driver

C

lumped

 the propagation delay of such a network for a voltage step at the input is proportional to the time-constant of the network:

 The overall propagation delay of the inverter:

Example:

Propagation Delay of a 0.25 m m Inverter t t t p

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 t

  pHL

0.69

2

R pLH

L

 2

C

L

0.69

C

L

0.69

(

R eqn 1

2

1

R

C

L

2

)

supply voltage equals to 2.5 V

The (W/L) ratios of the transistors to be 1.5 for the NMOS1, and 4.5 for the NMOS2.

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 make the parameters governing the delay explicit

Propagation delay of inverter as a function of supply voltage

V

29

DD

V

Tn

V

DSATn

/ 2

The propagation delay of a gate can be minimized in the following ways:

Reduce CL : three major factors contribute to the load capacitance: the internal diffusion capacitance of the gate itself, the interconnect capacitance, and the fanout.

Increase the W/L ratio of the transistors . This is the most powerful and effective performance optimization tool in the hands of the designer.

Increase V

DD

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 If symmetry and reduced noise margins are not of prime concern, it is possible to speed up the inverter by reducing the width of the PMOS device

The load capacitance of the first gate:

C

C

L

L

31

 dL

1

 

W

 

L

C

C

1 1 dD 1

C

1 gD

2

  

 C

C

W

2

C gL 2

 By setting:

 Sizing Inverters for Performance

Cint is associated with the diffusion capacitances of the NMOS and PMOS transistors as well as the gate-drain overlap (Miller) capacitance

Cext is the extrinsic load capacitance t

C

P

32 t

L

 opt

2

C

 int r

1

1

   

C

 ext

C C

W

C

C dD 1

C

C dD 1

C gD gD 2

2 gD

2

C

W

 

C

W

R eqD

R eqD

1

 r

R eqL

, r

 

R

R eqL eqD

tp0 = 0.69 ReqCint represents the delay of the inverter only loaded by its own intrinsic capacitance ( Cext = 0), and is called the intrinsic or unloaded delay t t

C

P

P int

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0.69

0.69

SC eq

0.69

R eq iref

R C

 int

R

,

C

R

1 int eq

 

S

R

C ext

C int ext ref

S

SC iref

 t

P

1

0

1

C ext

C int

C / SC ext

 iref

0.69

R C ref iref

1

C ext

SC iref

 t

P 0

1

C ext

SC iref

The intrinsic delay of the inverter tp0 is independent of the sizing of the gate, and determined by technology and inverter layout.

Making S infinitely large yields the maximum performance gain, eliminating the impact of external load, and reducing the delay to the intrinsic one.

Sizing A Chain of Inverters:

Determining the optimum sizing of a gate when embedded in a real environment.

  is a proportionality factor, which is only a function of technology

 Delay if the inverter is function of the ratio between its external load capacitance and input capacitance. This ratio is called the effective fanout f .

C int

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 

C g t

P

 t

P 0

1

C ext

C g

 t

P 0

1

 f

 

The goal is to minimize the delay through the inverter chain

 the optimum size of each inverter is the geometric mean of its neighbors sizes t

 t 35

C

C

P  t

 p

0

0 

1

C

,

C

C

1

, C 1

 g j

1 t p 0

 1

Total

Delay

C

C

,

1 t p

 j

N

C

1 t

 t

,

1

 f j p ,0

 j

N

1

1

C

C

,

1

,

1

C

L

With Cg,1 and CL given:

Choosing the Right Number of Stages in an Inverter Chain

The optimum value can be found by differentiating the minimum delay expression by the number of stages, and setting the result to 0.

For

= 0:

Optimal number of stages equals N = Ln( F )

Effective fan out of each stage is set to f = 2.71828 = e

36 f

N

N

C

F

C  g

L

,1

N

F

N F ln F

N

Minimum

Delay

 t p

Nt f e

1

 p 0

1

N

 f

F

 Optimum effective fanout f as a function of the self-loading factor

 in an inverter chain

 Normalized propagation delay ( tp /( tpopt ) as a function of the effective fanout f for

1.

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The rise/fall time of the input signal

 propagation delay of a minimum-size inverter as a function of the input signal slope

Example: Delay of Inverter embedded in Network

 an expression for the delay of the stage-2 inverter

38 t p ,2

 t

 p 0

1

   

C g ,1

C g

4 C g

,2

C g

,3

,2

  t p

   

0

1

C g ,3

4 C g ,2

C g ,1

C

L

C g ,2

C g ,3

Power, Energy, and Energy-Delay

The power dissipation of an inverter is dominated by dynamic dissipation resulting from charging and discharging capacitances.

Dynamic Power Consumption

Dynamic Dissipation due to Charging and Discharging Capacitances

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E

 

0

 i

 i

0

VDD

    

0

V C

0 dv

C dt out

L dv out dt

 

C

L

L

V

DD

0

DD

V

DD

 dv out out

0 out

C V

C V

2

DD

L DD

2

2

This means that only half of the energy supplied by the power source is stored on CL

 Example: Capacitive power dissipation of inverter

 the value of the load capacitance was determined to equal 6 fF

For a supply voltage of 2.5 V

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E dyn

C V

L DD

2 

37.5

fJ

T

 f

1

 t pLH

 t pHL

2 t p

 p

P dyn

E dyn

2 t p

580 m

W

 switching activity f : maximum possible event rate of the inputs

P 0

1 : probability that a clock event results in a 0

1 event at the output of the gate.

CEFF = P 0

1 CL is called the effective capacitance and represents the average capacitance switched every clock cycle

Example: Switching activity

 Power consuming transitions occur 2 out of 8 times, which is equivalent to a transition probability of 0.25 (or 25%).

Clock and signal waveforms

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 2

P C V f dyn L DD 0

1

 2

0

1

 2

C V P C V f

L DD EFF DD

Example: Transistor Sizing for Energy Minimization

Degrees of freedom are size factor f of the inverter and supply voltage Vdd of the circuit.

f = 1 and Vdd = Vref.

inverter driving an external load capacitance Cext, while being driven by a minimum sized gate.

42 t p

 t p 0

 2

E V C dd g

1

1

 f

 

1 f

F

1

  

1

 f

 

F

, F

C ext

C g 1

, t p 0

V

DD

V

DD

V

TE

1 t p  t pref t p 0

2 t

F

3

F

 f

V

DD



V ref

V

TE

 V ref

V

DD

V

TE

2

3

F

F f

1

Sizing of an inverter for energy-minimization

Required supply voltage as a function of the sizing factor f for different values of the overall effective fanout F

Energy of scaled circuit (normalized with respect to the reference case) as a function of f . Vref = 2.5V, VTE = 0.5V.

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Static Consumption

Example: Impact of threshold reduction on performance and static power dissipation

0.25 m m CMOS technology

 slope factor S for this device equals 90 mV/decade

 The off-current of the transistor for a

VT of approximately 0.5V equals 10-11A

 Reducing the threshold with 200 mV to

0.3 V multiplies the off-current of the transistors with a factor of 170!

Decreasing the threshold increases the subthreshold current at V

GS

= 0.

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Putting It All Together:

P tot

45

P dyn

P dp

P stat

C V

L DD

2 

V I t

DD peak s

 f

0

1

V I

DD leak

PDP

P t av p f max

1

2 t p

L DD

2

PDP C V f t max p

C V

L DD

2

2

EDP

   p

P t av p

2 

C V

L DD

2 t p

EDP

C V

L DD

V

DD

V

Te

, V

Te

V

T

V

DSAT

2

2

C V

L DD

3

V

DD

V

Te

2 t p

/ 2,

: techno log y

 parameter

Some of remaining simulations Input Charatristics

Input

Output

W

 

L

46

  

D

4.1

m

0.18

m

W

 

L 

   

L

0.22

m

0.18

m

47 t pHL

48 t pLH

Input Charatristics

Input

Output

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W

 

L 

  

D

4.1

m

0.18

m

W

 

L 

   

L

19.1

m

0.18

m

50 t pHL

51 t pLH

Ring Oscillator

52

W

 

L 

22

Transient simulation

53

f

54

1 f

T f

1

2 n

P

 

P

1

1.901

GHz

1

 

GHz

55 NOT

 f f

Oscillation

Oscillatio

1.1

GHz

Thanks for your attention

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