Metal-Oxide Semiconductor (MOS)
Field-Effect Transistors (MOSFETs)
1
Introduction
- Transistors are three-terminal devices.
- Voltage between two terminal controls the current flowing in the third terminal.
- Amplifiers, or switches.
Compared to Bipolar Junction Transistors (BJT), MOSTFETs;
- Can be made quite small (require small area).
- Can be manufactured with simple fabrication process.
- Can be operated with little power.
- Can be integrated densely (>200 millions on a single IC chip, Very-large-scale-integrated circuit, VLSI).
- Digital and analog functions can be implemented almost exclusively ( i.e., with very few or no resistors).
- Digital and analog functions can be implemented on the same IC chip (mixed-signal design).
4.1 Device Structure and Physical Operation
The enhancement-type MOSFET is the most widely used field-effect transistor.
4.1.1 Device Structure – (n-channel enhancement-type MOSFET = enhancement-type NMOS)
0.2~100 μm
2-~50 nm
0.1~3 μm
MOS
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Another name for the MOSFET:
Insulated-gate FET, IGFET (almost no current through the gate : ~10 -15 A)
4.1.2 Operation with No gate Voltage
Between drain and source : Back-to-back pn junction
No current flow
4.1.3 Creating a Channel for current flow
- An n-channel is formed in a p-type substrate – inversion layer.
- If a voltage is applied between drain and source, current flows
through this n-channel. (NMOS)
- Threshold voltage Vt : a voltage of υGS at which a sufficient
number of mobile electrons accumulate in the channel region to
form a conducting channel.(+0.5 ~ 1 V)
- The gate and the channel form a capacitor.
- The positive charges on the gate and the electrons in the channel
develop an electric field.
- This electric field controls the current flow in the channel.
Field-Effect Transistor (FET) !
Figure 4.2 The enhancement-type NMOS transistor with
a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
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4.1.4 Applying a Small VDS (< 50 mV)
The device acts as a resistance whose value is determined by υGS.
Specifically, the channel conductance is proportional to υGS – Vt’
and thus iD is proportional to (υGS – Vt) υDS.
(υGS – Vt) : excess gate voltage, effective voltage,
overdrive voltage
4.1.5 Operation as VDS increased.
- As υDS is increased υGD =υGS – υDS decreases and channel takes the
tapered form, and resistance between the drain and gate increases.
- At υGD =υGS – υDS = Vt or υDS = υGS - Vt , the channel depth at the
drain end is almost zero! – The channel is pinched off.
- Increasing υDS beyond this value has, theoretically, no effect on
the channel shape and channel current.-Saturation!
When υDS = small or 0 V
 DSsat  GS  Vt
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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type
NMOS transistor operated with vGS > Vt.
Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS
reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has
little effect (theoretically, no effect) on the channel’s shape.
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4.1.6 Derivation of the iD-vDS Relationship
i
dq dq dx

dt dx dt
Q  CV
Cox 
 ox
tox
(4.2)
 ox  3.9 0  3.9  8.854  1012  3.45  1011 F/m
dq  Cox (Wdx ) GS   ( x )  Vt 
d ( x )
( E  V )
dx
dx
d ( x )
  n E ( x )  n
(4.3)
E( x)  
dt
dx
(4.4)
d ( x )
dx
d ( x )
  ( x )  Vt 
dx
i   nCoxW GS   ( x )  Vt 
iD   i  nCoxW GS
iDdx  nCoxW GS  Vt   ( x )d ( x )

L
0
iDdx  
 DS
0
nCoxW GS  Vt   ( x )d ( x )
1 2 
W 
iD  ( nCox )   (GS  Vt ) DS   DS
 (4.5)
2
 L 

At the beginning of saturation region, υDS= υGS-Vt
1
W 
iD  ( nCox )   (GS  Vt )2 (4.6)
2
 L
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kn  nCox
W
iD  kn 
 L
(4.7)
Cox 
1 2 

 (GS  Vt ) DS  2  DS 



2
 (GS  Vt )

 ox
tox
(4.2)
(Triode region)
iD 
1 W
k
2 n  L
W
 L


 : Aspect ratio of the MOSFET
Ex. 4.1 p245

(4.5a)
(saturation region) (4.6a)
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4.1.7 The p-Channel MOSFET p.247
- The p-Channel MOSFET is fabricated on an n-type
substrate with p+ regions for the drain and source.
- The p-Channel MOSFET has holes as charge carriers.
- υGS, υDS, and Vt are negative. The current flows from the
source to the drain.
- PMOS technology originally dominated MOS
manufacturing.
4.1.8 Complementary MOS, or CMOS
- NMOS has virtually replaced because it is smaller,
faster, and needs lower supply voltage.
- But you have to be familiar with PMOS because:
there are many discrete PMOSFETs and
there are complementary MOS, CMOS!!
- CMOS is the most widely used of all the IC technologies
in analog and digital circuit design !!
Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is
formed in a separate n-type region, known as an n well. Another arrangement is also possible in
which an n-type body is used and the n device is formed in a p well. Not shown are the
connections made to the p-type body and to the n well; the latter functions as the body terminal
for the p-channel device.
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4.2 Current-Voltage Characteristics
Detailed analysis of equations 4.5 and 4.6
4.2.1 Circuit Symbol
Figure 4.10 (a) Circuit symbol for the n-channel
enhancement-type MOSFET. (b) Modified circuit
symbol with an arrowhead on the source terminal
to distinguish it from the drain and to indicate
device polarity (i.e., n channel). (c) Simplified
circuit symbol to be used when the source is
connected to the body or when the effect of the
body on device operation is unimportant.
Normal direction of current flow.
4.2.2 The iD-vDS Characteristics
Amplifier - Saturation region
Switch – Cutoff and triode region
• For the operation in the triode region,
GS  Vt (Induced channel) (4.8)
and keep υDS small enough so that the channel remains
continuous.
GD >Vt (Continuous channel) (4.9)
At υGD =υGS – υDS = Vt or υDS = υGS - Vt , the channel depth at
the drain end is almost zero! – The channel is pinched off.
GD   DS  Vt ,  DS  GS  Vt (Continuous channel) (4.10)
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Eq.(4.5) iD  kn
rDS 
W
L
 DS
iD
 DS small
GS =VGS
1 2 

(


V
)



GS
t
DS

2 DS 

 W

  kn
(VGS  Vt )
 L

 W
rDS  1  kn 
  L


 VOV 


iD
(4.11)
kn
W
(  Vt ) DS
L GS
(4.12)
1
(4.15)
(4.13)
VOV  VGS  Vt (4.14) gate-to-source overdrive voltage
The operation of the MOS transistor as a linear resistance whose
value is controlled by gate voltage !
• For the operation in the saturation region,
GS  Vt
GD  Vt
(Induced channel)
(4.16)
(Pinched-off channel) (4.17)
just same as for the triode operation.
(υGD =υGS – υDS)
At the boundary between triode and saturation region,
(4.11)
 DS  GS  Vt
(Boundary) (4.19)
 DS  GS  Vt
iD 
(Pinched-off channel) (4.18)
1 W
kn
(GS  Vt )2
2
L
(4.20) Saturation current
Eq.(4.20) shows that the saturation current is; (1) independent of the drain voltage.
(2) determined by square of the gate voltage.
Eq.(4.20) also shows that the saturated MOSFET behaves as an ideal current source.
Figure 4.13 Large-signal equivalent-circuit model of
an n-channel MOSFET operating in the saturation region.
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At the boundary between triode and saturation region,
 DS  GS  Vt
(Boundary) (4.19)
(4.11)
1 W
kn
(GS  Vt )2 (4.20) Saturation current
2
L
1 W 2
iD  kn  DS
(4.21) Saturation current
2
L
iD 
Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor
for operation in the triode region and in the saturation region.
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4.2.3 Finite Output Resistance in Saturation
1 W
kn
(GS  Vt )2 (4.20) Saturation current
2
L
Eq.(4.20) shows that the saturation current is independent of the drain voltage.
But, in practice, increasing υDS beyond υDSsat does affect the channel length.
iD 
The phenomenon that the channel length is reduced form
L to L-ΔL is known as channel-length modulation.
1
W
kn
(GS  Vt )2
2 L  L
1 W
1
 kn
(GS  Vt )2
2
L 1  (  L  L)
iD 
1 W
k
2 n L
Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move
slightly away from the drain, thus reducing the effective channel length (by ΔL).
1 W

Assuming L    DS , iD  kn  1   DS  (GS  Vt )2
2
L
L

let  
iD 

L
L 

2
 1  L  (GS  Vt )


( L / L
1)
, process-technology parameter (V -1 )
1 W
kn
(GS  Vt )2  1   DS  (4.22)
2
L
With extrapolation, VA  1/  , Early voltage
VA  VA L : V   5~50 [V/m], entirely process-techology parameter
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1 W
(GS  Vt )2  1   DS  (4.22)  : [V -1 ]
iD  kn
L
2
-1
 i 
ro   D 
(4.23)


 DS GS constant
let I D 
 k W

ro    n
(VGS  Vt )2 
 2 L

1
1 W
kn
(VGS  Vt )2 , ro   I
D
2
L
GS  Vt
(4.24)
VA  1/ 
(4.25)
ro 
4.2.4 Characteristics of the p-Channel MOSFET
-1
VA
ID
(4.26)
(Induced channel) (4.27)
 SG  Vt
 DS  GS  Vt
iD  k p
W
L
(Continuous channel)
1 2 

(


V
)



t
DS
 GS
2 DS 

(4.28)
(4.29)
k p =p C ox (4.30)
 DS  GS  Vt
iD 
(Pinched-off channel)
(4.31)
1 W
k p (GS  Vt )2  1   DS  (4.32)
2
L
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4.2.5 The Role of the Substrate-The Body Effect
- Usually, the source terminal is connected to the substrate (or body) terminal.
- In integrated circuit, many MOS transistors are fabricated on a single substrate.
- In order to maintain the cutoff condition for all the substrate-to-channel junctions, the substrate is usually connected
to the most negative power supply in an NMOS circuit (the positive in a PMOS circuit).
- The reverse bias will widen the depletion region.
- The channel depth is reduced.
- To return the channel to its former states, υGS has to be increased.
Vt  Vt   [ 2 f  VSB  2 f ]
(4.33)
2 f ( physical  parameter )  0.6 V
 (body  effect  parameter ) 
2qN A s
(4.34)
Cox
The body effect can cause considerable degradation in
circuit performance (Chap. 6)
4.2.6 Temperature Effect
4.2.7 Breakdown and Input Protection
- The overall observed effect of a temperature
increase is a decrease in drain current.
- This very interesting result is put to use in applying
the MOSFET in power circuit (Chap. 11).
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- Weak avalanche : υDS (20~150 V) breakdown between drain
and substrate.
- Punch-through : υDS (~20 V) breakdown between drain and
source for short-channel devices.
- υGS (>30 V) breakdown between gate and source.
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4.3 MOSFET Circuits at DC (Bias Analysis)
• For the operation in the triode region,
- Neglect Channel-length modulation. (λ=0)
- Overdrive voltage VOV=VGS-Vt (VOV, Vt > 0, for NMOS)
- Overdrive voltage VSG=|VGS|=|Vt |+|VOV| for PMOS
GS  Vt (Induced channel) (4.8)
 DS  GS  Vt (Continuous channel) (4.10)
• For the operation in the saturation region,
EXAMPLE 4.2
GS  Vt
Vt=0.7 V, μnCox =100 μA/V2, L=1 μm, W =32 μm
(Induced channel)
 DS  GS  Vt
Design the circuit so that the transistor operates
at ID = 0.4 mA and VD = +0.5 V
(4.16)
(Pinched-off channel) (4.18)
Since VD > VG, saturation region !
1
W
nCox (VGS  Vt )2
2
L
I D  400  A, nCox  100  A/V2 , W / L  32,
Eq. 4.6a, I D 
Substituting VGS  Vt  VOV ,
1
32 2
400   100  VOV
2
1
VOV  0.5 V
VGS  Vt  VOV  0.7  0.5  1.2 V
Thus source must be at -1.2 V.
RS 

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VS  VSS
ID
1.2  ( 2.5)
 3.25 k
0.4
RD 

VDD  VD
ID
2.5  0.5
 5 k
0.4
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EXAMPLE 4.3
Design the circuit to obtain ID of 0.08 mA. R=?
VD = ?, μnCox =200 μA/V2, L=0.8 μm.
VDS = VGS, Saturation region!
1
W
 nC ox (VGS  Vt )2
2
L
1
W 2
  nC ox
V
2
L OV
ID 
Let’s find VGS!
VOV 

2I D
nCox (W / L)
2  80
 0.4 V
200  (4 / 0.8)
VGS  Vt  VOV  0.6  0.4  1 V
VD  VG  1 V

Figure 4.21 Circuit for Example 4.3.
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R
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VDD  VD
ID
31
 25 k
0.080
18
EXAMPLE 4.5 Vt  1 V, kn (W / L)  1 mA/V 2 ,   0
EXAMPLE 4.4
Vt=1 V, k’(W/L) 1 mA/V2
Design the circuit so that VD = +0.1 V.
What is the effective resistance between drain
and source?
I ?
ID  ?
VD  ?
VG  ?
VS  ?
VG  VDD
RG 2
10
 10 
 5 V
RG 2  RG1
10  10
VGS  5  6 I D
Since VD < VG, and Vt =1 V, triode region !
I D  kn
RD 
W
L
1 2 

(VGS  Vt ) DS  2  DS   0.395 mA


VDD  VD 5  0.1

 12.4 k
ID
0.395
In practice, 12 kΩ, 5%
rDS
ID 
1 W
1
kn
(VGS  V)2   1  (5  6 I D  1)2
2
L
2
18 I D2  25 I D  8  0
I D  0.5 mA
VS  0.5  6  3 V
VGS  5  3  2 V
V
0.1
 DS 
 253 
ID
0.395
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Assume saturation region operation.
VD  10  6  0.5  7 V Saturation region operation!
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EXAMPLE 4.6
Vt= -1 V, k’(W/L) 1 mA/V2
1 W
k p (VGS  Vt )2
2
L
1 W 2
 k p
V
2
L OV
ID 
- Design the circuit so that the transistor operate in
saturation region at ID = 0.5 mA and VD = +3 V.
- What is the largest value that RD can have while
maintaining saturation region operation?
I D  0.5 mA, k 'pW / L  1 mA/V2
VOV  1 V
VGS  Vt  VOV  1  1  2 V
 VG should be 3 V
For this, a possible selection is RG1=2 MΩ, RG2= 3MΩ
RD 
VD
3

 6 k
I D 0.5
- Overdrive voltage VSG=|VGS|=|Vt |+|VOV| for PMOS
VD max  3  1  4 V
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RD 
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 8 k
0.5
20
EXAMPLE 4.7
Vt= ±1 V, k’(W/L) 1 mA/V2 for NMOS and PMOS
For υI =+2.5 V
- for QP, VGS = 0 V, cutoff !
- Find iDN, iDP, υO, for υI =0 V, +2.5 V, and -2.5 V.
υO should be negative for IDN.
υGD will be greater than Vt.
for QN, triode !
I DN  kn (Wn / Ln )(VGS  Vt )VDS
 1[2.5  ( 2.5)  1][O  ( 2.5)]
0  O
and also, I DN (mA) 
10 (k )
I DN  0.244 mA, O  2.44 V
For υI = -2.5 V
For υI =0 V,
- QN and QP are perfectly matched.
- Equal |VGS| (2.5 V)
-The circuit is symmetrical.
(upper and lower part)
 O should be 0 V
- Exact complement of +2.5 V
- QN will be off.
I DN  0
for Qp, triode !
I DP  0.244 mA, O  2.44 V
- Thus |VDG| = 0 V.
- Thus in saturation region !
I DP  I DN  12  1  (2.5  1)2
 1.125 mA
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4.4 The MOSFET as an Amplifier and as Switch
The MOSFET acts as a Voltage-Controlled Current Source !
υGS
Transconductance Amplifier !
iD
Saturation Region !!!
1 W
kn
(GS  Vt )2 (4.20) Saturation current
Nonlinear !
2
L
For linear amplification, we need dc-bias voltage VGS and require small input signal υgs.
iD 
4.4.1 Large-Signal OperationThe Transfer Characteristics
4.4.2 Graphical Derivation of
The Transfer Characteristics
 DS  VDD  RD iD (4.36)
iD 
VDD
1


(4.37)
RD RD DS
Load-line equation
For a given input υI(υGS),
We can find output υO (υDS).
Basic structure of the Common-Source (CS)
(ground-source) amplifier.
O   DS  VDD  RD iD
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4.4.2 Graphical Derivation of
The Transfer Characteristics
υO
υI = υGS
4.4.3 Operation as a Switch
Turn off : υI < Vt, somewhere on XA
Turn on : υI close to VDD, close to C
Digital Logic Inverter !
4.4.4 Operation as a Linear Amplifier
Between A and B
A 
dO
d I
(4.38)
 I  VIQ
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23
4.4.5 Analytical Expression for the Transfer Characteristics
υI < Vt, υO = VDD
υI ≥ Vt, υO ≥ υI - Vt
Cutoff-region, XA:
Saturation-region AQB:
O  VDD  RD iD
1
2
iD 
W
 L
O  VDD  RD nCox 
At Q,
A 
dO
d I
1
W
( nCox ) 
2
 L

2
 ( I  Vt )

(4.39)
A   RD nCox
 I  VIQ

2
 ( I  Vt )

W
(V  Vt ) (4.40)
L IQ
For dc bias point Q, υI = VIQ, υO = VOQ ,
VIQ  Vt  VOV VRD =VDD - VOQ
A  
2(VDD  VOQ )
VOV

2VRD
VOV
(4.41)
End point of the saturation region
VOB  VIB  Vt (4.42)
υI ≥ Vt, υO ≤ υI - Vt
Triode-region BC:
W
i D  nCox 
 L
O  VDD  RD iD
1 2

 [( I  Vt )O  2 O

1 2

( I  Vt )O  2 O 


small
W
O  VDD  RD nCox ( I  Vt )O
L
Taylor expansion, (1+x)-1 =1- x+ x2/2-….
O  VDD  RD nCox
W
L
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
W

 O = VDD 1  RD nCox ( I  Vt ) O 
L


(4.43)
W
rDS


rDS = 1  nC ox
( I  Vt )  , O  VDD
L


rDS  RD
Usually, rDS
RD ,
Copyright  2004 by Oxford University Press, Inc.
O  VDD
rDS
RD
(4.44)
(4.45)
EXAMPLE 4.8, p.277
24
4.5 Biasing in MOS Amplifier Circuits
4.5.1 Biasing by Fixing VGS - Large ΔID !, Not useful !
The spread in the values of parameters (e.g. W/L) is large among
the same type of MOSFET.
4.5.2 Biasing by Fixing VGS and Resistor in the Source
- Good for discrete MOSFET
ID 
4.5.3 Biasing Using a Drain-to-Gate Feedback Resistor
- Good for discrete MOSFET
4.5.4 Biasing Using a Constant-Current Source
- Good for IC
1
W
nCox (VGS  Vt )2
2
L
Figure 4.29 The use of fixed bias (constant VGS) can result in a large
variability in the value of ID. Devices 1 and 2 represent extremes among
units of the same type.
4.5.2 Biasing by Fixing VGS and Resistor in the Source
Excellent Biasing Technique for Discrete MOSFET Circuits
- For given VG and RS,
VG  VGS  RS I D (4.46)
1
W
I D  ( nCox ) 
2
 L

2
 (VGS  Vt ) (a)

}
ID, VGS can be
determined.
- For two FETs of the same type,
Smaller ΔID than that of Fig. 4.39
- For one FET,
ID increases. –> (4.46) VGS decreases.
–> (a) ID decreases.–> ID is stabilizes.
Rs provides negative feedback resulting in
stabilized ID. Degeneration resistance
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25
(a) basic arrangement
(c) practical implementation
using a single supply
(d) coupling of a signal source to the gate
using a capacitor CC1
For Fig. c and d
- RG : ~ MΩ for large input impedance to the signal source (Fig. d)
- CC1 : large capacitance, coupling, signal dc block not to disturb bias.
suitable only in discrete circuit design (Sect. 4.7).
- RD : large enough to obtain high gain,
small enough to allow for swing and operation in saturation. (Ex4.6)
For Fig. e
- RG : for a dc ground at the gate
for a high input impedance to a signal source.
(e) practical implementation using two supplies.
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26
EXAMPLE 4.9
Design!
Sol)
Vt=1 V, k’(W/L) 1 mA/V2
As a rule of thumb for design,
One-third of the power supply voltage as a drop
across each of RD, MOSFET, RS.
RD 
VDD  VD 15  10

 10 k
ID
0.5
RS 
VS
5

 10 k
RS 0.5
2
I D  12 kn (W / L)VOV
2
0.5  12  1  VOV
VGS  Vt  VOV  1  1  2 V
Figure 4.31 Circuit for Example 4.9.
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VG  VS  VGS  5  2  7 V
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27
4.5.3 Biasing Using a Drain-to-Gate Feedback Resistor
- Good for Discrete MOSFET
- RG : Feedback resistor
~ MΩ
VGS  VDS  VDD  RD I D
VDD  VGS  RD I D
1
W
I D  ( nCox ) 
2
 L
(4.49)

2
 (VGS  Vt ) (a)

- Feedback mechanism – negative feedback or degeneration
ID increases. – (4.49) VGS decreases. – (a) ID decreases.
ID is stabilizes !
- Bias for Common source amplifier
- Drawback of a limited output voltage swing.
What about shorting gate
and drain instead of RG?
4.5.4 Biasing Using a Constant-Current Source
- Good for IC - RG : ~ MΩ for large input impedance to the
signal source, for a dc ground at the gate.
- RD : for dc voltage at the drain, for output
signal swing, for operation in saturation.
- Constant-current source : Q1 is the heart of the circuit
Drain is shorted to the gate – saturation !
I D1 
1 W 
kn   (VGS  Vt )2 (4.50)
2  L 1
}
ID1, VGS can be
VDD  VSS  VGS
determined.
I D1  I REF 
(4.51)
R
1 W 
I  I D 2  kn   (VGS  Vt )2 (4.52) ID2 can be determined.
2  L 2
What about design ?
Implementation of the constant-current
(W / L)2
I  I REF
(4.53)
source using a current mirror.
D4.22, p286
(W / L)1
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4.6 Small-Signal Operation and Models
For dc bias current, I D 
1 W
kn
(VGS  Vt )2
2
L
VDS  VD  VDD  RD I D (4.55)
(4.54)
For saturation, we must have VD  VGS  Vt
4.6.2 The signal current in the drain terminal
GS  VGS   gs
(4.56)
1 W
kn
(VGS   gs  Vt )2
2
L
1 W
W
 kn
(VGS  Vt )2
 kn
(V  Vt ) gs +
2
L
L GS
iD 
dc bias current
Current proportional to input
1 W 2
k   (4.47)
2 n L gs
Nonlinear distortion
To reduce the nonlinear distortion,
Figure 4.34 Conceptual circuit utilized to study
the operation of the MOSFET as a small-signal
amplifier.
1 W 2
k 
2 n L gs
kn
W
(V  Vt ) gs
L GS
 gs
2(VGS  Vt ) (4.58)
or  gs
2VOV
(4.59)
If this small-signal condition is satisfied,
W
iD I D  id (4.60) where id  kn
(V  Vt ) gs
L GS
gm 
id
 gs
 kn
W
(V  Vt )
L GS
gm  kn
gm 
W
(V )
L OV
iD
GS
(4.61) transconductance
(4.62)
(4.63)
GS  VGS
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4.6.3 The Voltage Gain
A 
d
  gm RD
 gs
(4.65)
For small-signal
condition
 D  VDD  RD iD
For out of cutoff
Under the small-signal condition,
 D  VDD  RD ( I D  id )
 D  VD  RD id
For saturation
signal component:
 d   id RD   gm gs RD (4.64)
Figure 4.36 Total instantaneous voltages vGS and vD for the
circuit in Fig. 4.34.
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30
4.6.4 Separating the DC Analysis and the Signal Analysis
For the signal analysis,
Ideal constant voltage sources are replaced by short circuits.
Ideal constant current sources are replaced by open circuits.
4.6.5 Small-signal Equivalent-Circuit Model
FET behaves as a voltage-controlled current source.
The input impedance is very, very high.
The output impedance is also high.
Small-signal models for the MOSFET
(a) neglecting the dependence of iD
on vDS in saturation (the channellength modulation effect
(b) including the effect of channellength modulation, modeled by output
resistance ro = |VA| /ID.
To include the channel-length modulation,
V
ro  A
(4.66) (Eq. 4.26 in Sect. 4.2.3), VA  1 / 
ID
1 W 2
I D  kn
V
(4.67)
2
L OV

A  d   gm ( RD //ro )
 gs
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(4.68)
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For PMOS,
use VGS , Vt , VOV , VA , k 'p
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31
4.6.6 The Transconductance gm
gm  kn (W / L)(VGS  Vt )  kn (W / L)VOV (4.69)=(4.61)
- For large gm, we need large (W/L) and (VGS - Vt).
- However, large VG has disadvantage of reducing the
allowable voltage signal swing at the drain.
1
W
Eq. 4.6a, I D  nCox (VGS  Vt )2
2
L
(VGS  Vt )  2 I D k  W / L
gm  2kn W / L I D
(4.70)
cf.) Transconductance of BJT is proportional to the bias current
and independent of physical size and geometry of the device.
Practical example
k   120  A/V 2 , I D  0.5 mA
- gm = 0.35 mA/V for W/L =1
- gm = 3.5 mA/V for W/L =100
- gm = 20 mA/V for BJT with IC = 0.5 mA.
1
W
Eq. 4.6a, I D  nCox (VGS  Vt )2
2
L
kn (W / L)  2 I D /(VGS  Vt )2
gm 
2I D
2I
 D
VGS  Vt VOV
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(4.71)
Three Design Parameters
W/L, VOV, ID
Two the above can be chosen independently.
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Sol) gm  kn (W / L)(VGS  Vt )
EXAMPLE 4.10
Vt=1.5 V, kn’ (W/L) =0.25 mA/V2, VA = 50 V.
Small-signal gain=?, input resistance=?,
maximum input signal =?
VGS  VD  ?
1 W
kn
(VGS  Vt )2
2
L
VD  15  RD I D  15  10 I D (4.74)
Eq. 4.6a, I D 
ro 
o
VA
}
(4.66)
ID
Rin 
 gm gs ( RD // RL //ro ) A 
i
ii
?
o
  gm ( RD // RL //ro )
i
 0.725(10 // 10 // 47)  3.3 V/V
o 
1 
RG   i 

4.3 i
 i [1  ( 3.3)] 
RG
RG
ii  ( i   o ) / RG 
i 
Rin 
To stay in saturation region,
 DS  GS  Vt


i
ii

RG
 2.33 M
4.3
 DS min  GS max  Vt


VDS  A  i  VGS   i  Vt 4.4  3.3 i  4.4   i  1.5

 i  0.34 V
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4.6.6 The T Equivalent-Circuit Model
T Model
Hybrid-π Model
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small-signal Equivalent Circut Model when VSB  0 (i.e., No Body Effect)
small-signal Equivalent Circut Model when VSB  0 (i.e., Including Body Effect)
Table 4.2
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36
4.7 Single-Stage MOS
Amplifiers (Discrete circuits)
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4.7 Single-Stage MOS Amplifiers (Discrete circuits)
IC MOS amplifiers : Chap. 6
4.7 is useful to understand IC amplifier.
4.7.1 The Basic Structure
4.7.2 Characterizing Amplifiers
The material of Sect. 1.5 was limited to unilateral amplifiers.
Now, let’s include non-unilateral amplifiers.
1. Source : υsig + Rsig. Real signal source or previous amplifier.
Load : RL. Real load or previous amplifier.
2. Ri, Ro, Aυo, Ais, Gm do not depend on the value of Rsig and RL.
Rin, Rout, Aυ, Ai, Gυo, Gυ may depend on the value of Rsig and RL.
Figure 4.42 Basic structure of the circuit used to
realize single-stage discrete-circuit MOS amplifier
configurations.
Chap. 4 : unilateral only
Chap. 6 : non-unilateral also
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Ri  Rin RL  , Ro  Rout Rsig 
3. For non-unilateral amplifiers, Rin may depends on RL, Rout may
depends on Rsig.
For unilateral amplifiers, Rin = Ri, Rout = Ro.
4. The loading of the amplifier on the signal is determined by the
input resistance Rin.
5. When evaluating the gain Aυ from the open-circuit gain Aυo, Ro is
the output to use.
When evaluating the overall voltage gain Gυ from its open-circuit
value Gυo, Rout is the output to use.
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39
EXAMPLE 4.11, p304
υsig = 10 mV, Rsig= 100 kΩ. RL. = 10 kΩ
G  G o
υi (mV)
υo (mV)
79
w/o RL
9
90
with RL
8
70
Find all the amplifier parameters.
W/O RL , ( RL   )
90
 10 V/V
9
90
G o 
 9 V/V
10
Ri
A
Ri  Rsig  o
9
Ri
 10
Ri  100
Rin
8

10 Rin  100

Rsig   Rout

R
 1 

sig
RL  0
Ri   Ro

 81.8 k
iosc  A o ii Rin
Rin  400 k
A io 
RL  0
 
  1
 
/ Ro
iosc
 10  81.8 / 1.43
ii
 572 A/A
Rin
400
 8.75 
 350 A/A
RL
10
let's find short-circuit current gain
Ais  iosc / i i , iosc  A o i / Ro
70
 8.75 V/V
8
70
 7 V/V
10
RL
A  A o
RL  Ro
G 
10
8.75  10
10  Ro
Rout  2.86 k
i
Rin

 sig Rin  Rsig
 A
Ri  900 k
with RL connected, A 
10
10  Rout
Rin
short-circuit transconductance
A
10
Gm   o 
 7 mA/V
Ro 1.43
 /R  R
A o  o L  o in
 i / Rin  i RL
A o 
G o 
RL
RL  Rout
To determine υi, we need to know the
value of Rin obtained with RL=0.
iosc  G o sig / Rout
G o 
Ro  1.43 k
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Ri
A
Ri  Rsig  o
 i   sig
Rin
Rin
RL  0
RL  0
 Rsig
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40
gm  kn (W / L)(VGS  Vt )  kn (W / L)VOV (4.69)=(4.61)
(4.70)
- The most widely used of all MOSFET amplifier circuits. gm  2kn W / L I D
2I D
2I
gm 
 D (4.71)
VGS  Vt VOV
4.7.3 The Common-Source (CS) Amplifiers
Bypass capacitor
(~μF)
Bypass capacitor (~μF)
For signal ground
(b) Equivalent circuit of the amplifier for small-signal analysis.
Figure 4.43 (a) Common-source amplifier based
on the circuit of Fig. 4.42.
ig  0
Rin  Ri  RG
 i  sig
RG
Rin
 sig
Rin  Rsig
RG  Rsig
RG (~M )
Rsig
(4.78)
(4.79)
 i   sig
A   gm (ro RD RL ) (4.80)
 gs   i
 o   gm gs ( ro RD RL ) Ao   gm (ro RD ) (4.81)
}
G 

Rin
A
Rin  Rsig 
RG
R  ro RD
gm ( ro RD RL ) (4.82) out
RG  Rsig
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(4.83)
(c) Small-signal analysis performed directly on the amplifier circuit
with the MOSFET model implicitly utilized.
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41
4.7.4 The Common-Source (CS) Amplifier with a Source Resistance
RSac
RSdc
Figure 4.44 (a) Common-source amplifier with a
resistance RS in the source lead.
(b) Small-signal T-equivalent circuit with ro neglected.
o   id ( RD RL )  
gm ( RD RL )
i
1  gm RS
g R
A o   m D
1  gm RS
- The effect ro is not important (SPICE) in discrete-circuit amp.
- The effect ro plays major role and must be taken into A  o   gm ( RD RL ) (4.88)

account in IC amp.
i
1  gm RS

RG
gm ( RD RL )
Rin  Ri  RG (4.84)
G  o 
(4.90)
RG
 sig
RG  Rsig 1  gm RS
 i  sig
(4.85)
RG  Rsig
- R increases dc bias stability. (Sect. 4.5)
1/ gm
i
1
 gs  i
 i

(4.86)
gm
1/ gm  RS 1  gm RS
i
gm i
id  i 

(4.87)
1/ gm  RS 1  gm RS
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s
}
- Rs decreases υgs to reduce nonlinear distortion.
(4.86), (4.58)
- Rs increases the bandwidth (Sect. 4.12).
- Rs decreases gain. (4.90)
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(4.89)
Need trade-off !
Split RS !!
42
4.7.5 The Common-Gate (CG) Amplifier
(b) A small-signal equivalent circuit of the amplifier in (a).
Figure 4.45 (a) A common-gate amplifier based on the circuit of
Fig. 4.42.
(c) The common-gate amplifier fed with a current-signal input.
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Rin 
 i  sig
 i   sig
1
gm
Rin
Rin  Rsig
ii 
1
 Rsig
gm
i
Rin
G 
(4.92)
  sig
1
1  gm Rsig
i
1/ gm
(4.96b)
RG
gm ( RD RL )
(4.90 CS)
RG  Rsig 1  gm RS
(4.97) same as in CS
(4.93)
1
gm

gm ( RD RL )
1  gm Rsig
Rout  Ro  RD
1
gm
Rsig
G 
Rin  Ri  RG (4.84 CS)
(4.91)
Using Fig. 4.45(c), ii  isig
Normally, Rsig
 gm i
1 / gm ,
Rin
 isig
Rin  Rsig
ii  isig
Rsig
1
Rsig 
gm
(4.98)
(4.98a)
Unity-gain current amplifier, current follower !
CG amplifier is applied to the cascode circuit.
id  i   ii   gm i
o  d   id ( RD RL )  gm ( RD RL )i
A  gm ( RD RL ) (4.94)
A o  gm RD
G 
(4.95)
1
gm
A
Rin
A 
A 
1
Rin  Rsig
1  gm Rsig
 Rsig
gm
Microelectronic Circuits - Fifth Edition
Sedra/Smith
1. Unlike the CS amplifier (inverting), CG amp is non-inverting.
2. While the CS amplifier has a very high input impedance, that of the
CG amp is low.
3. Overall voltage gain of the CG amp is smaller than that of CS
amp by the factor of 1+ gmRsig.
(4.96a)
Copyright  2004 by Oxford University Press, Inc.
44
4.7.5 The Common-Drain (CD) or Source-Follower Amplifier
ac ground
Figure 4.46 (a) A common-drain or source-follower amplifier.
(b) Small-signal equivalent-circuit model.
(c) Small-signal analysis performed directly on
the circuit.
Microelectronic Circuits - Fifth Edition
Sedra/Smith
(d) Circuit for determining the output resistance Rout of the
source follower.
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45
Rin  RG
 i  sig
RG
Rin
=sig
Rin  Rsig
RG  Rsig
Usually, RG
( RL
( RL ro ) 
1
gm
(4.100)
G 
RG
RG  Rsig
For RG
ro
ro 
1
gm
RL ro
( RL
(4.102)
Rout 
1
gm
1/ gm ,
(4.104)
1
ro ) 
gm
1 / gm , ro
ro
RL ,
(4.102a)
1
RL 
gm
Rsig , ro
Normally, ro
A o 
RL
(4.101)
1
ro ) 
gm
RL ro
A o 
 i   sig
Rsig ,
RL ro
   i
A 
In many discrete-circuit application, ro
(4.99)
RL ,
G  1
1
gm
(4.106)
(4.105)
Rout 
The source follower has a very high input impedance,
a relatively low output impedance,
a gain less than but close to unity.
(4.103)
Unity-gain buffer amplifier ! (Sect. 1.5)
Normally, ro
1/ gm ,
Output stage of multi-stage amplifier !
A o  1 means the voltage at the source
follows that at the gate.
Source follower !
Microelectronic Circuits - Fifth Edition
Sedra/Smith
Copyright  2004 by Oxford University Press, Inc.
46
Microelectronic Circuits - Fifth Edition
Sedra/Smith
Copyright  2004 by Oxford University Press, Inc.
47
Microelectronic Circuits - Fifth Edition
Sedra/Smith
Copyright  2004 by Oxford University Press, Inc.
48
Microelectronic Circuits - Fifth Edition
Sedra/Smith
Copyright  2004 by Oxford University Press, Inc.
49
Microelectronic Circuits - Fifth Edition
Sedra/Smith
Copyright  2004 by Oxford University Press, Inc.
50
Microelectronic Circuits - Fifth Edition
Sedra/Smith
Copyright  2004 by Oxford University Press, Inc.
51