CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
OCTOBER15
ASSESSMENT_CODE MCA2050_OCTOBER15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
17527
QUESTION_TEXT
What is embedded system? Give one example for embedded system.
Explain characteristics of embedded computers.
An embedded computer is a computer system designed to perform a
particular unction or task. It is embedded as component of a bigger
complete device. Embedded system contain microcontroller dedicated to
complete device.
Microwave, washing machines, air conditioners, printers are examples of
embedded systems.
SCHEME OF
EVALUATION
Characteristics of embedded computers:
1. Real-time performance: The performance requisite in a embedded
application is real – time execution. Speed though in varying degrees, is
an important factor in all architectures. The ability to assure real-time
performance acts as a constraint on the speed needs of the system. Realtime performance means that the agent is assured to perform within
certain time restraints as specified by the task and the environment.
2. Soft real – time: In a number of applications, a more advanced
requisite exists: the standard time for a particular job is constrained and
the number of occurrences when the maximum time is exceeded. Such
techniques are occasionally called soft real – time and they occur when it
is possible to sometimes miss the time limitation on an incident,
provided that not plenty of them are missed.
3. Need to minimize memory size: Memory can be a considerable
element of the system cost. Thus, it is vital to limit the memory size
according to the requirement.
4. Need to minimize memory power: Larger memory also means high
power need. Emphasis on low power is made by the use of batteries.
Unnecessary usage of power needs to be avoided to keep the power need
low.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
17528
QUESTION_TEXT
Write any 10 features of MIPS architecture.
SCHEME OF
EVALUATION
1.It has a five-stage execution pipeline: fetch, decode, execute,
memory access, writeresult.
2.It has a regular instruction set where all instruction are 32 bit
3.There are three – operand arithmetical and logical instruction
4.It consists of 32 general-purpose registers of 32-bits each.
5.There are no status register or instruction side-effects
6.There are no complex instructions
7.It has optional coprocessors for system management and floating –
point
8.It consists of only the load and store instruction access memory.
9.It has a flat address space of 4 Gigabyte of main memory
10.The Memory-management unit maps virtual to actual physical
addresses
11.Optimizing C compiler replaces hand – written assembly code.
12.Its software tool chain knows about hardware and generates
correct code.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73361
QUESTION_TEXT
What is Branch prediction. Explain the Different strategies of branch
prediction
SCHEME OF
EVALUATION
Branch prediction is a method which is basically utilised for handling the
problems related to branch. (1 Mark)
Different strategies of branch prediction include:
1 Fixed branch prediction
In fixed branch prediction, prediction is considered to be fixed. This
approach of branch prediction is easy to implement. This approach
presumes either of the following:
branch is never taken
or
branch is always taken
2 Static branch prediction
Till now it is understood that instead of using a fixed approach,
theperformance can be improved by making use of an approach which
is relianton the type of branch. This type of approach is known as the
static branchprediction. This approach makes use of instruction opcode
for predictingwhether the branch is taken. This approach provides high
prediction correctness. To illustrate this, let us show sample data for
industrial environments. In these types of environments, the prediction
of branche sand loops from all branch-type operations are discussed
below:
branches are about 70%,
loops are about10%
remaining operations include procedure calls/returns
3 Dynamic branch prediction
For making more accurate predictions, this approach considers run-time
history. Here the n branch executions of history are considered and this
information is used for predicting the next one. The experiential study
done by Smith and Lee proposes that this approach provides major
enhancement in prediction accuracy.
(3 Marks each)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73364
i. Write a short notes on available design alternatives for a shared
memory processor
QUESTION_TEXT
ii.
SCHEME OF
EVALUATION
Write any four features of shared memory organization
i.
1. No physical sharing: In this memory system organization, every
processor or a node that consists of more than one processor has its
own private main memory. It can access remote memory connected to
other nodes through interconnection network. This architecture is known
as the non-uniform memory access architecture.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125203
QUESTION_TEXT
Explain Flynn classification of the computer system.
1.
Single instruction Single Data.
2.
Single instruction Multiple Data.
SCHEME OF EVALUATION 3.
Multiple instruction Single Data.
4.
Multiple instruction Multiple Data
(2.5 marks for each)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125204
QUESTION_TEXT
Explain Direct Mapping and Associative Mapping. What are the main
Elements of Cache Design
Direct mapping
Associative memories are very costly as compared to RAM due to the
additional logic association with all cells. Generally there are 2j words in
main memory and 2k words in cache memory. The j-bit memory
address is separated by 2 fields. k bits are used for index field. j-k bits
are long-fields. The direct mapping cache organization utilizes k-bit
indexes to access the cache memory and j-bit address for main
memory. Cache words contain data and related tags. Every memory
block is assigned to a particular line of cache in direct mapping. But if a
line already contains memory block when new block is to be added then
the old memory block is removed
Associative mapping
SCHEME OF
EVALUATION
Associative mapping is used in cache organization which is the quickest
and most supple organization. Addresses of the word and content of
the words are stored in associative memory. It means cache can store
any word in main memory.
(2 Marks each)
Main elements of Cache design are:
1. Cache Size: The size of cache should be small enough to bring overall
cost per bit closer to the main memory. On the contrary, the size must
be large enough, so that the cache and overall access time be
somewhat equal. Mostly large caches are slow than smaller ones
because if the cache is large then there are numerous gates are
concerned in addressing the cache which makes it slow
2. Mapping Function: The two types of mapping—Direct Mapping and
Associative Mapping
3. Replacement Algorithm: LRU (Least recently Used), FIFO (First-in,
First-out), LFU (Least Frequently Used) or some Random one i.e. simple
to build in hardware.
4. Write Policy: Write Through, Write Back or Write Once.
5. Line Size: Optimum size depends on workload.
6. Number of Caches: Single or two levels and Unified or split.
(1 Mark each)