Futures for DSM Physical Implementation:
Where is the Value, and Who Will Pay?
Andrew B. Kahng
abk@cs.ucla.edu , http://vlsicad.cs.ucla.edu
UCLA Computer Science Department
12th DA Show, Tokyo
July 14, 2000
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Subwavelength Optical Lithography
Subwavelength Gap since .35 m
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Numerical Technologies, Inc.
3
“The Design Productivity Gap”
Potential Design Complexity and Designer Productivity
Logic Tr./Chip
Tr./S.M.
Equivalent Added Complexity
68 %/Yr compounded
Complexity growth rate
$10
$3
$1
21 %/Yr compound
Productivity growth rate
“How many gates
can I get for $N?”
Year
Technology
3 Yr. Design
Chip Complexity Frequency
Staff
Staff Cost*
1997
250 nm
13 M Tr.
400 MHz
210
90 M
1998
250 nm
20 M Tr.
500
270
120 M
1999
180 nm
32 M Tr.
600
360
160 M
2002
130 nm
130 M Tr.
800
800
360 M
* @ $ 150 k / Staff Yr. (In 1997 Dollars)
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Source: SEMATECH
4
Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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What is design closure?
user constraints
RTL
“front end consistent
with back end”
synthesis
netlist
logic
optimization/
timing verif
meet constraints here
placement

routing
meet constraints there
layout
What is the problem ?
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source: K. Keutzer, DAC 2000
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“Olympic Flame”
ARISTO
Library
TYPICAL DESIGN FLOW
Design
Constraints
IP Blocks
Design
Netlist
Gate-Level
Verilog
RTL
Verilog
Hard Blocks
Concurrent
Block
Synthesis
Concurrent Block Partitioning,
Clustering & Placement
Block Shaping, Compaction &
Concurrent Port Placement
Early Planning
Gate-Level Optimization
Design
Refinement
Gate-Level Place & Route
Top-Level Routing
Chip
Assembly
RC Extraction
PREDICTABLE HIERARCHICAL DESIGN CONVERGENCE
Timing Analysis
Aristo, DAC-2000 panel
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“Recycle Bin”
RTL
Behavioral / RTL
synthesis
statistical WLM
timing library
Design Signoff
Route
logic
Increasi
ng
Modelin
g
Detail
Physical
Prototyping
GDSII
Monterey, DAC-2000 panel
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“Anakin Skywalker’s Pod Racer”
3DPrepare
Extraction
Database
Timing
Sign-off
RTL
Synthesis
Delay
True-3D
Calculation
Parasitics
Place
&
Route
Sequence
Timing
Timing
Analysis
Analysis
Interconnect
Interconnect
Driven
Driven
Optimization
Optimization
Driver sizing,
topology-based
optimization
Sequence, DAC-2000 panel
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Clear Thinking: Basics of Design Convergence
What must converge ?
 logic, timing, and spatial embedding
 support front-end signoff, provide predictable back-end
Ways to achieve Convergence through Predictability
 correct by construction (“assume, then enforce”)



constraints and assumptions passed downstream; not much goes upstream
ignores concerns via guardbanding
separates concerns as able (e.g., FE logic/timing vs. BE spatial embedding)
 construct

by correction (“tight loops”)
logic-layout unification; synthesis-analysis unification, concurrent optimization
 elimination


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of concerns
reduced degrees of freedom, pre-emptive design techniques
e.g., power distribution, layer assignment / repeater rules, GALS/LIS
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What Must A Design Closure Tool Look Like ?
Input
 RT-level HDL + technology + constraints
Output
 “go”: recipe for invocation and composition of “commodity” SP&R
 “no go”: diagnosis of RTL code problems
Logical and physical hierarchies co-evolve
 spatial: top-down coarse placement  physical hierarchy
 logic/timing: implementable RTL  logical hierarchy
 limits of human fanout, organizations  always have hierarchy

natural sequence of no-floorplanning, phys-floorplanning, RTL-floorplanning...
Details (must construct, predict, ignore, eliminate, ...)
 pin optimizations, interconnect planning, hierarchy reconciliations,
budgeting mechanisms, compatibility with downstream SP&R, ...
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DON’T Develop This RTL Planning Technology
Don’t spend too much time packing blocks that will change
 goal = early diagnosis, or handoff to commodity SP&R
 pre-synthesis uncertainty = +/- 15% area, timing


wirelength, path timing  must be connectivity-centric, not packing-centric
easier to work on direct realizations of the floorplan, not representations
 need
relative coarse placement that adapts to incremental ECOs
Don’t over-constrain block shaping (rectangles, L’s, T’s)
 placers handle constraints w/ granularity = site spacing, row height
 constructive pin assignment  don’t need roundness
 path timing optimization  may even want disconnected shapes
Don’t under-constrain layout region
 fixed-die planning: simultaneous zero-whitespace, zero-overlap
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Do Allow the Following...
1.0
0.5,0.5
1.0
Blk A
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Blk B
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It Is What the Cells Want Anyway !
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Do Develop This RTL Planning Technology
RTL partitioning
 understand interaction b/w block definition and placement quality
 recognize and cure a physically challenged logic hierarchy
Global interconnect planning and optimization
 symbolic route representations to support block plan ECOs
Controllable SP&R back end (including power/clock/scan)
Incremental / ECO optimizations, and optimizations that are
“robust” under partial or imperfect design knowledge
Better estimators (“initial WLMs”)
 to
account for resource, topological heterogeneity
 to account for optimizations (placement, ripup/reroute, timing)
 “earliest RTL signoff with detailed P&R knowledge”
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Conclusion
RTL-to-GDSII will commoditize SP&R market sectors
 Many
solutions are reasonable and will survive in the marketplace
 RTL-down SP&R becomes a “commodity”
 No
solution is complete
 Key
missing pieces include RTL partitioning; hierarchy and block
management; real working RTL diagnosis and signoff
 Individual
point technologies (e.g., global placement or detailed
routing) become less valuable  integration is most important
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Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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Subwavelength Optical Lithography
Subwavelength Gap since .35 m
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Numerical Technologies, Inc. 20
Optical Proximity Correction (OPC)
Corrective modifications to improve process control
 improve
yield (process window)
 improve
device performance
OPC Corrections
No OPC
With OPC
Original Layout
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Future OPC-Related Technologies
WYSIWYG broken  (mask) verification bottleneck
Function-aware OPC insertion
 OPC insertion is for predictable circuit performance, function
 tool understands functional intent, makes only the corrections
that win $$$, reduce performance variation
 applies to mask inspection as well
OPC- and manufacturing-aware layout
 don’t make corrections that can’t be manufactured or verified
 model effects of geometry on OPC cost needed to yield function
 understand (data volume, verification) costs of breaking hierarchy
Difficult solutions to flow issues
 e.g., how to avoid making same corrections 3x (library, router, PV)
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Phase Shifting Masks (PSM)
conventional mask
phase shifting mask
glass
Chrome
Phase shifter
0 E at mask 0
0 E at wafer 0
0 I at wafer 0
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Double-Exposure Bright-Field Alternating PSM
Positive photoresists for poly, metal
 unexposed areas = printed features
0
180
180
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+
=
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Why is Alternating PSM Valuable and Essential ?
PSM enables smaller transistor gate lengths Leff
 “critical” polysilicon features only (gate Leff)


faster device switching  faster circuits
better critical dimension (CD) control  better parametric yield, $/wafer
Full-chip PSM (poly, local interconnect)  denser layouts
 smaller
die area  more $/wafer
 achieving
Roadmap for device density depends on PSM
Data points
 25
nm gates manufactured with 248nm DUV steppers (NTI + MIT
Lincoln Labs, June 2000)
 90nm
gates in production at Motorola, Lucent since 1999
Alternative: $5 B fab with equipment that doesn’t exist yet
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The Phase Assignment Problem
Assign 0, 180 phase regions such that critical features
with width < B are induced by adjacent phase regions
with opposite phases
0
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180
26
Key: Global 2-Colorability
Odd cycle of “phase implications”  layout cannot be
manufactured
 layout
verification becomes a global, not local, issue
180
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0
?
180
180
0
180
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Critical features:
F1,F2,F3,F4
F2
F1
F4
F3
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F2
F1
Opposite-Phase
Shifters (0,180)
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F4
F3
29
S3
F2
S4
S1
F1
S8
F4
S7
S2
S5
F3
S6
Shifters: S1-S8
PROPER Phase Assignment:
 Opposite phases for opposite shifters
 Same phase for overlapping shifters
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S3
F2
S4
S1
F1
S8
F4
S7
S2
S5
F3
S6
Phase Conflict
Proper Phase Assignment is IMPOSSIBLE
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Phase Conflict Resolution
S3
F2
S4
S1
F1
S8
F4
S7
S2
Phase Conflict
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S5
F3
S6
feature shifting
to remove overlap
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Phase Conflict Resolution
S3
F2
S4
S1
F1
S8
F4
S7
S2
F3
Phase Conflict
feature widening to turn
conflict into non-conflict
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Future PSM-Related Technologies
UCLA-Cadence: first comprehensive methodology for
AltPSM layout design
3-way shared responsibility for phase-assignability
 good


layout practices (local geometry)
no T shapes, no doglegs, even-length transistor fingers, ...
but no complete set of “rules” exists
 automatic

latest technology: optimal conflict resolution for 50K polygons in 6 sec
 reuse

phase conflict resolution (global 2-colorability)
of layout (free composability)
problem: guarantee reusability of phase-assigned layouts, such that no odd
cycles can occur when the layouts are composed together in a larger layout
Changes all flows: library design, custom design, SP&R
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Macroscopic Process Effects
Contact Overetch
causes leakage
Dummy Fill controls
several types of process
distortions :
Variation greatly reduced.
Dummy Area Fill
Large topographical variation caused by soft Pattern
pad and mechanical properties
Dense
Array
CMP, SOG
Isolated Transistor
Dense Array
Contact Overetch
causes
leakage
Reduced
contact etch
variation
RIE
Isolated Transistor
Dense Array
Dummy Fill Pattern
CVD
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R. Pack, Cadence
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Field-Dependent Aberration
Field-dependent aberrations cause placement errors and
distortions
CELL _ A( X1, Y1 )  CELL _ A( X 0 , Y0 )  CELL _ A( X 2 , Y2 )
Big Chip
Lens
Towards Lens
Cell A
Field-dependent
aberrations
affect the fidelity
and placement
of critical circuit
features.
(X1 , Y1)
Cell A
Wafer
Plane
(X0 , Y0)
Cell A
Center: Minimal
Aberrations
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Edge: High
Aberrations
(X2 , Y2)
R. Pack, Cadence
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Conclusions
RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
 Closely
 Unites
related to foundry capital expenditure
EDA with much of mask industry, even process development
 Expands
scope of physical “verifications”, moves awareness
upstream into “syntheses” (logic, layout)
 Very
comprehensive changes to data model, infrastructure, flows
 Unified,
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front-to-back solutions will win
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Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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The Productivity Gap
Potential Design Complexity and Designer Productivity
Logic Tr./Chip
Tr./S.M.
Equivalent Added Complexity
68 %/Yr compounded
Complexity growth rate
$10
$3
$1
21 %/Yr compound
Productivity growth rate
“How many gates
can I get for $N?”
Year
Technology
3 Yr. Design
Chip Complexity Frequency
Staff
Staff Cost*
1997
250 nm
13 M Tr.
400 MHz
210
90 M
1998
250 nm
20 M Tr.
500
270
120 M
1999
180 nm
32 M Tr.
600
360
160 M
2002
130 nm
130 M Tr.
800
800
360 M
* @ $ 150 k / Staff Yr. (In 1997 Dollars)
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Source: SEMATECH
39
Mask Cost
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O(25 mask levels) ~ “$1M mask set” in 130nm
But: average only 500 wafers per mask set !
40
“Keep the Fabs Full”
Design technology must keep manufacturing facilities fully
utilized with:
 high-volume
parts
 high-margin
parts
Foundry capital cost > $2B
 How
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much value of new designs is needed to fill the fab ???
41
Design Productivity Need + DSM
= 2 EDA Trends
Application /
Behavior
Level of Abstraction
Design Entry Level
SW/HW
Implementation
Gap
RTL
Gate-level “platform”
Today
Tomorrow
Mask
Effort/Value
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source: MARCO GSRC
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Fab Amortization  Close the Implementation Gap
Level of Abstraction
Application
SW/HW
Design Entry Level
Hand-off “platform”
RTL
Mask
Effort/Value
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source: MARCO GSRC
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Design Productivity Gap  Low-Value Designs?
Percent of die area that must be occupied by memory to
maintain SOC design productivity
100%
80%
60%
% Area Memory
40%
% Area Reused
Logic
20%
% Area New Logic
19
99
20
02
20
05
20
08
20
11
20
14
0%
Source = Japanese system-LSI industry
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Reduce Back-End Effort ?
V S G S V S
Example: repeating dense wiring fabric
pattern at minimum pitch
V S G S V S
V
S
G
SV
S
- Eliminates signal integrity, delay uncertainty concerns
- But has at least 60% - 80% density cost
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source: MARCO GSRC
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Improve IP Reuse Productivity ?
P1
P3
P2
P4
P5
Pearls (the IP Processes)
MicroShells (the IP Requirements)
MacroShells (the Protocol Interface)
Communication Channels
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P6
P7
source: MARCO GSRC
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QUALITY Problem : > 1000x Energy-Flexibility Gap
Energy Efficiency
MOPS/mW (or MIPS/mW)
1000
Dedicated
HW
100
10
1
100-200 MOPS/mW
Reconfigurable
Processor/Logic
10-50 MOPS/mW
1 V DSP
3 MOPS/mW
ASIPs
DSPs
Embedded Processors
LP ARM
0.5-2 MIPS/mW
0.1
Flexibility (Coverage)
Source: Prof. Jan Rabaey, UC Berkeley
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“Keep the Fabs Full”
Design technology must keep manufacturing facilities fully
utilized with:
 high-volume
parts
 high-margin
parts
What happens when design technology “fails” ?
 not

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enough high-value designs
the semiconductor industry will find a “workaround”

reconfigurable logic

platform-based design
48
Platform-Based Design
System Application
Simple &
Direct
Application
Compilation
Sophisticated
Compiler
Architecture
Structured
Custom
RTL
Flow
Once per
Application
FPGA
FPGA & Config.
Microarchitecture
GPP Processor
Platform
Compilation
Silicon Process
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DSP
GPP
Once per
Family
source: MARCO GSRC
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Conclusions
RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Design productivity gap threatens design quality
 ASIC business model is at risk
 TAT
achieved at cost of QOR
 low
QOR  low silicon value
 electronics
industry chooses reprogrammable, platform-based
“workarounds”
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Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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EDA Industry Structure: Vendor Side
Tool usage focus still the core of the business model
 slows
down the move to open systems, open infrastructure
Some indicators of “immaturity”
 lack

 no
of metrics and other common infrastructure
LEF/DEF, SPEF, *SPF, OLA, .lib, ... are a minimal start, were slow to develop
differentiation between strategic, commodity technology
Some indicators of “poor health”
 customer
integration investment is 2.5x - 4x times tool investment
 EDA R&D
 20% of revenue, but 80+% of R&D = support, infrax
 R&D
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often provided by customers (designers), outsourced (M&A)
52
EDA Industry Structure: Customer Side
Collectively, insist that EDA be “everything to everyone”
 fragmentation of
vendor R&D resource, lots of secret options, ...
 tools attempt to fit in all methodologies  fit in none
Won’t let EDA vendors evolve to a more sustainable model
for low ASPs while spending 4x on integration  low R&D
levels
 sometimes invest in fragmentation of R&D talent (20 SP&R, 70
verif startups)
 push
No differentiation between strategic, commodity technology
 one-offs, hidden
options
 very little cooperative foundation: e.g., data model + API, silicon
calibration, library char, RLC extraction, gate/int delay calc, STA,
physical verification
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Must Escape “Death Spiral”
“Failure of EDA”
  why pay for it
  why invest in it
  why work on it
 ...
Must stop wasting scarcest of all resources: brains
 how many GDSII parsers do we need ? how many interconnect
delay calculators ? how many netlist connectivity data models ?
 acknowledge de facto commodity technology
 turn these technologies into common infrastructure
Mature behavior is required
 with
respect to “strategic vs. commodity” distinction
 with respect to “control”
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Conclusions
RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Design productivity gap threatens design quality
EDA industry must evolve and mature to achieve EDA
industry productivity
 eliminate
wastage on duplicated commodity infrastructure
 acknowledge
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and share de facto commodity technologies
55
Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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CAD Life Cycle Questions
What will the design problem look like?
How can we quickly develop the right design technology?
Did I really solve the problem?
 Did
the design process improve?
 Did
achievable design envelope get bigger?
Proposal: We MUST develop shared infrastructure to answer
all three questions
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1. Technology Extrapolation
Evaluates impact of
What is the most power-efficient noise
management strategy?
design technology
 process technology

How and when do L, SOI,
SER, etc. matter?
Evaluates impact on
achievable design
 associated design problems

Questions to be addressed:
Will layout tools need to perform process
simulation to effectively model cross-die
and cross-wafer manufacturing variation?
What will the design problem look like ?
Sets requirements for CAD tools, methodologies, investment
Familiar example: ROADMAPS
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Optimal Repeater Sizing
Most commonly used optimal repeater sizing expression
(Bakoglu)
S
New study:
RD Cint
RintCin
Sweep repeater size for single stage in the chain
 Examine both delay and energy-delay product

Critical Path Delay (ns)
Lseg = 2.14 mm
W=S=1m
W=S=0.5m
2.2
6
2.0
5
1.8
4
1.6
1.4
3
1.2
2
1.0
0.8
1
0
100
200
300
400
Repeater Size (X min size)
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500
Normalized Energy-Delay Product
2.4
Bakoglu
optimal sizing
59
Cu Resistivity: Effect of Line Width Scaling
Global
525
Semiglobal 320
Local
250
ITRS 1999 Line width (nm)
280
170
133
95
58
48
Diffuse scattering
Elastic scattering
Effect of 5 nm Barrier
• Conformal 5 nm barrier assumed
• Even a 5 nm barrier will increase
resistivity drastically
Effect of Electron Scattering
• No barrier assumed
• Electron scattering increases resistivity
• Lowering temperature has a big effect
source: MARCO IFRC
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Cu Resistivity: Barriers Deposition Technology
Atomic Layer Deposition (ALD)
Ionized PVD
Collimated PVD
• 5 nm barrier assumed at the thinnest spot
• No scattering assumed, I.e., bulk resistivity
Interconnect dimensions scaled according to ITRS 1999
source: MARCO IFRC
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What Technology Extrapolation is Available Today?
Too many Roadmaps
ITRS, JISSO, STARC, … Roadmaps
 some university tools: SUSPENS, GENESYS, RIPE, BACPAC, …
 numerous tools in industry

Observations
everyone predicts “same” parameters but different assumptions, inputs:
near-total duplication of effort !!!
 no documentation or visibility into internal calculations
 “hard-wired”  cannot easily test other modeling choices
 missing: models of CAD tools and optimizations (what is really
“achievable”?)
 missing: scope, comprehensive coverage

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Shared, Worldwide Technology Extrapolation System
Flexibility
edit or define new parameters and relations between them
 perform specific studies (but different studies at different times)

Quality
continuous improvements
 world-wide participation of experts

Transparency
open-source mechanism
 models visible to the user

No more redundant effort
permanent repository of first choice
 adoptability and maintainability

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GTX: GSRC Technology Extrapolation System
GTX is set up as a framework for technology extrapolation
“Living Roadmap”
Knowledge
User inputs
Parameters (data)
Rules (models)
Pre-packaged
Rule chain (study)
GTX
Implementation
Engine (derivation)
GUI (presentation)
Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/
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2. CAD-IP Reuse
How can we quickly develop the right design technology?
Problem: Currently takes 5-7 years to get a leading-edge
algorithm into production tools
 Result:
Must solve today’s design problems with yesterday’s CAD
technology
Problem: Published descriptions insufficient for replication
or even comparison of algorithms
 Result:
Cannot identify, evaluate or advance the CAD technology
leading edge
 IF WE DO NOT KNOW WHERE THE LEADING EDGE OF CAD
TECHNOLOGY IS, WE HAVE A REAL PROBLEM !!!
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Unclear Leading Edge of CAD: A Real Problem
Comparison of two LIFO-FM partitioner implementations
Min and Ave cut sizes from 100 single-start trials
Tolerance
LIFO-FM
Paper1
2%
Paper2
Paper1
10%
Paper2
Min
Ave
Min
Ave
Min
Ave
Min
Ave
Ibm01 Ibm02 Ibm03 Ibm04 Ibm05 Ibm06
450
2701
366
594
270
486
244
445
648
2459 3201
12253 16944 20281
301
1588 1014
542
2688 1802
313
1624
544
3872 12348 2383
266
1057
561
405
1993 1290
2397
3420
2640
3382
1874
3063
2347
3222
1436
16578
1008
1746
1479
14007
821
1640
Papers 1, 2 both published since mid-1998
This is a crisis !
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2. CAD-IP Reuse
How can we quickly develop the right design technology?
Problem: Currently takes 5-7 years to get a leading-edge
algorithm into production tools
 Result:
Must solve today’s design problems with yesterday’s CAD
technology
Problem: Published descriptions insufficient to enable
replication or even comparison of algorithms
 Result:
Cannot identify, evaluate or advance the CAD technology
leading edge
The TAT and QOR problems are not only for CAD
customers, but for CAD itself !!!
 productivity
of CAD tool development (time-to-market)
 quality of resulting CAD tools (quality-of-result)
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Analogy: Hardware Design :: CAD Tool Design
Hardware design is difficult
 complex electrical engineering and optimization problems
 mistakes are costly
 verification and test not trivial
 few can afford to truly exploit the limits of technology
 A Winning Approach: Hardware IP reuse
CAD tools design is difficult
 complex software engineering and optimization problems
 mistakes can be showstoppers
 verification and test not trivial
 few can manage complexity of leading-edge approaches
 A "Surprising Proposal”: CAD-IP reuse
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What is CAD-IP?
Data models and benchmarks
 context descriptions and use models
 testcases and good solutions
Algorithms and algorithm analyses
 mathematical formulations
 comparison and evaluation methodologies for algorithms
 executables and source code of implementations
 leading-edge performance results
Traditional (paper-based) publications
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The Bookshelf: A Repository for CAD-IP
“Community memory” for CAD-IP
 data
models
 algorithms
 implementations
Publication medium that enables efficient CAD R&D
 benchmarks,
 algorithm
 quality
performance results
descriptions and analyses
implementations (e.g., open-source UCLA PDTools)
Simplified comparisons to identify best approaches
Easier for industry to communicate new use models
http://vlsicad.cs.ucla.edu/GSRC/bookshelf
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Proposed Change for Entire EDA Community
Proposal: Data model and API are non-competitive and
non-differentiating
 Genesis,
MilkyWay, CHDStd-IDM, UDM-Nike, … all very similar !
 should be commoditized and shared by the community
 “coopetition” distributes infrastructure burden, frees R&D resources

coopetition = cooperation + competition
 Common data model across multiple vendors, users
 common API
is necessary; common database is not necessary
 “control” issues solved by open-source model (www.openeda.org)
 issues
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of integration and adoption costs still to be overcome
71
3. METRICS
Did I really solve the problem?
Foundation of design optimization:
 understanding of what should be optimized by which heuristic
 understanding of design as a process
There are no standards or infrastructure for measuring and
optimizing the semiconductor design process
“METRICS” = “measure, then improve”
 design
becomes less of an art and more of a formal discipline
Infrastructure
 design process data collection infrastructure
 data mining / visualization / diagnosis infrastructure
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METRICS System Architecture
Tool
Transmitter
Tool
Tool
Transmitter
Transmitter
wrapper
Java
Applets
API
XML
Inter/Intra-net
Web
Server
DB
Reporting
Data
Mining
Metrics Data Warehouse
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Benefits of METRICS
Benefits for project management
 accurate

up front estimates for people, time, technology, EDA licenses, IP re-use...
 accurate


resource prediction at any point in design cycle
project post-mortems
everything tracked - tools, flows, users, notes
no “loose”, random data left at project end
 management

console
web-based, status-at-a-glance of tools, designs and systems at any point in
project; correct go / no-go decisions as early as possible
Benefits for tool R&D
 feedback
 real
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on tool usage and parameters used
benchmarking
74
Example Diagnoses
Placer runtime is linear in number of cells  GOOD !
 CPU_TIME = 12 + 0.027 NUM_CELLS (corr = 0.93)
Placer runtime becomes unpredictable at two particular
utilization thresholds  BAD !
 80%,
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95%
75
The Industry Needs METRICS Standards
 Standard metrics naming across tools

same name  same meaning, independent of tool supplier

generic metrics and tool-specific metrics

no more ad hoc, incomparable log files
 Standard schema for metrics database
 Standard middleware for database interface
 See:
http://vlsicad.cs.ucla.edu/GSRC/METRICS
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CAD Life Cycle Questions
What will the design problem look like?
 answer:
technology extrapolation
How can we quickly develop the right design technology?
 answer:
CAD-IP reuse
Did I really solve the problem?
 Did
the design process improve?
 Did
achievable design envelope get bigger?
 answer:
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Metrics
77
Conclusions
RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Design productivity gap threatens design quality
EDA industry must evolve and mature to achieve EDA
industry productivity
Open, shared infrastructure can restore TAT, QOR of design
technology
3
initiatives: Technology Extrapolation, CAD-IP Reuse, and
METRICS
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Outline
Future DSM physical implementation technologies
 design
closure
 design-manufacturing
interface
Valuations
 the
significance of design productivity and design quality
 structural
aspects of the EDA industry
Values
 toward maturity
and a design productivity renaissance
Conclusions: Who Will Pay ?
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“We Must Solve the CAD Productivity Challenges”
“Death Spiral” is a bad local optimum configuration
 not enough value, not enough R&D, fragmentation of R&D
The design quality gap is just as dangerous as the design
productivity gap
 ASIC
business model is at risk !
Solution lies in maturity of the EDA industry
 “coopetitive” behavior of vendors and customers, together
Future
Today
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Happiness
80
“We Will Solve the CAD Productivity Challenges”
Build the non-differentiating, open-source EDA foundation



Bottom Up: data model (+API), concrete syntax (e.g., .lib + XML), tech
extrapolation, silicon calibration/characterization, performance analyses, ...
EDPS, CHDStd, DAPIC experiences = useful foundation
world-wide cooperation needed (Japan/Asia, North America, Europe)
Understand that bottom-up commoditization of tools and
adapters is inevitable




Bottom Up: Analyses first (RCX, DC, STA), then Syntheses (S, P & R)
pure tools $ static (?), but value remains in being best at leading edge
enormous resource savings in duplicated R&D, maintenance
more value from integrations, methodologies, faster technology delivery
Long-term: EDA moves upward in value chain


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escapes “service” role
becomes more aware, specific to markets, manufacturing process
81
“Who Will Pay?”
Costs of cooperating are less than costs of not cooperating
Benefits of cooperation are immense
 free
up brains to improve Design Technology TAT and QOR
 technology
extrapolation + CAD-IP reuse + Metrics
delivery of solutions the right problems, at the right time, with
measurable impact
=
We should welcome costs of openness, shared infrastructure
 academia,
vendor + internal EDA, designer communities together
It is a great future, if we make it happen !
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THANK YOU !
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EXTRA SLIDES
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Synergies
Feasibility / sanity
checkers to embed
within a tool flow
GTX
Optimized design
processes,
calibration data
for modeling
CAD
optimization
Metrics
Estimates of
best-optimized
design, optimal
tradeoffs
Which problems
are critical?
What will
instances
look like?
CAD-IP
Reuse
Models, measures
of algorithmic
activity
Objective functions,
tool QOR metrics
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GTX Engine
Knowledge
User inputs
GTX
Parameters (data)
Rules (models)
Pre-packaged
Rule chain (study)
Implementation
Engine (derivation)
GUI (presentation)
Contains no domain-specific knowledge
Evaluates rules in topological order
Performs studies
Multiple values through “sweeping”
Runs on three platforms (Solaris, Windows and Linux)
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GTX Graphical User Interface (GUI)
Provides user interaction
Visualization (plotting, printing, saving to file)
4 views:
Parameters
 Rules
 Rule chain


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Values in chain
87
The World of the Living Roadmap
Firewall
Technology
Models
The
Internet
Proprietary
Models
Sematech, GSRC
University
Researchers
Richard Newton
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“The Golden Copy”
88
Challenges for Applied Algorithmics
Research in mature areas can stall
 incremental
research - difficult and risky

implementations not available  duplicated effort

too much trust  which approach is really the best?

some results may not be replicable

‘not novel’ is common reason for paper rejection
 exploratory
research - paradoxically, lower-risk

novelty for the sake of novelty

yet, novel approaches must be well-substantiated
Pitfalls: questionable value, roadblocks, obsolete contexts
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“What Are Some Concrete, Industry-Wide Steps?”
First step: open minds
Second step: agreements on scope of design activity
 bound
the interoperability problem by defining canonical design
states, e.g.:



cycle-accurate microarchitecture
gate-level placement
global-routed but not detailed-routed
Third step: proofs that coopetition is feasible
 how



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different or similar are (for example):
foundry process/rule description formats? library model generators?
IDM/CHDStd, UDM, Genesis, MilkyWay, ...?
AWE, ramp-Elmore, etc. interconnect delay calculations?
90
Where is the Solution ? (DAC-2000 Panel)
A: RTL estimation
B: RTL synthesis + optimization
C: gate-level estimation
D: gate-level logic optimization
E: cell + wire sizing + physical support (e.g., P&R)
F: block placement, floorplanning + wireplanning + budgeting
G: gate-level place and route
H: other
Company
Cadence
Synopsys
Avant!
Magma
Aristo
Sequence
Monterey
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A
25
0
5
0
B
10
30
20
10
25
0
0
15
C
5
0
0
0
5
0
D
10
20
20
0
10
20
10
E
10
10
35
50
20
50
7.5
F
25
25
20
0
30
15
10
G
15
15
25
40
10
15
7.5
H
0
0
0
0
0
0
50
91
Perfect Rectilinear Floorplanning
Fixed-die planning:
find a coarse global floorplan, then
migrate whitespace  overlap such that both disappear
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See, for example: http://vlsicad.cs.ucla.edu/SLIP2000/
Mn
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93
What Does Process Variability Imply for EDA ?
VERY DIFFICULT PROBLEMS !
We require much deeper understanding of process
 coma effects (lens aberration)
 halation (iso-dense effects on etch dynamics)
 statistical variation in ion implant
Performance verification infrastructure may change
 E.g., “delay” is no longer a number – it is a distribution
Must have complete, integrated, front-to-back solutions
 All three examples: OPC, PSM, Area Fill
Long-term: must drive process requirements from system
architecture and design technology roadmaps
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RC and RLC Interconnect Delay Models
Five different interconnect models
Bakoglu’s model (RC)
 [Alpert, Devgan and Kashyap, ISPD 2000] (RC)
 [Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC)
 [Kahng and Muddu, TCAD 1997] (RLC)
 Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC)

225
RC_ADK
145
RC_B
175
Wire Delay (ps)
Wire Delay (ps)
RC_ADK
RLC_ADK
RLC_IFN
125
RLC_KM
HSPICE
75
RC_B
RLC_ADK
125
RLC_IFN
105
RLC_KM
85
HSPICE
65
45
25
3.0
4.0
5.0
6.0
7.0
Wire Length (mm)
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8.0
9.0
10.0
25
0.4
0.6
0.8
1.0
1.2
1.4
Wire Width (µm)
95
Generic and Specific Tool Metrics
Generic Tool Metrics
tool_name
tool_version
tool_vendor
compiled_date
start_time
end_time
tool_user
host_name
host_id
cpu_type
os_name
os_version
cpu_time
string
string
string
mm/dd/yyyy
hh:mm:ss
hh:mm:ss
string
string
string
string
string
string
hh:mm:ss
Placement Tool Metrics
num_cells
num_nets
layout_size
row_utilization
wirelength
weighted_wl
integer
integer
double
double
double
double
Routing Tool Metrics
num_layers
integer
num_violations integer
num_vias
integer
wirelength
double
wrong-way_wl double
max_congestion double
Partial list of metrics now being collected in Oracle8i
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Example Testbed: Cadence SLC Flow
QP
DEF
Incr. Placed DEF
LEF
GCF,TLF
CTGen
Clocked DEF
Constraints
QP Opt
Optimized DEF
M
E
T
R
I
C
S
WRoute
Routed DEF
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97
Current Status of METRICS Initiative
 Current status
complete prototype of METRICS system with Oracle8i, Java Servlet,
XML parser, and transmittal API library in C++
 METRICS wrapper for Cadence and Cadence-UCLA flows, front-end
tools (Ambit BuildGates and NCSim)
 easiest proof of value: via use of regression suites

 Issues for METRICS constituencies to solve
security: proprietary and confidential information
 standardization: flow, terminology, data management, etc.
 social: “big brother”, collection of social metrics, etc.

 Ongoing work with EDA, designer communities to identify tool
metrics of interest
users: metrics needed for design process insight, optimization
 vendors: implementation of the metrics requested, with standardized
naming / semantics

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GTX Current Status
Models implemented
cycle-time models of SUSPENS (with extension by Takahashi), BACPAC
(Sylvester, Berkeley), Fisher (ITRS)
 currently adding


GENESYS (with help from Georgia Inst. Tech.)

RIPE (with help from Rensselaer Univ.)
new device and power modules (Synopsys / Berkeley)
 new SOI device model (Synopsys / Berkeley)
 inductance models (Silicon Graphics / Berkeley / Synopsys)
 yield and die cost models (CMU)

Studies performed in GTX
model and parameter sensitivity analyses
 design optimization studies

Seeking contributions, suggestions of new models, studies
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