Detailed Routing:
New Challenges
Detailed Routing:
New challenges
• Manufacturers use different wire widths
 Vias connecting wires of different widths
−  block additional routing resources on the layer with the
smaller wire pitch
2
Detailed Routing:
New challenges
W2
U2
U1
E2
E1
M6
M5
M4
M3
M2
M1
130 nm
B2
B1
M5
M4
M3
M2
M1
90 nm
B3
B2
B1
M4
M3
M2
M1
65 nm
E1
B3
B2
B1
C2
C1
M4
M3
M2
M1
45 nm
W1
E2
E1
B3
B2
B1
M5
M4
M3
M2
M1
© 2011 Springer Verlag
Representative layer stacks
for 130 nm - 32 nm
technology nodes
32 nm
3
Detailed Routing:
New challenges
• Manufacturing yield: a key concern in detailed
routing
 Redundant vias and wiring segments as backups
(via doubling and non-tree routing)
 Manufacturability constraints (design rules) become
more restrictive  complicate detailed routing
− Example: design rules specify minimum allowed spacing
between wires and vias depending on their widths and
proximity to wire corners.
− Example: Recent spacing rules take into account multiple
neighboring polygons.
4
Via Doubling
5
Detailed Routing:
New challenges
• Detailed routers must account for manufacturing
rules and the impact of manufacturing faults
 Via defects/performance degradation (from
misalignments):
− Via doubling during or after detailed routing
− Area penalty
 Interconnect defects:
− Non-tree routing: Add redundant wires to already routed nets
(postprocess)
 Antenna-induced defects:
6
Antenna Effect
• Recent DFM Issue
 Long metal lines and vias introduce antenna
violations.
 Conductor layers fabricated from lowest layer to
highest layer.
 The etch process builds up the electrical charges
on metal layers.
 These charges cause a high voltage spike, which
may destroy the gates connected to the metals.
7
Antenna Effect
 A long line connected to gate only can cause
failure
 Not a problem after chip is complete since every
net has at least one driver
M2
M1
Driver (diffusion)
Load (poly)
 But, we can have a problem during manufacturing
 Here is the same net after M1 is built, but not yet
M2
M1
Driver (diffusion)
Load (poly)
8
Antenna Effect
Antenna violation
Diffusion
Sink 1
Sink 2
©[Wu]
9
Antenna Rules
 Violations to the above antenna rules in every
metal layer have to be fixed before the chip
tapeout.
 Each metal layer may have various upper limit
rules based on the process specifications.
 0.18 (0.13) um technology: the maximum length of
an “antenna” wire ≈ 500 um (20 um).
Process-Induced Damage Rules (otherwise known as “Antenna Rules”)General Requirements.
http://www.mosis.org/Technical/Designrules/guidelines.html#antenna
11
Antenna Avoidance
1. Jumper Insertion:
 Router inserts jumpers for long metals from low-level
metals to upper-level layers.
− The jump cuts the long metals in the low-level layers to
disconnected pieces.
− based on the fact that wire segments on top routing layers are
normally fabricated at the end
Antenna violation
Diffusion
Gate
Jumper insertion
Diffusion
Gate
12
Antenna Avoidance
1. Jumper Insertion:
• Disadvantage:
 jumpers introduce extra vias
−  Degrade both manufacturing yield and circuit timing
performance
Jia Wang, Hai Zhou, “Optimal Jumper Insertion for
Antenna Avoidance under Ratio Upper-Bound,” DAC 2006.
13
Antenna Avoidance
3. Layer Assignment:
• Reduce antenna length by layer assignment.
Antenna violation
Diffusion
Gate
Jumper insertion
Diffusion
Gate
Layer assignment
Diffusion
Gate
Di Wu, Jiang Hu and Rabi Mahapatra, “Coupling Aware Timing
Optimization and Antenna Avoidance in Layer Assignment,” ISPD 2005.
15