III
Prof. Muhammad Saeed
Assembly Language Instructions
1/27/2015
Computer Architecture & Assembly Language
2
Language Instructions
† MOV
MOV
MOV
MOV
MOV
MOV
reg, reg
mem, reg
reg, mem
mem, imm
reg, imm
† MOVZX
MOVZX reg32, reg/mem8
MOVZX reg32, reg/mem16
MOVZX reg16, reg/mem8
† MOVSX
MOVSX reg32, reg/mem8
MOVSX reg32, reg/mem16
MOVSX reg16, reg/mem8
1/27/2015
Computer Architecture & Assembly Language
3
Language Instructions
† XCHG
XCHG reg, reg
XCHG reg, mem
XCHG mem, reg
† INC, DEC
INC reg/mem
DEC reg/mem
The Overflow, Sign, Zero, Auxiliary Carry, and Parity
flags are changed according to the value of the
destination operand.
† ADD, SUB
ADD dest, source The Carry, Zero, Sign, Overflow, Auxiliary Carry, and
SUB dest, source Parity flags are changed according to the value that is
placed in the destination operand.
† NEG
NEG reg
NEG mem
1/27/2015
The Carry, Zero, Sign, Overflow, Auxiliary Carry, and
Parity flags are changed according to the value that is
placed in the destination operand.
Computer Architecture & Assembly Language
4
Language Instructions
† PUSH
PUSH reg/mem16
PUSH reg/mem32
PUSH imm32
The PUSH instruction first decrements ESP
and then copies a source operand into the
stack. A 16-bit operand causes ESP to be
decremented by 2. A 32-bit operand causes
ESP to be decremented by 4.
† POP
POP reg/mem16
POP reg/mem32
The POP instruction first copies the contents
of the stack element pointed to by ESP into a
16- or 32-bit destination operand and then
increments ESP. If the operand is 16 bits, ESP
is incremented by 2; if the operand is 32 bits,
ESP is incremented by 4
Language Instructions
† PUSHFD and POPFD
The PUSHFD instruction pushes the 32-bit EFLAGS register on the
stack, and POPFD pops the stack into EFLAGS.
† PUSHAD and POPAD
The PUSHAD instruction pushes all of the 32-bit general-purpose
registers on the stack in the given order: EAX, ECX, EDX, EBX, ESP,
EBP, ESI, and EDI. The POPAD instruction pops the same registers off
the stack in reverse order.
† PUSHA and POPA
PUSHA instruction, pushes the 16-bit general-purpose registers (AX,
CX, DX, BX, SP, BP, SI, DI) on the stack in the order listed. The POPA
instruction pops the same registers in reverse
Language Instructions
† LOOP
The LOOP instruction assumes that the ECX (or CX) register contains
the loop count. When the loop instruction is executed, the CX register is
decremented and the control jumps to the target label, until the CX
register value reaches zero.
† Unconditional Jump
Jmp label1
Language Instructions
† Conditional Jumps
Following are the conditional jump instructions used on signed data
Instruction
Description
Flags tested
JE/JZ
Jump Equal or Jump Zero
ZF
JNE/JNZ
Jump not Equal or Jump Not Zero ZF
JG/JNLE
Jump Greater or Jump Not
Less/Equal
OF, SF, ZF
JGE/JNL
Jump Greater or Jump Not Less
OF, SF
JL/JNGE
Jump Less or Jump Not
Greater/Equal
OF, SF
JLE/JNG
Jump Less/Equal or Jump Not
Greater
OF, SF, ZF
Language Instructions
† Conditional Jumps
Following are the conditional jump instructions used on unsigned data
Instruction
Description
Flags tested
JE/JZ
Jump Equal or Jump Zero
ZF
JNE/JNZ
Jump not Equal or Jump Not Zero
ZF
JA/JNBE
Jump Above or Jump Not Below/Equal
CF, ZF
JAE/JNB
Jump Above/Equal or Jump Not Below
CF
JB/JNAE
Jump Below or Jump Not Above/Equal
CF
JBE/JNA
Jump Below/Equal or Jump Not Above
AF, CF
Language Instructions
† Conditional Jumps
The following conditional jump instructions have special uses and check the
value of flags
Instruction
Description
Flags tested
JXCZ
Jump if CX is Zero
none
JC
Jump If Carry
CF
JNC
Jump If No Carry
CF
JO
Jump If Overflow
OF
JNO
Jump If No Overflow
OF
JP/JPE
Jump Parity or Jump Parity Even
PF
JNP/JPO
Jump No Parity or Jump Parity Odd
PF
JS
Jump Sign (negative value)
SF
JNS
Jump No Sign (positive value)
SF
Language Instructions
† AND
AND
AND
AND
AND
AND
reg,reg
reg,mem
reg,imm
mem,reg
mem,imm
The AND instruction performs a boolean (bitwise)
AND operation between each pair of matching
bits in two operands and places the result in the
destination operand
† OR
OR
OR
OR
OR
OR
reg,reg
reg,mem
reg,imm
mem,reg
mem,imm
The OR instruction performs a boolean OR
operation between each pair of matching bits in
two operands and places the result in the
destination operand
Language Instructions
† XOR
OR
OR
OR
OR
OR
reg,reg
reg,mem
reg,imm
mem,reg
mem,imm
The XOR instruction performs a boolean
exclusive-OR operation between each pair of
matching bits in two operands and stores the
result in the destination operand
† NOT
NOT reg
NOT mem
The NOT instruction toggles (inverts) all bits in an
operand
Language Instructions
† TEST
The TEST instruction performs an implied AND
operation between each pair of matching bits in two
operands and sets the Sign, Zero, and Parity flags
based on the value assigned to the destination
operand. The only difference between TEST and
AND is that TEST does not modify the destination
operand.
The TEST instruction always clears the Overflow and
Carry flags. It modifies the Sign, Zero, and Parity
flags in the same way as the AND instruction.
Language Instructions
† CMP
In x86 assembly language we use the CMP instruction
to compare integers. Character codes are also
integers, so they work with CMP as well. The CMP
(compare) instruction performs an implied subtraction
of a source operand from a destination operand.
Neither operand is modified.
CMP uses the same operand combinations as the
AND instruction.
Language Instructions
† Directive
† Instruction
† Procedure
 myproc PROC
……
ret
myproc endp
† Macro
 myMacro MACRO
……..
endm
(call myproc)
(myMacro)
Language Instructions
† PTR Operator
†
PTR operator overrides the declared
size of an operand to access the
MOV eax, WORD PTR [var] operand using a size attribute that is
from the one assumed by
LENGTHOF Operator different
the assembler.
Var1 WORD 20 DUP(0)
Var2 DWORD 20 DUP(0) The LENGTHOF operator counts the
LENGTHOF var1
number of elements in an array
† SIZEOF Operator
Var1 WORD 20 DUP(0)
Var2 DWORD 20 DUP(0)
SIZEOF var1
The SIZEOF operator counts the
number of bytes in an array
† ($ - array)
Array BYTE “WELCOME”, 0dh, 0ah
Size WORD
( $-Array )
Language Instructions
† LABEL Directive
.DATA
val16
val32
.CODE
mov
mov
LABEL
DWORD
ax,
dx,
The LABEL directive gives a size
attribute without allocating any
storage
WORD
12345678h
val16
[val16+2]
.DATA
LongValue
LABEL DWORD
val1 WORD
5678h
val2 WORD
1234h
.CODE
mov eax, LongValue
Language Instructions
† Indexed Operand
.DATA
array BYTE
.CODE
mov esi,
mov al,
An indexed operand adds a constant
to a register to generate an effective
address
10h, 20h, 30h
0
array[esi]
† Scale Factors in Indexed Operand
.DATA
Array DWORD
100h, 200h, 300h, 400h
.CODE
mov esi, 3 * TYPE array
mov eax, array[esi]
Language Instructions
Program
1st Program
.586
.MODEL flat, stdcall
option casemap :none
Include D:\msaeed\academic\assemblylanguage\masm32\include\windows.inc
Include D:\msaeed\academic\assemblylanguage\masm32\include\kernel32.inc
Include D:\msaeed\academic\assemblylanguage\masm32\include\user32.inc
Includelib D:\msaeed\academic\assemblylanguage\masm32\lib\kernel32.lib
Includelib D:\msaeed\academic\assemblylanguage\masm32\lib\user32.lib
.DATA
WindowTitle
Message
BYTE
BYTE
“Greetings",0
“Hello, World",0
.CODE
main:
invoke MessageBox, NULL, ADDR Message, ADDR WindowTitle, MB_OK
invoke ExitProcess, eax
end main
1/27/2015
Computer Architecture & Assembly Language
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END