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 VLSI
 Very-large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining thousands of transistors
into a single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device. Before the
introduction of VLSI technology most ICs had a limited set of
functions they could perform. An electronic circuit might consist
of a CPU, ROM, RAM and other glue logic. VLSI lets IC makers add
all of these into one chip.
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VLSI TRAINING COURSE CONTENT :
VLSI Design Flow
SoC Architecture Concepts
On-Chip Bus Protocols (AXI4.0, OCP3.0)
Peripheral Bus Protocols(USB3.0/PCIEx Gen3)
Advanced Verilog for Verification
SystemVerilog for Advanced Verification
ASIC Verification Concepts
ASIC Verification Methodologies : OVM & UVM
PERL Automation
PROJECTS : Module(IP) Level Verification Projects
Project#1 : SystemVerilog Based Project based Complex IP (USB, Ethernet,
MemCtrl, Bridge, etc)
Project#2 :SV & OVM/UVM Based Project based on Complex IP (UART, KBD,
Bridge, etc)
System on Chip(SoC) Verification Concepts
Mock Interviews & Group Discussions
Student assignments for weekday practice
 Module 1
 Applied Network Analysis
 Electrical Network Elements - Independent and Dependent
Sources, Passive Elements
 Network Analysis Techniques - Review of Time and Frequency
Domain responses of RC networks
 Module 2
 Devices and Circuits for Microelectronics
 MOSFET Characteristics, MOSFET Capacitances
 CMOS Inverter - Conceptualizing the Inverter using Network
Elements, Inverter VTC, Transient Response
 CMOS Gate Design
 PN Junction, BJT Device Characteristics and Applications
Review OPAMP Applications - Review
 Module 3
 Digital System Design
 Quality Metrics of a Digital System
 Review of Number Systems , Combinational Logic Design
 Interpreting the Logic gate Data Sheets
 Designing with Mux, Demux, Decoders, Encoders
 Sequential Elements and Sequential Logic Design- D Latch, D
Flop Design of Sequential Systems - Registers and Counters
 Module 4
 Basic C Programming
 Introduction to C Programming - Structure of a C program,
The C compilation process
 Types and Operators - C base types, Precedence &
associativity, - Arithmetic operations
 Functions -The Function as a logical program unit,
Parameter passing, Memory segments Control Flow -Logical
expressions and operations, Decision Making, Loops,
Introduction to Pointers
 Module 5
 Review of Micro Processors/ Microcontrollers
 Introduction to a Generic Microprocessor
 Instruction Execution Cycles, Single, Multi Cycle, Pipelined
Data Paths
 Interrupts, Memory Mapping and Peripheral Interfaces
Introduction to Bus Architecture overview - APB, AXI
Module 6
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Advanced Digital System Design
Synchronous Finite State Machine Design
Data-path elements - Arithmetic Structures
Introduction to and Programmable Platforms
Design Capture and Simulation
Practical Digital System Design Examples
Module 7
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Chip Design Methodology - I
Driver for VLSI: Moore's law
Evolution of Design Approaches (leading upto HDLs),
Simulator and Synthesizers Specification formation to Micro
- architecture
 Module 8
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Digital System Design with Verilog
Hardware Modeling Overview,
Verilog language concepts
Modules and Ports
Dataflow Modeling
Introduction to Test benches
Operators
Procedural Statements
Controlled Operation Statements
Coding for Finite State Machines
Coding For Synthesis
Tasks and Functions Advanced Verilog Test benches
Module 8
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Functional Verification
Introduction to Verification
Introduction to Verification Plan
Verification Tools
Stimulus and Response
Introduction to Bus Function Models Verification
environment and its components
Module 9
 Chip Design Methodology - II
 Advanced Simulation and Synthesis
 Introduction to Design Verification RTL design, synthesis,
verification, regression
Module 10
 Verification using System verilog
 System Verilog- Introduction, Basics, Enhancement made on
System Verilog, Interface and Modports System Verylogsfor
Verification, SystemVerilog Event ordering
 Clocking Block and program block, OOPs concept of System
Verilog Parameterized classes, Virtual interface, Constrained
Randomization, Techniques, Functional Coverage System,
 Verilog Assertion
Module 11
 Digital System Design using FPGAs FPGA Architecture -
Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB),
FPGA Architecture
 Optimal FPGA Design - HDL Coding Techniques for FPG,
FPGA Design Techniques Synthesis Techniques,
Implementation, Options - Overview, Achieving Timing
Closure, Path Specific Constraints, Introduction to Advanced
IO Timing
 FPGA Design Flow - Xilinx tool Flow, Reading Reports,
Implementing IP cores, Pin Planning using Plan Ahead,
Global Timing Constraints, Debugging Using Chipscope Pro
 Static Timing Analysis - Introduction Reset Techniques, Clock
Domain Crossing, Multiple Clock Domains, Dual
Synchronization
Module 12
 Chip Design Methodology - III
 Design and Verification Guidelines
 SoC Verification Methodology Physical Design,
Manufacturing, Silicon validation
Module 13
 Course Project Course project
 Advanced VLSI
Basic Electronic Review
 Electrical Network Elements, Review of DC and AC Circuits
 Basic Semiconductor Device and Circuits- PN Junction, BJT
and MOSFET
 Review of OPAMP Applications
 Interpreting device datasheets(PN junction, BJT, MOSFET
and OPAMP)
Module 2
 Digital Design Review
 Number Systems
 Combinational Network Design
 Interpreting the datasheet of a Logic Gate
 Designing with Mux, Demux, Decoders, Encoders
 Sequential Elements - D Latch, D Flop
 Design of Sequential Systems - Registers and Counters
 Introduction to Data Converters
Module 3
 Programming in C
 Introduction to C Programming - Structure of a C program,
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The C compilation process
Types and Operators - C base types, Precedence &
Associativity, - Arithmetic operation, Promotion &
Typecasting
Control Flow - Logical expressions and operations, Decision
Making, Loops
Definitions and declarations, Header files, Scope and
lifetime - Storage Classes
Introduction to pointers - Using pointers to access single dim
arrays
Bit Manipulation, Bit level manipulation,
Sted C IO functions
Functions - The Function as a logical program unit,
Parameter passing by copy and reference
Salient Features of Embedded Systems :
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1.
80% hands on / practical classes.
Real time Scenarios / Project Exposure.
Limited no of students per batch.
Corporate Training Atmosphere
Week end Batches to suit Professional.
Placement Assistance which includes
Resume Preparation
2. Individual Counselling
3. Offline Support, which includes email queries and
assignments.
4. Association with people who are working for more than
20 Companies who may provide interviews .
 Backup Classes.
 Provision to come for one more batch.