This Linux tutorial is based on the SoC_SW_Lab_13.0.pdf and SoC_HW_Lab_13.0.pdf tutorials available
from http://www.arrownac.com/solutions/sockit/ under the getting started tab.
HARDWARE LABORATORY
MODULE 1. Getting Started
Your first objective is to ensure that you have all of the items needed and to install the tools so that you
are ready to create and run your design.
List of Required Items:
-Arrow Electronics SoCKit development board
-Quartus II v13.0sp1 Web Edition
-Computer with Centos 5.9
-Arrow SocKIT_Materials.zip from http://www.arrownac.com/solutions/sockit/ (available under getting
started)
There are a few jumpers that require configuring before proceeding with the labs.
-BOOTSEL[2..0] jumpers. These should be configured as "100" to select boot from SD card 3.3V
- CLKSEL[1..0] jumpers. These should be configured as "00" for the slowest HPS peripheral clock speed
Option
Please ensure that the jumpers are configured as indicated below.
Modify the default MSEL bit settings.
- SW6 is located on the bottom side of the SoCKit.
- Please change MSEL[0:4] to 00001.
- To do so move MSEL[1] to the '0' position.
Verify that the JTAG chain is correctly configured. The JTAG chain switch is located in to the right of the
green audio connector.
- HSMC_EN should be disabled (left position) and the HPS_EN should be enabled (right position).
MODULE 2. Examine the System Design
Refer to module 2 in the SoC_HW_13.0.pdf for information
Module3. Opening Quartus
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This tutorial assume that Quartus 13.0sp1 and EDS has successfully been installed on your computer
in the /home/<USERNAME>/altera/ directory
Extract the hardware lab materials to the /home/<USERNAME>/ directory
Open a terminal. To load Quartus environmental variables run the following script:
/home/<USERNAME>/altera/13.0sp1/embedded/embedded_command_shell.sh
 You may want to add this script to an alias in your .bashrc file.
In the same terminal, type quartus to start quartus.
A splash screen will appear, select Open Existing Project:
 Now browse to the directory:
/home/<USERNAME>/SoCKit_Materials/SoCKit/SoCKit_HW_lab_13.0 and select
soc_system.qpf and then select Open.
If you close the splash screen without opening the project:
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Select File -> Open Project and browse to the directory
/home/<USERNAME>/SoCKit_Materials/SoCKit/SoCKit_HW_lab_13.0 and select soc_system.qpf
The Quartus II project will open. The project already contains a top level Verilog file
(..\top\c5sx_soc.v) and a Qsys project (soc_system.qsys) that will be modified in the following
modules.
MODULE 4. Build the Qsys System
Please refer to Module 4 in the SoC_HW_Lab_13.0.pdf for instructions.
MODULE 5. Complete the Quartus II Project
5.4 Compile: is mandatory in order for lab to work
MODULE 6. Hardware Debug Flow (System Console)
6.1 Downloading and Programming FPGA
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Previously, when the USB Blaster driver was enabled, the SoCKit was plugged in, the programming
dip switch was enabled and the cables were connected, ensure that the SoCKit is still powered on,
and cables are still connected.
 Within Quartus II, select Tools -> Programmer.
 Select Hardware Setup (top left hand side of the Programming Window) and ensure that the
currently selected hardware is CV SoCKit [USB-1]. It should be on by default
o
In order for CV SoCKit [USB-1] to be visible it must be enabled in the virtual machine.
Within Virtualbox click on Devices->USB Ddevices->Altera CV SoCKit
o
It may take several attempts for Altera CV SoCKit to become visible. Ensure the USB
cable is connect to the USB Blaster II port and is attached to your computer. Exit the
Quartus programmer, reopen the programmer and look for the CV SoCKit under
Hardware Setup.
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Close the Hardware Setup window and return to the Programmer window.
Auto Setup
o Select "Auto Detect"
o Select the correct device: "5CSXFC6D6ES" and then OK
o Select, Add File. Select the soc_system.sof that is present in the .\output_files directory. If it
is not present ensure that you have compiled the project as in the previous step.
o The Programming window should now appear as below. If you have trouble with the Auto
setup you may find more luck in the manual setup.
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Manual Setup
o Select, Add File. Select the soc_system.sof that is present in the .\output_files directory. If it
is not present ensure that you have compiled the project as in the previous step.
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Select Add Device. Add the flowing 2 devices: Cyclone V->5CSXFC6D6ES and SoC Series V>SOCVHPS. Click ok.
o The window should then now look as shown above. (If not, then delete the extra
5CSXFCD6ES device):
Press the Start Button as seen below to program the FPGA. After programming the FPGA the
progress indicator should indicate 100% complete (as seen above) There should be no error
messages
Refer to the SoC_HW_13.0.pdf for the subsequent sections in module 6.0
SOFTWARE LABORATORY
MODULE 1. Getting Started
Refer to module 1 in the SoC_SW_13.0.pdf for information
MODULE 2. Examine the System Design
Refer to module 2 in the SoC_SW_13.0.pdf for information
MODULE 3: Generate, Build and Run the Preloader
Refer to module 3 in the SoC_SW_13.0.pdf to for background information on the bootloader.
Section 3.1
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Continue using the hardware lab materials stored in the /home/<USERNAME>/ directory. After
completing the software tutorial you will have generated the necessary sof and qsys files required
for this tutorial. Do not use the files provided by in the SoCKit_SW_lab_13.0 lab directory! These
files need to be recompiled for quartus 13.0sp1.
Open a terminal. To load Quartus environmental variables run the following script:
/home/<USERNAME>/altera/13.0sp1/embedded/embedded_command_shell.sh
 You may want to add this script to an alias in your .bashrc file.
Launch the BSP Editor
 In this same terminal launch the BSP Editor by typing bsp-editor
Create a new BSP
 Select File --> New BSP to create a new BSP
Indicate the location of the Preloader Settings Directory
 Use
/home/<USERNAME>/SoCkit_HW_lab_13.0/hps_isw_handoff/soc_s
ystem_hps_0/ as the preloader directory. This directory contains the xml files that
Quartus / Qsys has generated. They describe the customized peripheral and DDR settings for
the SoC.
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Generate the preloader
 Press OK to create the BSP settings file and directory
Note the default location of the created preloader project directory is \software\spl_bsp
 Press the Generate button to generate the preloader source and makefile
 Press Exit once generation is complete.
3.2 Build the Preloader
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Open a terminal. To load Quartus environmental variables run the following script:
/home/<USERNAME>/altera/13.0sp1/embedded/embedded_command_shell.sh
CD to the preloader project directory within the shell
 The preloader files can be found in
/home/<USERNAME>/SoCkit_HW_lab_13.0/software/spl_bsp
Type make and press enter
A tar file which contains a template of standard source files for the preloader is being copied from
the SoC EDS install directory. The custom source files are in the generated sub-directory.
The preloader will take a few minutes to build. An examination of the preloader project directory
after completion shows the project contents. The preloader ELF file resides in the
\software\spl_bsp\uboot-socfpga\spl directory.
3.3 Launch DS-5 Embedded Development Suite & Import the Preloader project
 Open a terminal. To load Quartus environmental variables run the following script:
/home/<USERNAME>/altera/13.0sp1/embedded/embedded_command_shell.sh
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 You may want to add this script to an alias in your .bashrc file.
Launch the ARM DS-5 tool in this same terminal by typing eclipse into the terminal
Refer to Refer to module 3 in the SoC_SW_13.0.pdf for continued information. File path and name
changes are listed below
3.3.3 ->Under “Import Existing Code”: Be sure to select the spl_bsp under the hardware project at
/home/<USERNAME>/SoCkit_HW_lab_13.0/software/spl_bsp/
3.4 Create a Debug Configuration for the Preloader project
 Refer to Refer to module 3 in the SoC_SW_13.0.pdf for continued information. File path and name
changes are listed below
3.4.3 ->Under “Select the files necessary for Target debug”: Be sure to select the u-boot-spl under
the hardware project at
/home/<USERNAME>/SoCkit_HW_lab_13.0/software/spl_bsp/ubootsocfpga/u-boot-spl/
3.4.3 ->Under “Select the files necessary for Target debug”: Be sure to select the soc_system
subdirectory under the hardware project at
/home/<USERNAME>/SoCkit_HW_lab_13.0/soc_system
4. Configure the Debugger
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Copy the “preloader.ds” inside the SoCkit_SW_lab_13.0 directory to the
SoCkit_HW_lab_13.0 directory.
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Click on the Debugger tab.
Select the "Debug from entry point" pilot button.
Check the "Run target initialization debugger script" box.
Press the File System button and navigate to the "preloader.ds" script from the HW folder
Note: Please verify that you have selected the preloader.ds script in the SoCkit_HW_lab_13.0 folder
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Press the Open button.
Press the Debug button to start the debug session.
Refer to Refer to module 3 in the SoC_SW_13.0.pdf for continued information
MODULE 4. Validating the FPGA Peripherals from the Hard Processor System (HPS)
Refer to module 4 in the SoC_SW_13.0.pdf for information