ASIC Logic
Speaker: Yu-Ju Cho 卓余儒
Advisor: Prof. Andy Wu 吳安宇教授
National Taiwan University
Adopted from National Chiao-Tung University
IP Core Design
SOC Consortium Course Material
Goal of This Lab
Prototyping
Familiarize with ARM Logic Module (LM)
Know how to program LM
HW/SW co-verification using LM and CM
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Outline
Introduction
ARM System Overview
ARM Integrator System Memory Map
Prototyping with Logic Module
Lab – ASIC Logic
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Introduction
Rapid Prototyping – A fast way to verify your
prototype design.
– Enables you to discover problems before tape out.
– Helps to provide a better understanding of the design’s
behavior.
ARM Integrator and Logic Module can be used for
Hardware Design Verification and HW/SW coverification.
– Hardware Design Verification: using LM stand alone.
– HW/SW co-verification: using LM, CM, Integrator together.
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Outline
Introduction
ARM System Overview
– ARM Synchronization Scheme: Interrupt
– ARM Synchronization Scheme: Polling
ARM Integrator System Memory Map
Prototyping with Logic Module
Lab – ASIC Logic
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ARM System Overview
 A typical ARM system consists of an ARM core, a DSP chip
for application-specific needs, some dedicated hardware
accelerator IPs, storages, and some peripherals and controls.
ARM920T
DSP CHIP
Motion
Estimation
Accelerator IP
External
Memory
External
Memory
Controller
AHB
On chip memory
controller and
memory
GPIOs
Direct Memory
Access (DMA)
Interrupt
Controller
AHB-to-APB
Bridge
Remote KB/
Mouse
Controller
APB
Real Time
Counter
Timers
LCD Controller
USB
Controller
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ARM System Synchronization Scheme: Interrupt
 A device asserts an interrupt signal to request the ARM core
handle it.
 The ARM core can perform tasks while the device is in use.
 Needs Interrupt Controller. More hardware.
IP0
IP1
IP2
IP3
Interrupt controller receives the IRQs
and update the IRQ status indicating the
IRQ sources.
Interrupt Controller
ARM CORE
clear IP0's IRQ
IP 0
IP0, IP1, IP2, and IP3 raised interrupt
request (IRQ) at the same time. The
IRQs are sent to the interrupt controller.
ARM core receives the IRQs,
deteremines which IRQ should be
handled according to programmed
priorities. and then executes the
corresponding interrupt service routine
(ISR).
The ISR performs its operations and
clears the IP0's interrupt.
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IRQ registers
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IRQ register Bit assignment
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ARM System Synchronization Scheme: Polling
 The ARM core keeps checking a register indicating if the
device has done its task.
 The ARM core is busy “polling” the device while the device is
in use.
 Less hardware.
ARM core polls IP0's ready register after
IP0 has been enabled.
ARM CORE
Polling IP0
Disable IP0
IP 0
Once IP0 is done with its operation,
ARM core will know from the changed
value of the ready register.
ARM core will execute the
corresponding operations and then
disable IP0.
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Outline
Introduction
ARM System Overview
ARM Integrator System Memory Map
Prototyping with Logic Module
Lab – ASIC Logic
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Overview of System Memory Map
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Core Module Memory Map
Core Module Control Register CM_CTRL
Bits
Name
Access
Function
31:6
Reserved
5
BIGEND
R/W
0=little-endian
1=big-endian
4
Reserved
3
RESET
W
Reset core module
2
REMAP
R/W
1
nMBDET
R
0
LED
R/W
0=access Boot ROM
1=access SSRAM
0=mounted on MB
1=stand alone
0=LED OFF
1=LED ON
4-pole DIP switch (S1) on motherboard
– S1[1]=ON: code starts execution from boot ROM
– S1[1]=OFF: code starts execution from flash
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Core Module Memory Map (cont.)
 The nMBDET signal is permanently grounded by the
motherboard so that it is pulled LOW on the core module
when it is fitted.
 The REMAP bit only has effect if the core module is attached
to a motherboard (nMBDET = 0).
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Core Module Memory Map (cont.)
8MB
8MB
256MB
256KB
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Core Module Alias Address
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Integrator Memory Map for Core Modules
 REMAP = 0: Default following reset.
Accesses to addresses 0x00000000
to 0x0003FFFF
– S1[1] = ON: the access is to boot ROM
– S1[1] = OFF: the access is to flash
 REMAP = 1: Accesses to address
0x00000000 to 0x0003FFFF
 REMAP: ROM is slow & narrow to
RAM, so use this register to change
memory map after initialization
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Integrator Memory Map for Logic Modules
 S1[1] = ON: the EBI resources are
mapped into the bottom 256MB of
the system memory map.
 S1[1] = OFF: the flash is mapped
repeatedly into bottom 256MB of
the system memory map.
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System Memory Map (1/3)
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System Memory Map (2/3)
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System Memory Map (3/3)
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Outline
Introduction
ARM System Overview
ARM Integrator System Memory Map
Prototyping with Logic Module
–
–
–
–
–
–
ARM Integrator AP & ARM LM
FPGA tools
Example 0
Example 1
Example 2
Exercise
Lab – ASIC Logic
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AP Layout
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What is LM
Logic Module
A platform for developing Advanced
Microcontroller Bus Architecture (AMBA),
Advanced System Bus (ASB), Advanced Highperformance Bus (AHB), and Advanced
Peripheral Bus (APB) peripherals for use with ARM
cores.
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Using the LM
It can be used in the following ways:
– As a standalone system
– With an CM, and a AP or SP motherboard
– As a CM with either AP or SP motherboard if a
synthesized ARM core is programmed into the FPGA
– Stacked without a motherboard, if one module in the stack
provides system controller functions of a motherboard
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LM Architecture
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Components of LM
Altera or Xilinx FPGA
Configuration PLD and flash memory for storing
FPGA configurations
1MB ZBT SSRAM
Clock generators and reset sources
A 4-way flash image selection switch and an 8-way
user definable switch
9 user-definable surface-mounted LEDs (8G1R)
User-definable push button
Prototyping grid
System bus connectors to a motherboard or other
modules
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LM Layout
8-way
switch
4-way
switch
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Links
CONFIG link
– Enable configuration mode, which changes the JTAG
signal routing and is used to download new PLD or
FPGA configurations.
JTAG, Trace, and logic analyzer connectors
Other links, switches, and small ICs can be added
to the prototyping grid if required.
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Integrator Memory Map
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FPGA tools
FPGA GUI Synthesis Tool
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A Timing Information Example
We strongly suggest you to perform place-and-route
operation on a better PC, it’s a very time-consuming work!
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Example0
Path = .\lab7\Codes\SW\example0\SSRAM.c
Move data between SSRAM of core module and
ZBT SSRAM of logic module
This program does the following tasks:
1. Backup the data in the SSRAM of core module at
locations 0x00030000 to 0x00038000 range to the ZBT
SSRAM of logic module at locations 0xC2000000 to
0xC2008000
2. Write values to the SSRAM at locations 0x00030000 to
0x00038000
3. Verify the values in the SSRAM at locations 0x00030000
to 0x00038000
4. Restore the backup data back to their original locations
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Example 1
Path = .\lab7\Codes\HW\example1\Verilog
Count up on logic analyzer channel a
Count down on logic analyzer channel b
Reset by pushbutton
LEDs scan from left to right.
Switches [0:1] (brown:red) control the clock
frequency (CTRLCLK1) and affect the LEDs
scanning frequency.
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Example 1 (cont.)
LED[7:0]
CLK1
nPBUTT
SW[1:0]
Example1
1MHz
LAA[15:0]
LAB[15:0]
Logic Analyser
LAACLK
LABCLK
CTRLCLK1[18:0
Set
]CTRLCLK2[18:0] Frequency
PWRDNCLK1, PWRDNCLK2,
0
Disable SSRAM
and FLASH
1
SnCE, FnOE, FnWE
1
1
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On-board Clock Generators
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Clock Signal Summary
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Programming the LM Clock
1MHz:
2MHz:
5MHz:
10MHz:
CTRLCLKx=19'b1100111110000000100
CTRLCLKx=19'b1100011110000000100
CTRLCLKx=19'b1100001110000000111
CTRLCLKx=19'b1100000110000000111
Constraint:
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Example 2
The example code operates as follows:
1. Determines DRAM size on the core module and sets up
the system controller
2. Checks that the logic module is present in the AP
expansion position
3. Reports module information
4. Sets the logic module clock frequencies
5. Tests SSRAM for word, halfword, and byte accesses.
6. Flashes the LEDs
7. Remains in a loop that displays the switch value on the
LEDs
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Two Platform – AHB & ASB
 Two versions of example 2
are provided to support the
following implementations:
– AHB motherboard and
AHB peripherals
– ASB motherboard and
AHB peripherals
 Which AMBA has been
downloaded on board can
be observed by the
alphanumber display
– H: AHB
– S: ASB
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AHB Platform
Core
SDRAM
Other
Modules
AHB
AHBAHBTop
AHBDecoder
AHBZBTRAM
ZBTSRAM
AHB
AHBMuxS2M
MYIP
AHB2APB
AHBAPBSys
APB
APBRegs
APBIntcon
Logical Module
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Example2 Files Description
 Hardware files .\Lab7\Codes\HW\example2\Verilog
–
–
–
–
–
–
–
–
AHBAHBTop.v
AHBDecoder.v
AHBMuxS2M.v
AHBZBTRAM.v
AHB2APB.v
AHBAPBSys.v
APBIntCon.v
APBRegs.v
For FPGA synthesis tool to generate bitstream
 Software program files .\Lab7\Codes\SW\example2\
–
–
–
–
–
sw.mcp
logic.c
logic.h
platform.h
rw_support.s
For codewarrior to generate sw.axf
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Software Description
5 files included in .\Lab7\Codes\SW\example2\
–
–
–
–
–
sw.mcp: project file
logic.c: the main C code
logic.h: constant definitions
platform.h: constant definitions
rw_support.s: assembly functions for SSRAM testing
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Work Flow Summary
Prepare HDL
Design
Synthesis
Prepare Software
Design
Place&Route
FPGA Bitstream
Generation
Downloading the
Bitstream to LM's
FPGA
Make & Build
AXD Image
Generation
Run the AXD image with MultiICE
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Outline
Introduction
ARM System Overview
ARM Integrator System Memory Map
Prototyping with Logic Module
Lab – ASIC Logic
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Lab 7: ASIC Logic
 Goal
 Requirements and Exercises
– HW/SW Co-verification using
Rapid Prototyping
 Principles
– RGB-to-YUV and YUV-to-RGB
conversions, see next slides
 Discussion
– Basics and work flow for
prototyping with ARM Integrator
– Target platform: AMBA AHB subsystem
 Guidance
– Overview of examples used in
the Steps
 Steps
– Understand the files for the
example designs and FPGA tool
– Steps for synthesis with Xilinx
ISE 6.1 or Altera Quartus II 2.2
– In example 1, explain the differences
between the Flash version and the
FPGA one.
– In example 1, explain how to move
data from DRAM to registers in MYIP
and how program access these
registers.
– In example2, draw the interconnect
among the functional units and
explain the relationships of those
interconnect and functional units in
AHB sub-system
– Compare the differences of polling
and interrupt mechanism
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Exercise: RGB and YUV Conversion (1/4)
RGB-to-YUV conversion (hardware) and then YUVto-RGB conversion (software).
RGB2YUV
Y = 0.299R + 0.587G + 0.114B
U = –0.169R – 0.332G + 0.500B
V = 0.500R – 0.419G – 0.0813B
YUV2RGB
R = Y + 1.403V
G = Y – 0.344U – 0.714V
B = Y + 1.770U
Y = ( 306R + 601G + 117B) >> 10
U = (–173R – 339G + 512B) >> 10
V = ( 512R – 429G – 83B ) >> 10
R = Y + 1437V
G = Y – 352U – 731V
B = Y + 1812U
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Exercise: RGB and YUV Conversion (2/4)
Files Description
– Software files .\Lab7\Codes\SW\exercise
• Input.bmp: test bitmap file
• rw_support.s: assembly functions for access data in logic module
• yuv2rgb.c: the main C code
– Perform YUV to RGB conversion
– Read 8 YUV data from and write 8 RGB data to logic module when
IRQ0 is asserted
– Hardware files .\Lab7\Codes\HW\exercise
• AHBAHBTop.v : must be modified to connect the interrupt signal
from MYIP
• AHBDecoder.v, AHBMuxS2M.v, AHBZBTRAM.v, AHB2APB.v,
AHBAPBSys.v, APBIntCon.v, APBRegs.v
• AHBAHBTop.csf and AHBAHBTop.ucf: define the pin assignment
• MYIP.v: RGB to YUV converter
– Perform RGB to YUV conversion
– Assert IRQ0 when 8 RGB data have been converted into 8 YUV data
to inform ARM processor to read the 8 YUV data
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Exercise: RGB and YUV Conversion (3/4)
Memory Allocation in LM
0xCC0000E4

0xCC0000C8
0xCC000068
0xCC000064
0xCC00001C

0xCC000000
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Output buffer
Interrupt
Polling
Input buffer
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Exercise: RGB and YUV Conversion (4/4)
Based on the template system
– Implement the RGB-to-YUV and YUV-to-RGB
conversions with pure software, compare the performance
of the template system with that of pure software
implementation.
– Design a system that performs RGB-to-YUV conversion
with software and YUV-to-RGB conversion with hardware.
The synchronization scheme used in the system is
polling.
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Reference
 http://twins.ee.nctu.edu.tw/courses/ip_core_02/index.html
 LM-XCV2000E.pdf
 DUI0126B_CM7TDMI_UG.pdf
 DUI0098B_AP_UG.pdf
 progcards.pdf
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