EE365
Adv. Digital Circuit Design
Clarkson University
Lecture #14
CPLDs & FPGAs
Topics
• CPLDs
• FPGAs
Lect #14
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PLDs
16V8 (20 Pins)
• can have 16 inputs (max) and/or 8 outputs (marcrocells)
• has 32 inputs to each of the AND gates (product terms)
22V10 (24 pins)
• can have 22 inputs and/or 10 outputs (max)
• has 44 inputs to each of the AND gates
How about a “128V64” for larger applications?
It will be slower and will more wasted silicon space
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Solution? Use CPLDs
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The OR gates
GAL16V8
(review seq_1.ppt)
• Each output is
programmable as
combinational or
registered
• Also has
programmable output
polarity
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And Plane
XOR gates to
make inverting or
non-inverting buffer
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A General CPLD structure
A collection of PLDs on a single chip with
Programmble interconnects
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Who makes the CPLDs?
Manufacturer
Altera
Altmel
Cypress
Lattice
Philips
Vantis
Xilinx
CPLD Products
MAX 5000, 7000 & 9000
ATF & ATV
FLASH370, Ultra37000
ispLSI 1000 to 8000
XPLA
MACH 1 to 5
XC9500
URL
www.altera.com
www.atmel.com
www.cypress.com
www.latticesemi.com
www.philips.com
www.vantis.com
www.xilinx.com
Let’s takes a look at this
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The Xilinx 9500-series CPLD
• The internal PLDs are called Configurable Functional Blocks
(FBs or CFBs)
• Each FB has 36 inputs and 18 Macrocells (effectively a “36V18”)
• Each CLPD is packaged in a plastic-leaded chip carrier (PLCC)
• The number of I/O pins are much less than the total number of
Macrocells in family of devices
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Xinlinx CPLDs
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Architecture of Xilinx 9500-family CPLD
36 Signal pins
18 outputs
Global Clock
Global set/reset
Global 3 state control
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18 Output
enable signals
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Architecture of Xilinx FB
Most CLPDs have fewer AND terms per macrocell
XC9500 has 5 whereas 16V8 has 8 and 22V10 has 8-16
But…each macrocell can use unused ANDs from its
neighboring macrocells using the “product-term-allocators”
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XC9500 Product
term allocator and
macrocell
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ISP
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Lect #14
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XC9500 I/O Block
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Switch matrix
for XC95108
• Could be anything from a limited set of
multiplexers to a full crossbar.
• Multiplexer -- small, fast, but difficult fitting
• Crossbar -- easy fitting but large and slow
1
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XC4000E I/O Block
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FPGAs
• Historically, FPGA architectures and
companies began around the same time as
CPLDs
• FPGAs are closer to “programmable ASICs” - large emphasis on interconnection routing
– Timing is difficult to predict -- multiple hops vs. the
fixed delay of a CPLD’s switch matrix.
– But more “scalable” to large sizes.
• FPGA programmable logic blocks have only a
few inputs and 1 or 2 flip-flops, but there are
a lot more of them compared to the number
of macrocells in a CPLD.
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General FPGA chip
architecture
a.k.a. CLB -“configurable logic
block”
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Xilinx 4000-series FPGAs
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FPGA specsmanship
• Two flip-flops per CLB, plus two per I/O
cell.
• 25 “gates” per CLB if used for logic.
• 32 bits of RAM per CLB if not used for
logic.
• All of this is valid only if your design has
a “perfect fit”.
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Configurable Logic Block (CLB)
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CLB function generators (F, G,
H)
• Use RAM to store a truth table
– F, G: 4 inputs, 16 bits of RAM each
– H: 3 inputs, 8 bits of RAM
– RAM is loaded from an external PROM at system
initialization.
• Broad capability using F, G, and H:
–
–
–
–
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Any 2 funcs of 4 vars, plus a func of 3 vars
Any func of 5 vars
Any func of 4 vars, plus some funcs of 6 vars
Some funcs of 9 vars, including parity and 4-bit
cascadable equality checking
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CLB input and output connections -buried in the sea of interconnect
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Detail
connections
controlled by
RAM bits
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Programmable Switch Matrix
programmable switch element
turning the corner, etc.
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The fitter’s job
•
•
•
•
•
Partition logic functions into CLBs
Arrange the CLBs
Interconnect the CLBs
Minimize the number of CLBs used
Minimize the size and delay of interconnect
used
• Work with constraints
– “Locked” I/O pins
– Critical-path delays
– Setup and hold times of storage elements
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Oh, by the way -- I/O blocks
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Problems common to CPLDs and
FPGAs
• Pin locking
– Small changes, and certainly large ones, can
cause the fitter to pick a different allocation of I/O
blocks and pinout.
– Locking too early may make the resulting circuit
slower or not fit at all.
• Running out of resources
– Design may “blow up” if it doesn’t all fit on a single
device.
– On-chip interconnect resources are much richer
than off-chip; e.g., barrel-shifter example.
– Larger devices are exponentially more expensive.
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Next time
• SRAM
• DRAM
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