EE365 Adv. Digital Circuit Design Clarkson University Lecture #11 State Machines Topics • State Machine Types • State machine Design Lect #11 Rissacher EE365 Clocked synchronous seq. circuits • A.K.A. “state machines” • Use edge-triggered flip-flops • All flip-flops are triggered from the same master clock signal, and therefore all change state together • Feedback sequential circuits – No explicit flip-flops; state stored in feedback loops – Example: edge-triggered D flip-flop itself (4 states) – Sections 7.9, 7.10 (advanced courses) Lect #11 Rissacher EE365 State-machine structure depends on (Mealy) output state and input typically edge-triggered D flip-flops Lect #11 Rissacher EE365 State-machine structure output depends (Moore) on state only typically edge-triggered D flip-flops Lect #11 Rissacher EE365 Remember Mealy state and input Moore state Lect #11 Rissacher EE365 Notation, characteristic equations • Q means “the next value of Q.” • “Excitation” is the input applied to a device that determines the next state. • “Characteristic equation” specifies the next state of a device as a function of its excitation. • S-R latch: Q = S + R´ · Q • Edge-triggered D flip-flop: Q = D Lect #11 Rissacher EE365 State-machine analysis steps • Assumption: Starting point is a logic diagram. 1. Determine next-state function F and output function G. 2a. Construct state table – For each state/input combination, determine the excitation value. – Using the characteristic equation, determine the corresponding next-state values (trivial with D ff’s). 2b. Construct output table – For each state/input combination, determine the output value. (Can be combined with state table.) 3. (Optional) Draw state diagram Lect #11 Rissacher EE365 Example state machine Lect #11 Rissacher EE365 Excitation equations Lect #11 Rissacher EE365 Transition equations • Excitation equations • Characteristic equations (D flip-flop is easy) • Substitute excitation equations into characteristic equations Lect #11 Rissacher EE365 Transition and state tables (transition equations) (output equation) transition table Lect #11 state table state/output table Rissacher EE365 State diagram • Circles for states • Arrows for transitions (note output info) Lect #11 Rissacher EE365 Modified state machine MAXS MAXS = Q0 Q1 • Moore machine (output depends only on current state) Lect #11 Rissacher EE365 Updated state/output table, state diagram Lect #11 Rissacher EE365 Timing diagram for state machine • Not a complete description of machine behavior Lect #11 Rissacher EE365 State-machine design and synthesis The creative part, like writing a program Lect #11 Turning the crank, like a compiler does Rissacher EE365 A Design example (from text) • Design a machine inputs A and B with output Z that is 1 if: – A had the same value at the two previous ticks – B has been 1 since the last time the above was true Lect #11 Rissacher EE365 State Assignment • Can minimize number of states (see text), but hardly anyone bothers anymore. • Need to assign state-variable combinations to states. – Minimum number of variables for n states is log2 n – Using more than minimum number may be advantageous in some situations, e.g., one variable per state (“one-hot”) (see text). – Example -- 4 states, 2 state variables (Q1,Q2): A ==> 00 B ==> 01 C ==> 10 D ==> 11 Lect #11 Up to this point is “art”, the rest is just “turning the crank.” Rissacher EE365 State assignment contd . • There are 6,720 different state assignments of 5 states to 3 variables. – And there are even more using 4 or more variables • Here are a few “obvious” or “interesting” ones: Lect #11 Rissacher EE365 Transition equations; circuit • Transition table specifies each state variable (Q1, Q2) as a combinational logic function of Q1, Q2, X1, X2. – Find a realization of each function by your favorite means -- ad hoc, minimal sum-ofproducts, etc. • Build the circuit. Lect #11 Rissacher EE365 Transition/output table (decomposed assignment) D1 D2 D3 • Simple textual substitution • With D flip-flops, excitation table is identical to transition table (now with D1 D2 D3) Lect #11 Rissacher EE365 Develop excitation equations • Assume unused states have next-state = 000 Lect #11 Rissacher EE365 Option: Minimize with “Don’t Cares” D=1 D2=Q1 • Q3´ • A´ + Q3 • A + Q2 • B D3= A Lect #11 Rissacher EE365 Circuit using minimized equations Lect #11 Rissacher EE365 Unused States ‘0’ versus ‘don’t-care’ • Minimal-Risk versus Minimal-Cost • Don’t-care uses less gates, but can give unpredictable output if the system goes into a state that it was not meant to Lect #11 Rissacher EE365 In Class Practice Problem 1s-counting machine. Design a clocked synchronous state machine with two inputs, X and Y, and one output, Z. The output should be 1 if the number of 1 inputs on X and Y since reset is a multiple of 4, and 0 otherwise. Use D flip-flops. • Write State and Output table • Write Transition/Excitation and Output table • Write K-maps • Find Excitation and Output Equations • Draw AND-OR and D flip-flop circuit Lect #11 Rissacher EE365 In Class Practice Problem State and Output Table I started the table for you. Essentially, in this problem, the output indicates the number of inputs received modulo 4. Here the state represents the current count and the inputs X and Y represent the new ‘1s’ that can be added to the count. Lect #11 Rissacher EE365 In Class Practice Problem State and Output Table Lect #11 Rissacher EE365 In Class Practice Problem Transition/Excitation and Output Table Here’s the layout of the Transition/Excitation and Output Table: Lect #11 Rissacher EE365 In Class Practice Problem Transition/Excitation and Output Table Next: • Write K-maps • Find Excitation and Output Equations • Draw AND-OR and D flip-flop circuit Lect #11 Rissacher EE365 In Class Practice Problem K-maps, Excitation Eqns. and Output Eqns. D1 = Q2•X’•Y + Q1’•X•Y + Q1•X’•Y’ + Q2•X•Y’ D2 = Q1’•X’•Y + Q1’•X•Y’ + Q2•X’•Y’ + Q2’•X•Y Z = Q1’•Q2’ Lect #11 Rissacher EE365 In Class Practice Problem Circuit (outline) X Y Combinational AND-OR D1 (flip flop) D2 (flip flop) Comb. (AND) Z D1 = Q2•X’•Y + Q1’•X•Y + Q1•X’•Y’ + Q2•X•Y’ D2 = Q1’•X’•Y + Q1’•X•Y’ + Q2•X’•Y’ + Q2’•X•Y Z = Q1’•Q2’ Lect #11 Rissacher EE365 Next time • Registers • Counters Lect #11 Rissacher EE365