Accelerator Laboratory
RF-Systems for STF
S. Fukuda
Content
Introduction
Status of STF and Plan
forFY2006
LLRF
Summary
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Accelerator Laboratory
Cryogenics
CM(35MV/m)
5MW
For 5MW
10MW
For 10MW
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Accelerator Laboratory
•
•
•
Plan to Phase-1 (for 2 years)
For #1-Modulator:
Reinforce the modulator with bouncer circuit using the PNC modulators and
1:6 pulse-transformer making use of JHP pulse-transformer. Old IGBT is
reused. PLC Control system is newly equipped. Almost done
For #2 modulator:
New modulator which is capable to drive 10 MW MBK klystron is designed and
manufactured. This is based on the TESLA Design. New device IEGT is promising.
Waiting the tender
Two 5-MW Klystrons will be prepared.
– Thomson TH2104A (1.296GHz in KEK used in JHP) is tested at 1.3GHz.
Under testing
– Procurement of Thales TH2104C is under going as the replaceable klystron.
Purchased
– If competitive budget or equivalent is approved, a multi-beam klystron will be
introduced.
Planning in FY2006
•
•
Two kinds of power distribution is tested to compare the performance and cost.
under progressing
LLRF system is prepared for the beam acceleration test.
under progressing
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Accelerator Laboratory, KEK
Klystron
Specification of STF-RF
Two 5-MW klystrons (one for RF gun),
1.3 GHz,
125kV, 1.5ms(RF pulse width),5 Hz Repetition
Modulator-1
Reinforcement of PNC modulator
IGBT SW, Pulse width of 1.7ms(voltage)
1:6 Pulse Trans. With Bouncer, flat top 1%
Modulator-2
New modulator / IGBT SW, Pulse width of 1.7ms
1:15 Pulse Trans. With Bouncer, flat top 1%
Power Distribution
System (PDS)
5MW power is fed into 8 cavities.
3dB tournament PDS
LLRF
Digital feedback system using 10 x 16bit ADCs.
IF=10MHz, Lo=1310MHz, Sampling 40 MHz.
Amplitude stability ±0.1％
Phase stability ±0.1deg.
S. FUKUDA LCPAC 060325
Linear PDS /
4
Accelerator Laboratory
Concept of test facility for quick and
inexpensive start utilizing existing properties
Making use of power supply and
waveguide component moved
from PNC (Power Reactor and Nuclear
Fuel Corp).
Power supply has 3 modes;
(1)Short pulse (100ms), (2)long
pulse (4ms) and (3)CW for the
modulating anode type klystron.
For mode(2), possible
klystron is modulating
anode type TH2115
(Thales). About 2MW
output is possible for this
case.
Reform to (PT+Bouncer)
allows to use TH2104A(C).
５－１０MW
S. FUKUDA LCPAC 060325
Photo of Modulator in PNC
Block diagram of PNC modulator
5
Modulator Development
Accelerator Laboratory
Chock
IGBT
AC6.6kV
Klystron
TH2104
Shunt Snubber
23kV
140kV
Pulse
Transformer
VCB
Rectifier
Heater
Transformer
215 F
135 F
50 F
1: 6
Crowbar Storage
Ignitron Capacitor
Install of Pulse transformer
Bouncer
Waveform of modulator without
bouncer
•Modulator reformation was almost done and started operation for coupler test.
•Reformation was performed as half the price as the newly built modulator.
•Bouncer circuit will be added in middle of April in 2006.
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Accelerator Laboratory
Candidate Klystrons
10 MW Peak
(1.3GHz、Long Pulse)
10 MW Peak
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5-10 MW
7
Klystron test status (1)
Accelerator Laboratory
Performance of the klystron, which was bought 15 years ago, was checked in
short pulse operation(3micro sec pulse width)
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P f　ｏｕｔ
(M W )
5
1300M H z
1296M H z
4
3
2
1
0
60
70
80
90
100
110
120
130
）
Applied印加電圧（
voltageｋＶ
(kV)
6
5
P out(M W )
4
3
1300M H z
1296M H z
2
1
0
0
Waveform: voltage (top),
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Current (bottom)
100
200
300
400
500
Pin(W )
8
Klystron Test-Photo of test station and long pulse test
Accelerator Laboratory
Klystron
High Power Circulator
Pulse Transformer Tank
RF Window
IGBT Sw Cabinet
Variable Shorted WG
High power Water Load
Coupler Insertion Points
RF waveform
measured in 060301
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Modulator and klystron plan
in FY2006
Accelerator Laboratory
 Modulator
New modulator (#2) based on the ILC-BCD type will be manufactured.
Preparation of the tender is under going. Full completion depends on
budget.
 Klystron



Second TH2104C (5MW tube) will be conditioned for the waveguide
components’ evaluation or RF gun test.
Collaboration of the 10MW-MBK, especially of the horizontally mounted MBK ,
with Toshiba Corp. is considered. It is also depends on the budget.
Design work of the 10 MW-MBK with the 36 beam-lets which is operated in 50
kV are planed. Collaboration between KEK and Russian engineers is under
going.
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Coupler test configuration
Accelerator Laboratory
Modulator
for 5MW
Kly
Modulator
for 5MW
Kly
Arc Sensor
5MW
DC
DC
Circulator
Usual test
terminated by a
high power load
Arc Sensor
5MW
Circulator
DC
DC
Coupler
Coupler
Durability test under the
large reflection power.
High-power circulator is
required to protect the
klystron
Variable Short
High Power
Dummy
Coupler
developed by
Kako etc.
Waveguide Layout and coupler test
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Accelerator Laboratory
Phase-1 Cavity Test WG Configuration
Arc Sensor
Modulator
for 5MW
Kly
5MW
Monitor DC
Another type of PDS, which is
possible to change the phase and
Qext of the cavities independently,
should be also studied.
Penetration(10m)
At first, 8 circulators will be used to have an initial test.
3-dB Hybrid-PDS
3dB
Power Distribution
DC
Monitor DC
3 Stub Tuner
Φ
Φ
Φ
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Accelerator Laboratory
LLRF system @STF Phase1
Power meter
Fast Interlock
Arc sensor
Klystron linerlizer
J-PARC based LLRF system
Digital FB system using a FPGA board
LLRF PLC system control digital FB system
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Digital FB
cPCI system
will be installed
in Aug.2006
400 W Amp.
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Digital LLRF FB control @STF Phase1
Accelerator Laboratory
STF phase-1
JPARC linac
LLRF
4x14bit ADCs
324 MHz
Max. 2 cav.
IF=12 MHz
LO=312 MHz
Sampling=48 MHz
STF phase-2
10x16bit ADCs
1300 MHz
Max. 8 cav.
(rocketIO)
IF=10 MHz
LO=1310 MHz
Sampling=40 MHz
1300 MHz
Max. 36 cav.
IF=10 MHz
LO=1310 MHz
Sampling=40 MHz
Digital
cavity simulator
Amplitude:6000, phase:0deg.
J-PARC
STF Phase-1
Cavity
Normal
Super
Frequency
324 MHｚ
1300 MHｚ
Q-value
2e4
2e6
Rise time
100 us
500 us
Pulse width
650 us
1.5ms
Phase
difference
～30deg.
～60deg.
Pulse voltage
Lorentz detuning
others
Achieved stability of
~+-0.1%, ~+-0.05deg. @J-PARC
Microphonics
Amp. Stability
±1％
±0.1％
Phase stability
±1deg.
±0.1deg.
FB loop
＜1us
＜3us
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FPGA & DSP boards @STF Phase1
Custom FPGA board
Mezzanine card of the commercial DSP board
10 16bit-ADCs and 2DACs + 2Rocket IO
40 MHz clock
Accelerator Laboratory:
Commercial DSP board (Barcelona)
(same to J-PARC system)
:4x TI C6701 DSPs
Can access to FPGA like an external memory of DSP
Real time intelligent diagnostics by DSP board
Output max
Quench etc.
RF off
(by diagnostics in DSP)
10 16bit-ADCs
FPGA
2DACs
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Accelerator Laboratory
Software development plan for STFPhase1
Cavity Simulator: by commercial FPGA board
(Finished)
FB program development
（~2006.Dec）
FB algorism
(software development)
FB operation
（2006 Dec.）
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Real Cavities
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Proposal of IF mixture
Now, the number of ADCs in a FPGA board is limited
due to the substrate. (maybe ~15 with 16 layers in
substrate)
The idea is based on the ‘digital radio’ and obtaining
cavity signals with a ADC.
Accelerator Laboratory
Triger(48 MHz)
IF1(8 MHz)
IF2(12 MHz)
Mixed signal
(IF1+IF2)
averaging
(IF2 1)
-> IF1 signal
Over-sampling: IF 8 MHz & 12 MHz with 48 MHz sampling
-> include averaging effect ->increase resolution
averaging
(IF1 1)
-> IF2 signal
Mixture of two signals decrease the
resolution of analog signals but averaging
increases the resolution.
Cavity signals do not change during
averaging (due to high Q values)
→ Enough IF separation
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LLRF schedule
Accelerator Laboratory
(analog llrf and MPS)
• Analog llrf (amplifier, etc.): finished
• MPS: almost finished (except modification for 8 cavities)
• PLC program improvement (MPS, for 8 cavities): ~ Aug.,2006
(digital FB system)
• FPGA/DSP/Host program development: ~June 2006
• Brash-up of feedback algorithm by cavity simulator: July,2006-Aug.,2006
• Installation of digital FB system to STF: Aug.,2006
• Test operation at STF with cavity simulator: ~Dec. 2006
• Host/Data acquisition software development: ~Dec. 2006
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Accelerator Laboratory
Summary
 In FY2005, RF system for STF has been developed as planed in the
beginning.
 Reformation of the PNC modulator has almost done and performed the
klystron test. Bouncer circuit will be installed in middle of April.
 First coupler test will be scheduled in April.
 Klystron bought 15 years ago was evaluated and operated normally.
 Plan of the FY2006 for modulator and klystron are shown. New modulator is
now under the preparation of tender. Development of MBK is also seriously
considered.
 LLRF is under manufactured based on the technology developed in J-PARC.
 Analogue system of LLRF has installed and already operated.
 Digital LLRF system are developed. Digital FB hardware for STF Phase-1
was completed and installed.
 Cavity simulator and software development are scheduled in this spring to
autumn.
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