REGISTER MANAGMENT
TOOL
Final presentation – Part B
Preformed by: Liat Honig
Nitzan Carmel
Supervisor: Moshe Porian
Date: 17/05/13
Duration: Two Semesters
MANY TEAMS NEED TO CREATE THEIR OWN REGISTER
BLOCKS FOR FPGA SYSTEMS.
LEADING TO
BUGS
Double Effort
THE SOLUTION
A
REGISTER MANAGEMENT TOOL
Automatically generates registers according to
a required specification using a smart interface!
AUTOREG – A SMART REGISTER MANAGEMENT
TOOL
INSERT YOUR
PROJECT’S
SPECIFICATIONS
TO THE GUI
AUTOMATICALLY
CREATE VHD AND
HSID FOR
REGISTER BLOCKS!
THE SOLUTION
–
A REGISTER MANAGEMENT
Project
Goals
TOOL
 Automatically
registers according
to the
o Determinegenerates
and characterize
a local bus
forrequired
specification.
communication with all the register slave blocks.
 Enables REUSE
o Generic Implementation that allows reuse in
multiple projects.
 Saves money and resources
o Encapsulation of implementation, which will be
hidden from the user.
 Creates unity in the registers VHD files
THE SOLUTION
–
A REGISTER MANAGEMENT
Project
Goals
TOOL
o Determine and characterize a local bus for
 Creates
documentation
the register
components
communication
with for
all the
slavecreated
blocks.
Leads to an organized – HSID
o Generic Implementation that allows reuse in
multiple
projects.
 Alarms
in case
of incorrect input
o Encapsulation of implementation, which will be
hiddenthe
from
the user.
 Manages
registers
through the entire project
Project Goals
o Determine and characterize a local bus for
communication with all the register slave blocks.
o Generic Implementation that allows reuse in
multiple projects.
o Encapsulation of implementation, which will be
hidden from the user.
PROJECT SPECIFICATIONS
1. Writing a GUI interface through which the user will determine a
variety of attributes.
2. Interactivity - The tool will provide feedback for user errors and
will provide a summary output.
3. VHDL:
VHD files
Local Bus
Master
Simulation
Environment
4. No special license will be needed to operate the tool, an EXE
file will be given to the user.
5. HSID will be generated under IEEE standards (IP-XACT)
PROJECT STEPS

1. Determine the implementation platform of the user
interface and data processing: Excel/MATLAB/C++/C#/JAVA .

2. Full characterization of the tool capabilities.

3. Learning the working environment (Wishbone protocol,
advanced VHDL coding , MODELSIM simulation environment).

4. VHDL generic design and simulation.
 5. Implementing the GUI (Graphic User Interface)
 6. Implementing Automatic VHDL generation.
 7. Final MODELSIM and MATLAB Simulations.
VHDL IMPLEMENTATION
GENERAL DESCRIPTION
Project Goals
Local Bus
Register
access
o Determine and characterize a local bus for
communication with all the register slave blocks.
Register
Register
Block
Block
Chip
o Generic
data I/O
Register
Block
Implementation that allows reuse in
multiple projects.
o Encapsulation of implementation, which will be
hidden from the user.
VHDL TOP ARCHITECTURE
reset
clk
ProjectBlock
Goals
A
Reg_status_1
Wishbone Master
Function_1
o Determine and characterize a local bus
for
communication with all the register slave blocks.
o Generic ImplementationReg_enable_2
that allows reuse in
Function_2
Block_A_reg_top
multiple projects.
o Encapsulation of implementation, which will be
hidden from the user.
func_err_3
Function_3
REG BLOCK ARCHITECTURE
Block_A_reg_top
Inputs from block
o Determine and characterize a local bus for
Reg1
communication with all the register slave
blocks.
Outputs
to block
Reg2
Reg3
Priority
Encoder
WB
Master
o Generic Implementation that allows reuse in
WB
multiple
Slaveprojects.
4
o Encapsulation of implementation, which
will be
reg_chosen
hidden from the user.
Reg4
Data from chosen
register
Functional
Block
GENERIC IMPLEMENTATION
GENERIC IMPLEMENTATION
VHDL SIMULATION
SIMULATION ENVIRONMENT
Macro
Scripts
SIMULATION ENVIRONMENT
Macro
Scripts
• Compilation
• Simulation
• Waveforms
Test Bench
SIMULATION ENVIRONMENT
Results
Output File
Simulation
input
Macro
Scripts
• Compilation
• Simulation
• Waveforms
Simulation
outputs
Test Bench
• Procedure called
serially many
times
• Comparison to
expected values
• Reporting
results to output
file
Waveforms
TEST PLAN - OVERVIEW

Testing small modules separately

gen_reg.vhd:
Read
 Write
 Read/Write
 Clear On Read
 Const.


wbs_reg.vhd
Read transactions (single/burst)
 Write transactions (single/burst)



encoder_generic.vhd
Then, testing the entire design

Gen_block.vhd
TEST PLAN – CASES

Testing Regular Activity
Various generic values for address width
 Various values for data
 Read/Write single/burst wishbone cycles for suitable
registers

Testing system boundaries
 Testing system generics

SYNTHESIS
SYNTHESIS RESULTS
A synthesis demonstration was ran, using
Quartus II 12.0sp2, using the following test case:
32 registers, with 8-bit data width, with device
EP4CGX50DF27C6
 Compilation and Synthesis finished successfully.
 Summaries:

Maximum Frequencies:
• Slow 1.2V 85C model –
1199MHz
• Slow 1.2V 0C model –
1328MHz
NETLISTS
GRAPHICAL USER INTERFACE
REQUIREMENTS FROM GUI

Easy to use user experience

Feedback is provided in real time

Data is filled automatically if possible

Easy project view and management

Data and Address can be represented in both
Hexadecimal and Decimal formats
OPENING SCREEN – PROJECT SETTINGS
Settings made for
the entire project
Choose a protocol
Specify address width
Choose address radix
Specify data width
Choose data radix
Specify number of blocks
Specify a directory to
save the generated files
Browser for finding the
requested directory
OPENING SCREEN – PROJECT SETTINGS
Settings made for
the entire project
Choose a protocol
Specify address width
Choose address radix
Specify data width
Choose data radix
Specify number of blocks
Specify a directory to
save the generated files
Continue to next screen
2ND SCREEN – EDIT BLOCK SETTINGS
Opens text editor
Settings made for
the specific block
Specify a name
Provide a description
(optional)
2ND SCREEN – EDIT BLOCK SETTINGS
Settings made for
the specific block
Specify a name
Provide a description
(optional)
Specify an initial
address
Specify number of
registers
choose reset polarity
Navigation
tree view
back to
project
settings
delete
current
block
Continue to next
screen
3RD SCREEN – EDIT REGISTER SETTINGS
Settings made for
a specific register
Specify a name
Provide a description
Choose register type
Specify the offset
address
Specify the initial
data value
Navigation
tree view
Back to block
settings
delete
current
register
3RD SCREEN – EDIT REGISTER SETTINGS
Settings made for
a specific register
Specify a name
Provide a description
Choose register type
Specify the offset
address
Specify the initial
data value
TOP MENUS
 File menu
Create a new project
Open an existing project
Save project as
Save current project
Close current project
Exit AutoReg
 Help menu
About AutoReg
Open user guide
 Generate menu
Report for errors
Generate VHDL files
TREE VIEW
 “Top View” of the entire project
 Automatically sorted by the
absolute address
 Allows easy navigation between
all the screens and components
 Addresses and names are filled
automatically
 Navigation is blocked when
errors or missing data is found in
the current window
ERRORS DISPLAY
AutoReg notifies the user and prevents access to some contents in
the project whenever:
Data isn’t
legal/valid/
complete


Addresses/bits
are
overlapping
Easy to use user experience
Feedback is provided in real time
Before
Deleting an
object
OUTPUTS
ERROR REPORT
HSID
XML – ACCORDING TO IP-XACT STANDARD
VHD FILES

VHD files and reports are created in two subfolders:
DEMO
SUGGESTIONS FOR A LATER PROJECT
1. An option to create a wide register (more than one
address).
2. Support other protocols (not wishbone only)
3. Support more register types
4. Add a possibility to mix between the bits of the same
register when it comes to access manners.
5. Support boards and not just on FPGA
6. Search and filter possibilities
7. Copy-Paste possibilities
SUGGESTIONS FOR A LATER PROJECT
8. Creating a database with options to import and export
9. An option to duplicate , add or delete a register using a
right-click option from the tree view.
10. Unifying the edit_block figure and the edit_reg figure to
prevent window from “jumping”
11. Under the help menu, add a keyboard map for all
keyboard shortcuts of the GUI.
Link:
AutoReg Gui - other features.docx
THE END