by
Dr. Junaid Ahmed Zubairi
Dept of Computer Science
SUNY at Fredonia, Fredonia NY
1

 Introduction to the workshop and setting targets
 Combinational and sequential logic
 Quartus-II package features and usage guide
 Hands on VHDL (Lab1)
 VHDL design units
 Designing a simple circuit and its testing (Lab2)
 Design of a sequential logic circuit (lab3)
 Design project
2

 This workshop is about using VHDL for
VLSI design
 Participants are expected to learn a subset of VHDL features using Altera
Quartus-II platform
3

 VHDL is VHSIC (Very High Speed Integrated
Circuits) Hardware Description Language
 VHDL is designed to describe the behavior of the digital systems
 It is a design entry language
 VHDL is concurrent
 Using VHDL test benches, we can verify our design
 VHDL integrates nicely with low level design tools
4

 It is IEEE standard (1076 and 1164)
 VHDL includes VITAL (IEEE 1076.4), using which the timing information can be annotated to a simulation model
 VHDL has hierarchical design units
 Learning VHDL and Verilog is easy; mastering is difficult
 VHDL and Verilog are identical in functionality
5

 VLSI design starts with (not always!!) capturing an idea on the back of an envelope
 From the specifications, one needs to construct a behavioral description of the circuit
 When one describes how information flows between registers in a design, it is called RTL
(register transfer level)
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 A structure level description defines the circuit in terms of a collection of components
 VHDL supports behavioral, RTL and structural descriptions, thus supporting various levels of abstraction
 Most VHDL users prefer RTL descriptions and use VHDL as input to the synthesis process
 Synthesis tools then optimize and compile the design as per specified constraints and map to target devices as per libraries
7

 Gate level simulation is conducted to verify the design; using the same test vectors that were generated for RTL simulation
 Finally the place and route tools are used for layout generation and timing closure
8

Design Specification
Design Entry/RTL Coding
- Behavioral or Structural Description of Design
RTL Simulation
- Functional Simulation (Modelsim
®
, Quartus II)
- Verify Logic Model & Data Flow
(No Timing Delays)
M512
LE
M4K
I/O
Synthesis
- Translate Design into Device Specific Primitives
- Optimization to Meet Required Area & Performance Constraints
- Precision, Synplify, Quartus II
Place & Route
- Map Primitives to Specific Locations inside
Target Technology with Reference to Area &
Performance Constraints
- Specify Routing Resources to Be Used
9

t clk
Timing Analysis
- Verify Performance Specifications Were Met
- Static Timing Analysis
Gate Level Simulation
- Timing Simulation
- Verify Design Will Work in Target Technology
PC Board Simulation & Test
- Simulate Board Design
- Program & Test Device on Board
- Use SignalTap II for Debugging
10

 We will be using Quartus-II software by
Altera
 This package allows us to write and compile
VHDL designs and perform RTL simulation with waveforms
 Please download Quartus-II from www.altera.com
if not installed already
 Install the license by requesting 30-days grace period. After the expiry of the 30-days period, You can redirect the license to the redwood.cs.fredonia.edu server. We have three floating licenses set up for full version.
11

 Fully-Integrated Design Tool
 Multiple Design Entry Methods
 Logic Synthesis
 Place & Route
 Simulation
 Timing & Power Analysis
 Device Programming

 MegaWizard
®
& SOPC Builder Design Tools
 LogicLock
™
Optimization Tool
 NativeLink ® 3 rd -Party EDA Tool Integration
 Integrated Embedded Software Development
 SignalTap
®
II & SignalProbe
™
Debug Tools
 Windows, Solaris, HPUX, & Linux Support
 Node-Locked & Network Licensing Options
 Revision Control Interface
13

14

Dynamic menus
Floorplans
Execution Controls
Window & new file buttons
Compiler Report
To Reset Views: Tools

Toolbars>Reset All;
Restart Quartus II
15

 Launch the Quartus-II software and identify the main menu item that leads to the following choices:
 New Project Wizard
 Compilation icon and menu item
 Generate Functional Simulation Netlist
 Start Simulation item and icon
 License Setup
 Open recent files and projects
 Launch a new file
16

 Lab-1 is a short and simple project designed to get you started in shortest possible time
 Lab-1 handout will be distributed separately
 Lab-1 calls for designing a half-adder in
VHDL and simulating it in Quartus-II
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 You may use UPPERCASE for reserved words in VHDL and lowercase words for your chosen names but it is not necessary
 The basic building blocks of VHDL design are
ENTITY declaration and ARCHITECTURE body
 The VHDL file name must be the same as the
ENTITY name
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 ENTITY declaration treats the design as a black box. It just names the inputs and outputs as ports
 It does not specify how the circuit works
 The last entry in the port declaration is not followed by a semicolon
 Each signal has a signal mode (IN, OUT or
BUFFER) and a signal type (BIT,
BIT_VECTOR, STD_LOGIC,
STD_LOGIC_VECTOR)
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 Std_logic and std_logic_vector are part of IEEE library. They allow additional values ‘-’(don’t care), ‘Z’ (hi-Z) and ‘X’
(indeterminate)
 In order to use IEEE values, you should use the following statements:
 library ieee;
 use ieee.std_logic_1164.all;
20

 The functional relation between the input and output signals is described by the architecture body
 Only one architecture body should be bound to an entity, although many architecture bodies can be defined
 Architecture body can be written in many different ways
21

 We have used the concurrent assignment statements in Lab-1 code:
 sum<=A xor B;
 carry<= A and B;
 The concurrent assignment takes place based on the activity on RHS of the arrow
22

 We can also describe the architecture based on a list of components used and mapping of our circuit’s signals to the inputs and outputs of the components
 Usually it is done to build a circuit that uses several independent design units
23

 Begin with the design of bottom units in VHDL
 Save each unit in a separate VHDL file declaring it as a new project in Quartus-II
 Design the top unit next as a new project, placing bottom units in the VHDL file as components
 Name the project as the top unit , include the bottom unit files in the project and then compile
 Next lab places half adders as components in a full adder
24

 Lab-2 uses two half adders to build a full adder as shown in the next slide
 It is important to define the internal connectors as “signal” variables in VHDL code
 Signals will connect the two half adders as shown.
 All signals must be named and defined in the architecture body
25

26


 library ieee; use ieee.std_logic_1164.all;







 entity adderfour is port (Cin:in std_logic; x:in std_logic_vector(3 downto 0); y:in std_logic_vector(3 downto 0); s:out std_logic_vector(3 downto 0);
Cout:out std_logic); end adderfour;
27












 architecture compo of adderfour is signal c1,c2,c3:std_logic; component full_adder port (X,Y,Cin:in std_logic; sum,Cout:out std_logic); end component; begin stage0:full_adder port map (Cin,x(0),y(0),s(0),c1); stage1:full_adder port map (c1, x(1),y(1),s(1),c2); stage2:full_adder port map (c2,x(2),y(2),s(2),c3); stage3:full_adder port map (c3,x(3),y(3),s(3),Cout); end compo;
28

 The source code shown builds a four-bit ripple carry adder
 It uses four 1-bit full adders as components
 The structural style is just like specifying a network with all its inputs, outputs and intermediate wires
 All intermediate wires are declared in the architecture body as signals
29

 Instead of naming each wire separately, we group them together and give them a common name
 For example, in a 4-bit adder, we use four inputs x3,x2,x1,x0
 We can also declare a vector called X.
 X :in std_logic_vector(3 downto 0);
 X(3), X(2), X(1), X(0) can be referred individually
30

 Using VHDL, design a simple 4-bit 2function combo box that accepts two four bit numbers (A,B) and produces the complement of ‘A’ if a control input C is
‘0’ otherwise it sets the output to the result of logical AND (A AND B). Test your circuit with one set of different inputs and one set of identical inputs.
For example {1011} and {1001, 0110}
31

 Synchronous Sequential circuits require the use of a clock signal. Clock signal can be generated easily in VHDL
 As an example, look at the following code segment:
 Clk <= not(Clk) after 10ns;
 The Clk wire is assigned its opposite value after 10ns.
 In Quartus, you generate clock waveform by editing the .vwf file. Select clk input and use
“Overwrite Clock” option
32

 Design of an edge triggered D flip flop
 (Demo)
 Adding asynchronous reset to the flip flop
 (Demo)
 How do you convert it to latch?
33

 library ieee;
 use ieee.std_logic_1164.all;
 entity my_ff is
 port (D,clk,reset:in std_logic; Q:out std_logic);
 end my_ff;
34

 architecture synch of my_ff is
 begin
 process (clk,reset)
 begin
 if reset='1' then
 Q <='0';
 elsif clk='1' and clk'EVENT then
 Q<=D;
 end if;
 end process;
 end synch;
35

 The source code shown implements a D flip flop that is rising edge triggered and uses asynchronous reset
 The rising edge is detected by the following statement:
 elsif clk='1' and clk'EVENT then Q<=D;
 This statement says that if clk has a current value of 1 and if there has been an event on the clk line, assign Q the value of D
 Asynchronous reset is achieved by first checking if reset has a value 1
36

 In the D flip flop design, we have introduced the 3 rd type of architecture body, i.e. sequential flow
 Sequential execution is implemented in VHDL with process() statement.
 A process consists of a sensitivity list and a series of statements to be executed in the order in which they are written
 The process is called as soon as the value of any one member of the sensitivity list is changed
37

 Build 8-bit parallel load register by using eight D flip flops as components
 Demonstrate its working by simulation
38