Microcomputer Systems 1
ADSP-BF533 Ez-Kit Lite Audio
Interface
Lab #3 Audio Interface
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2
ADSP-BF533 Ez-Kit Lite Audio
Interface
SPI
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SPORT0
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BF533 EZ-Kit Lite – Audio
Interface

EZ-Kit Lite contains AD1836 Audio Codec

The AD1836 audio codec provides


three channels of stereo audio output and
two channels of multi-channel/stereo 96 kHz input.

The SPORT0 interface of the processor links with the stereo audio
data input and output pins of the AD1836 codec.

The processor is capable of transferring data to the audio codec in


time-division multiplexed (TDM) or
two-wire interface (TWI) mode.

The TDM mode can operate at a maximum of 48 kHz sample rate but
allows simultaneous use of all input and output channels.

The TWI mode allows the codec to operate at a 96 kHz sample rate
but limits the output channels to two.

When using TWI mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and
RFS0 pins of the processor, must be tied together external to the processor. This
is accomplished with the SW9 DIP switch (see “Push Button Enable Switch (SW9)”
on page 2-12 for more information).
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Blackfin Audio Interface Usage
 Two-Wire Interface (TWI) and Serial Peripheral
Interface (SPI)
 Forward channel used to configure and control audio
converters
 Reverse channel relays feedback info from converters
 SPORT’s Used as data channel for audio data
 SPORT TX connects to audio DAC
 SPORT RX connects to audio ADC
 Full-duplex SPORT RX/TX connects to audio codec
 In some codecs (e.g., AC97), SPORT also can serve as
the codec control channel
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BF533 Interface with AD1871
Data Transfer
& Synch
Configuration
& Control
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SW9 Switch Configuration
 Make sure that SW9 switches 5 and 6 are ON &
SW12 is ON. See explanation bellow:
1
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2
3
4
5
6
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7
Switch Default Configuration
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Push-buttons and LED’s
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Push Button Enable Switch
(SW9 & SW12)
 SW9
 Positions 1 through 4:
 Disconnects the drivers associated with the push
buttons from the PF pins of the processor.
 Positions 5 and 6:
 Used to connect the transmit and receive frame syncs
and clocks of SPORT0.
 This is important when the AD1836 audio/video decoder
and the processor are communicating in I2S mode.
 SW12
 When is set to OFF, SW12 disconnects SPORT0 from
the audio codec. The default is the ON position.
 Table 2-6 in the next slide shows which PF is
driven when the switch is in the default (ON)
position.
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Push Button Enable Switch
(SW9)
Table 2-6 shows which PF is driven when the switch is in the default (ON) position
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SPORT0 interface to AD1836 audio
codec
 The SPORT0 connects to the AD1836 audio
codec and the expansion interface.
 The AD1836 codec uses both the primary and
secondary data transmit and receive pins to
input and output data from the audio inputs and
outputs.
 The SPORT1 connects to the SPORT connector
(P3) and the expansion interface.
 The pinout of the SPORT connector and the
expansion interface connectors can be found in
“ADSP-BF533 EZ-KIT Lite Schematic” on page B1.
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The pin layout of the SPORT connector &
expansion interface connectors
SW12
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Audio Interface Configuration
 The AD1836 audio codec’s internal
configuration registers are configured
using the Serial Port Interface - SPI port
of the processor (see Slide #6).
 The processor’s PF4 - programmable flag pin
is used as the select for this device.
 For information on how to configure the
multi-channel codec, go to
www.analog.com/UploadedFiles/Datasheets/
344740003AD1836_prc.pdf.
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Audio Interface and
Programmable Flags
 The processor has 15 programmable flag pins
(PF’s). The pins are multifunctional and depend on
the processor setup. Table 2-1 in the ADSP-BF533
EZ-KIT Lite Evaluation System Manual provides the
summary of the programmable flag pins used on
the EZ-Kit Lite.
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Programmable Flag
Connections
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Audio Interface Configuration
(cont.)
 The general-purpose IO pin PA0 of flash
A is a source for the AD1836 codec
reset.
 See “Flash General-Purpose IO” on page 112 for more information about the pin of
ADSP-BF533 EZ-KIT Lite Evaluation System
Manual.
 Also information given in the next slide.
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AD1836 codec reset via PA0
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Flash General-Purpose IO


General-purpose IO signals are controlled by means of
setting appropriate registers of the flash A or flash B.
These registers are mapped into the processor’s address
space, as shown in the Table below (ADSP-BF533 EZ-KIT
Lite Evaluation System Manual – Flash Memory)
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Flash General-Purpose IO


Flash device IO pins are arranged as 8-bit ports labeled A through G.
There is a set of 8-bit registers associated with each port. These registers are



Direction,
Data In, and
Data Out.
Note that the Direction and Data Out registers are cleared to all zeros at
power-up or hardware reset.

The Direction register controls IO pins direction. This is a 8-bit read-write
register.


When a bit is 0, a corresponding pin functions as an input.
When the bit is 1, a corresponding pin is an output.

The Data In register allows reading the status of port’s pins. This is a 8-bit
read-only register.

The Data Out register allows clearing an output pin to 0 or setting it to 1. This
is a 8-bit read-write register.

The ADSP-BF533 EZ-KIT Lite board employs only flash A and flash B ports A
and B. Table 1-5 and Table 1-6 provide configuration register addresses for
flash A and flash B, respectively (only ports A and B are listed in the next
slide).

The following bits connect to the expansion board connector.


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Flash A: port A bits 7 and 6, as well as port B bits 7 and 6
Flash B: port A bits 7–0
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Flash A & B Configuration
Registers for Ports A and B.

Table 1-5. Flash A Configuration Registers for Ports A and B
Register Name
Port A Address
Port B Address
Data In (read-only)
0x2027 0000
0x2027 0001
Data Out (read-write)
0x2027 0004
0x2027 0005
Direction (read-write)
0x2027 0006
0x2027 0007

Table 1-6. Flash B Configuration Registers for Ports A and B
Register Name
Port A Address
Port B Address
Data In (read-only)
0x202E 0000
0x202E 0001
Data Out (read-write)
0x202E 0004
0x202E 0005
Direction (read-write)
0x202E 0006
0x202E 0007
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IO Assignments for Port A and
B
 Table 1-7 Flash A Port A Controls.
Bit Number User IO
Bit Value
7
Not defined
Any
6
Not defined
Any
5
PPI clock select bit
1
00=local OSC (27MHz)
4
PPI clock select bit
0
01=video decoder pixel clock
1x=expansion board PPI clock
3
Video decoder reset
0=reset ON; 1=reset OFF
2
Video encoder reset
0=reset ON; 1=reset OFF
1
Reserved
Any
0
Codec reset
0=reset ON; 1=reset OFF
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Talk-Through
Analysis of Lab Exercise
main.c
//--------------------------------------------------------------------------//
//
//
//
Name:
Talkthrough for the ADSP-BF533 EZ-KIT Lite
//
//
//
//--------------------------------------------------------------------------//
//
//
//
(C) Copyright 2003 - Analog Devices, Inc. All rights reserved.
//
//
//
//
Project Name:
BF533 C Talkthrough TDM
//
//
//
//
Date Modified:
04/03/03
HD
Rev 1.0
//
//
//
//
Software:
VisualDSP++3.1
//
//
//
//
Hardware:
ADSP-BF533 EZ-KIT Board
//
//
//
//
Connections:
Connect an input source (such as a radio) to the Audio //
//
input jack and an output source (such as headphones) to
//
the Audio output jack
//
//
//
//
Purpose:
This program sets up the SPI port on the ADSP-BF533 to
//
configure the AD1836 codec. The SPI port is disabled
//
after initialization. The data to/from the codec are
//
transfered over SPORT0 in TDM mode
//
//
//--------------------------------------------------------------------------//
#include
#include
#include
#include
//
//
//
//
//
"Talkthrough.h"
"sysreg.h"
"ccblkfn.h"
<btc.h>
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Talkthrough.h
#ifndef __Talkthrough_DEFINED
#define __Talkthrough_DEFINED
//--------------------------------------------------------------------------//
// Header files
//
//--------------------------------------------------------------------------//
#include <sys\exception.h>
#include <cdefBF533.h>
#include <ccblkfn.h>
#include <sysreg.h>
//--------------------------------------------------------------------------//
// Symbolic constants
//
//--------------------------------------------------------------------------//
// addresses for Port B in Flash A
#define pFlashA_PortA_Dir (volatile unsigned char *)0x20270006
#define pFlashA_PortA_Data (volatile unsigned char *)0x20270004
// names for codec registers, used for iCodec1836TxRegs[]
#define DAC_CONTROL_1
0x0000
#define DAC_CONTROL_2
0x1000
#define DAC_VOLUME_0
0x2000
#define DAC_VOLUME_1
0x3000
#define DAC_VOLUME_2
0x4000
#define DAC_VOLUME_3
0x5000
#define DAC_VOLUME_4
0x6000
#define DAC_VOLUME_5
0x7000
#define ADC_0_PEAK_LEVEL
0x8000
#define ADC_1_PEAK_LEVEL
0x9000
#define ADC_2_PEAK_LEVEL
0xA000
#define ADC_3_PEAK_LEVEL
0xB000
#define ADC_CONTROL_1
0xC000
#define ADC_CONTROL_2
0xD000
#define ADC_CONTROL_3
0xE000
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Flash A & B Configuration
Registers for Ports A and B.

Table 1-5. Flash A Configuration Registers for Ports A and B
Register Name
Port A Address
Port B Address
Data In (read-only)
0x2027 0000
0x2027 0001
Data Out (read-write)
0x2027 0004
0x2027 0005
Direction (read-write)
0x2027 0006
0x2027 0007

Table 1-6. Flash B Configuration Registers for Ports A and B
Register Name
Port A Address
Port B Address
Data In (read-only)
0x202E 0000
0x202E 0001
Data Out (read-write)
0x202E 0004
0x202E 0005
Direction (read-write)
0x202E 0006
0x202E 0007
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DAC Control Register 1 & 2
From: AD1836A Multi-channel Codec Manual
#define DAC_CONTROL_1
0x0000
#define DAC_CONTROL_2
0x1000
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DAC Volume Control Registers
#define
#define
#define
#define
#define
#define
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DAC_VOLUME_0
DAC_VOLUME_1
DAC_VOLUME_2
DAC_VOLUME_3
DAC_VOLUME_4
DAC_VOLUME_5
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0x2000
0x3000
0x4000
0x5000
0x6000
0x7000
28
ADC Peak Level Registers
#define
#define
#define
#define
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ADC_0_PEAK_LEVEL
ADC_1_PEAK_LEVEL
ADC_2_PEAK_LEVEL
ADC_3_PEAK_LEVEL
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0x8000
0x9000
0xA000
0xB000
29
ADC Control Register 1
#define ADC_CONTROL_1
#define ADC_CONTROL_2
#define ADC_CONTROL_3
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0xC000
0xD000
0xE000
30
ADC Control Register 2
#define ADC_CONTROL_1
#define ADC_CONTROL_2
#define ADC_CONTROL_3
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0xC000
0xD000
0xE000
31
ADC Control Register 3
#define ADC_CONTROL_1
#define ADC_CONTROL_2
#define ADC_CONTROL_3
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0xC000
0xD000
0xE000
32
Talkthrough.h (cont. 1)
// names for slots in ad1836 audio frame
#define INTERNAL_ADC_L0
#define INTERNAL_ADC_L1
#define INTERNAL_ADC_R0
#define INTERNAL_ADC_R1
#define INTERNAL_DAC_L0
#define INTERNAL_DAC_L1
#define INTERNAL_DAC_L2
#define INTERNAL_DAC_R0
#define INTERNAL_DAC_R1
#define INTERNAL_DAC_R2
0
1
4
5
0
1
2
4
5
6
// size of array iCodec1836TxRegs and iCodec1836RxRegs
#define CODEC_1836_REGS_LENGTH
11
// SPI transfer mode
#define TIMOD_DMA_TX 0x0003
// SPORT0 word length
#define SLEN_32
0x001f
// DMA flow mode
#define FLOW_1
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0x1000
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Talkthrough.h (cont. 2)
//--------------------------------------------------------------------------//
// Global variables
//
//--------------------------------------------------------------------------//
extern int iChannel0LeftIn;
extern int iChannel0RightIn;
extern int iChannel0LeftOut;
extern int iChannel0RightOut;
extern int iChannel1LeftIn;
extern int iChannel1RightIn;
extern int iChannel1LeftOut;
extern int iChannel1RightOut;
extern volatile short sCodec1836TxRegs[];
extern volatile int iRxBuffer1[];
extern volatile int iTxBuffer1[];
//--------------------------------------------------------------------------//
// Prototypes
//
//--------------------------------------------------------------------------//
// in file Initialisation.c
void Init_EBIU(void);
void Init_Flash(void);
void Init1836(void);
void Init_Sport0(void);
void Init_DMA(void);
void Init_Sport_Interrupts(void);
void Enable_DMA_Sport0(void);
// in file Process_data.c
void Process_Data(void);
// in file ISRs.c
EX_INTERRUPT_HANDLER(Sport0_RX_ISR);
#endif //__Talkthrough_DEFINED
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main.c
#include "Talkthrough.h"
#include "sysreg.h"
#include "ccblkfn.h"
#include <btc.h>
//--------------------------------------------------------------------------//
// Variables
//
//
// Description: The variables iChannelxLeftIn and iChannelxRightIn contain //
//
the data coming from the codec AD1836. The (processed)
//
//
playback data are written into the variables
//
//
iChannelxLeftOut and iChannelxRightOut respectively, which
//
//
are then sent back to the codec in the SPORT0 ISR.
//
The values in the array iCodec1836TxRegs can be modified to
//
//
set up the codec in different configurations according to
//
//
the AD1885 data sheet.
//
//--------------------------------------------------------------------------//
// left input data from ad1836
int iChannel0LeftIn, iChannel1LeftIn;
// right input data from ad1836
int iChannel0RightIn, iChannel1RightIn;
// left ouput data for ad1836
int iChannel0LeftOut, iChannel1LeftOut;
// right ouput data for ad1836
int iChannel0RightOut, iChannel1RightOut;
//
//
// SPORT0 DMA transmit buffer
volatile int iTxBuffer1[8];
// SPORT0 DMA receive buffer
volatile int iRxBuffer1[8];
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main.c (cont 1)
// array for registers to configure the ad1836 names are defined in "Talkthrough.h"
volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] = {
DAC_CONTROL_1
| 0x000,
DAC_CONTROL_2
| 0x000,
DAC_VOLUME_0
| 0x3ff,
DAC_VOLUME_1
| 0x3ff,
DAC_VOLUME_2
| 0x3ff,
DAC_VOLUME_3
| 0x3ff,
DAC_VOLUME_4
| 0x3ff,
DAC_VOLUME_5
| 0x3ff,
ADC_CONTROL_1
| 0x000,
ADC_CONTROL_2
| 0x180,
ADC_CONTROL_3
| 0x000 };
#define
#define
#define
#define
#define
#define
DAC_CONTROL_1
DAC_VOLUME_0
DAC_CONTROL_2
DAC_VOLUME_1
DAC_VOLUME_2
DAC_VOLUME_3
DAC_VOLUME_4
DAC_VOLUME_5
#define ADC_CONTROL_1
#define ADC_CONTROL_2
#define ADC_CONTROL_3
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0x0000
0x2000
0x1000
0x3000
0x4000
0x5000
0x6000
0x7000
|
|
|
|
|
|
0x000
0x3ff
0x000
0x3ff
0x3ff
0x3ff
0x3ff
0x3ff
=
=
=
=
=
=
0x0000
0x23ff
0x1000
0x33ff
0x43ff
0x53ff
0x63ff
0x73ff
0xC000 | 0x000 = 0xC000
0xD000 | 0x180 = 0xD180
0xE000 | 0x000 = 0xE000
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DAC Volume Control Registers
#define
#define
#define
#define
#define
#define
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DAC_VOLUME_0
DAC_VOLUME_1
DAC_VOLUME_2
DAC_VOLUME_3
DAC_VOLUME_4
DAC_VOLUME_5
0x23ff
0x33ff
0x43ff
0x53ff
0x63ff
0x73ff
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0010
0011
0100
0101
0110
0111
0011
0011
0011
0011
0011
0011
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
37
ADC Peak Level Registers
#define
#define
#define
#define
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ADC_0_PEAK_LEVEL
ADC_1_PEAK_LEVEL
ADC_2_PEAK_LEVEL
ADC_3_PEAK_LEVEL
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0x8000
0x9000
0xA000
0xB000
38
ADC Control Register 1
#define ADC_CONTROL_1
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0xC000 1100 000 000 000
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ADC Control Register 2
#define ADC_CONTROL_2
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0xD180 1101 0001 1000 0000
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40
ADC Control Register 3
#define ADC_CONTROL_3
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0xE000
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1110 0000 0000 0000
41
ADC Master Mode
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ADC Slave Mode
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main.c (cont 2)
// SPORT0 DMA transmit buffer
volatile int iTxBuffer1[8];
// SPORT0 DMA receive buffer
volatile int iRxBuffer1[8];
////////////////////
// BTC Definitions
////////////////////
#define MAXBTCBUF 24000
int BTCLeft[MAXBTCBUF];
int BTCRight[MAXBTCBUF];
int BTCLeftVolume = 0;
int BTCRightVolume = 0;
BTC_MAP_BEGIN
//
Channel Name, Starting Address, Length (bytes)
BTC_MAP_ENTRY("Audio Left Channel", (long)&BTCLeft, sizeof(BTCLeft))
BTC_MAP_ENTRY("Audio Right Channel", (long)&BTCRight, sizeof(BTCRight))
BTC_MAP_ENTRY("Audio Left Volume", (long)&BTCLeftVolume, sizeof(BTCLeftVolume))
BTC_MAP_ENTRY("Audio Right Volume", (long)&BTCRightVolume, sizeof(BTCRightVolume))
BTC_MAP_END
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main.c (cont. 3)
//--------------------------------------------------------------------------//
// Function:
main
//
//
//
// Description:
After calling a few initalization routines, main() just //
//
waits in a loop forever. The code to process the incoming //
//
data can be placed in the function Process_Data() in the //
//
file "Process_Data.c".
//
//--------------------------------------------------------------------------//
void main(void)
{
sysreg_write(reg_SYSCFG, 0x32);
Init_EBIU();
Init_Flash();
Init1836();
Init_Sport0();
Init_DMA();
Init_Sport_Interrupts();
Enable_DMA_Sport0();
//Initialize System Configuration Register
btc_init();
while(1) {
btc_poll();
}
}
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Initialize.c
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836
SPORT0
DMA configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
External Bus Interface Unit
(EBIU) Setup
#include "Talkthrough.h"
//--------------------------------------------------------------------------//
// Function:
Init_EBIU
//
//
//
// Description: This function initializes and enables asynchronous memory
//
//
banks in External Bus Interface Unit so that Flash A can be
//
//
accessed.
//
//--------------------------------------------------------------------------//
void Init_EBIU(void)
{
*pEBIU_AMBCTL0 = 0x7bb07bb0;
*pEBIU_AMBCTL1 = 0x7bb07bb0;
*pEBIU_AMGCTL = 0x000f;
}
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External Bus Interface Unit

The EBIU services requests for external memory from the


Core or from a
DMA channel.

The priority of the requests is determined by the External
Bus Controller.

The address of the request determines whether the request
is serviced by the


EBIU SDRAM Controller or the
EBIU Asynchronous Memory Controller.

The EBIU is clocked by the system clock (SCLK). All
synchronous memories interfaced to the processor operate
at the SCLK frequency.

The ratio between core frequency and SCLK frequency is
programmable using a phase-locked loop (PLL) system
memory-mapped register (MMR).
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EBIU Programming Model

This programming model is based on system memorymapped registers used to program the EBIU.

There are


six control registers and
one status register in the EBIU. They are:



Asynchronous Memory Global Control register (EBIU_AMGCTL)
Asynchronous Memory Bank Control 0 register (EBIU_AMBCTL0)
Asynchronous Memory Bank Control 1 register (EBIU_AMBCTL1)



SDRAM Memory Global Control register (EBIU_SDGCTL)
SDRAM Memory Bank Control register (EBIU_SDBCTL)
SDRAM Refresh Rate Control register (EBIU_SDRRC)

SDRAM Control Status register (EBIU_SDSTAT)
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The Asynchronous Memory
Interface
 The asynchronous memory interface allows
interfaceing to a variety of memory and peripheral
types. These include





SRAM,
ROM,
EPROM,
flash memory, and
FPGA/ASIC designs.
 Four asynchronous memory regions are supported.
Each has a unique memory select associated with
it, shown in Table 17-3.
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Asynchronous Memory Bank
Address Range
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54
EBIU_AMGCTL Register
 The Asynchronous Memory Global Control register
(EBIU_AMGCTL) configures global aspects of the
controller.
 The EBIU_AMGCTL register should be the last
control register written to when configuring the
processor to access external memory-mapped
asynchronous devices.
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Initialization.c
//--------------------------------------------------------------------------//
// Function:
Init_EBIU
//
//
//
// Parameters:
None
//
//
//
// Return:
None
//
//
//
// Description:
This function initializes and enables the asynchronous //
//
memory banks for the External Bus Interface Unit (EBIU), so
//
//
that access to Flash A is possible.
//
//--------------------------------------------------------------------------//
void Init_EBIU(void)
{
*pEBIU_AMBCTL0 = 0x7bb07bb0;
*pEBIU_AMBCTL1 = 0x7bb07bb0;
Asynchronous Memory
*pEBIU_AMGCTL = 0x000f;
}
Global Control Register
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Asynchronous Memory Global
Control Register EBIU_AMGCTL
0x000f = 0000 0000 0000 1111
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Initialization.c
//--------------------------------------------------------------------------//
// Function:
Init_EBIU
//
//
//
// Parameters:
None
//
//
//
// Return:
None
//
//
//
// Description:
This function initializes and enables the asynchronous //
//
memory banks for the External Bus Interface Unit (EBIU), so
//
//
that access to Flash A is possible.
//
//--------------------------------------------------------------------------//
void Init_EBIU(void)
{
*pEBIU_AMBCTL0 = 0x7bb07bb0;
Asynchronous Memory
*pEBIU_AMBCTL1 = 0x7bb07bb0;
Control Register
*pEBIU_AMGCTL = 0x000f;
}
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58
EBIU_AMBCTL0 and
EBIU_AMBCTL1 Registers
 The EBIU asynchronous memory
controller has two Asynchronous
Memory Bank Control registers:
 EBIU_AMBCTL0 and
 EBIU_AMBCTL1.
 They contain bits for counters for:





setup,
strobe, and
hold time;
bits to determine memory type and size; and
bits to configure use of ARDY.
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59
Asynchronous Memory Bank
Control 0 Register
0x7bb07bb0 =
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0111 1011 1011 0000
0111 1011 1011 0000
60
External Memory Map

The three SDRAM control registers
must be initialized in order to use the
MT48LC32M16 – 64 MB (32M x 16
bits) SDRAM memory of EZ-Kit Lite:




EBIU_SDGCTL: SDRAM Memory
Global Control register
EBIU_SDBCTL: SDRAM Memory
Bank Control register
EBIU_SDRRC: SDRAM Refresh
Rate Control register
The External Memory Map supported
by BF533 is provided in the Figure
17-1.
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61
EBIU_SDGCTL Register
 The SDRAM Memory Global
Control register (EBIU_SDGCTL)
includes all programmable
parameters associated with the
SDRAM access timing and
configuration. Figure 17-10
shows the EBIU_SDGCTL register
bit definitions.
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62
SDRAM Memory Global Control
register: EBIU_SDGCTL
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63
Initialize.c
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836
SPORT0
DMA configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
Initialize.c
//--------------------------------------------------------------------------//
// Function:
Init_Flash
//
//
//
// Description: This function initializes pin direction of Port A in Flash A //
//
to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board
//
//
is connected to Port A.
//
//--------------------------------------------------------------------------//
void Init_Flash(void)
{
*pFlashA_PortA_Dir = 0x1;
}
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Initialize.c
//--------------------------------------------------------------------------//
// Function:
Init_Flash
//
//
//
// Description: This function initializes pin direction of Port A in Flash A //
//
to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board
//
//
is connected to Port A.
//
//--------------------------------------------------------------------------//
void Init_Flash(void)
{
Direction
*pFlashA_PortA_Dir = 0x1;
0x1 = 0001
Configuration
}
•The Direction register controls IO pins direction.
This is a 8-bit read-write register.
•When a bit is 0, a corresponding pin functions as an input.
•When the bit is 1, a corresponding pin is an output.
•See Slide #13 for details or EZ-Kit Lite HRM.
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66
Initialize.c
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADC1836
SPORT0
DMA configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
BF533 Interface with AD1871
Data Transfer
& Synch
Configuration
& Control
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Initialize.c
//--------------------------------------------------------------------------//
// Function: Init1836()
//
//
//
// Description: This function sets up the SPI port to configure the AD1836. //
//
The content of the array sCodec1836TxRegs is sent to the //
//
codec.
//
//--------------------------------------------------------------------------//
void Init1836(void)
{
int i;
int j;
static unsigned char ucActive_LED = 0x01;
// write to Port A to reset AD1836
*pFlashA_PortA_Data = 0x00;
Reset AD1836 ADC &
DAC Codec.
// write to Port A to enable AD1836
*pFlashA_PortA_Data = ucActive_LED;
// wait to recover from reset
for (i=0; i<0xf000; i++);
// Enable PF4
*pSPI_FLG = FLS4;
// Set baud rate SCK = HCLK/(2*SPIBAUD) SCK = 2MHz
*pSPI_BAUD = 16;
// configure spi port
// SPI DMA write, 16-bit data, MSB first, SPI Master
*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR;
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Activate AD1836 Via
PF4 pin
Setting the Baud Rate
of the SPI Interface
with the
Codec
Setting
the
DMA
transfer
69
Serial Peripheral Interface
(SPI)

The processor has a Serial Peripheral Interface (SPI) port
that provides an I/O interface to a wide variety of SPI
compatible peripheral devices.

SPI is a four-wire interface consisting of




SPI is a





two data pins (IN & OUT), a
device select pin (SPISS), and a
clock (CLK) pin.
full-duplex synchronous serial interface, supporting
master modes,
slave modes, and
multimaster environments.
The SPI compatible peripheral implementation also
supports


programmable baud rate and
clock phase/polarities.
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Serial Peripheral Interface
(SPI)
 Typical SPI compatible peripheral
devices that can be used to interface to
the SPI compatible interface include:
Other CPUs or microcontrollers
Codecs
A/D converters
D/A converters
Sample rate converters
SP/DIF or AES/EBU digital audio transmitters
and receivers
 LCD displays
 Shift registers
 FPGAs with SPI emulation






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Serial Peripheral Interface
(SPI)

The SPI is an industry-standard synchronous serial link that
supports communication with multiple SPI compatible
devices. The SPI peripheral is a synchronous, four-wire
interface consisting of



two data pins:


Master Out Slave In (MOSI) and
Master In Slave Out (MISO)

Serial Peripheral Interface Slave Select (SPISS) Input Signal, and a

Serial Peripheral Interface Clock (SCK) Signal.
one device select pin
gated clock pin

With the two data pins, it allows for full-duplex operation to
other SPI compatible devices.

The SPI also includes



programmable baud rates,
clock phase, and
clock polarity.
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Serial Peripheral Interface
(SPI)

The SPI can operate in a multimaster environment by
interfacing with several other devices, acting as either a
master device or a slave device.

Figure 10-1 provides a block diagram of the SPI. The
interface is essentially a shift register that serially
transmits and receives data bits, one bit at a time at the
SCK rate, to and from other SPI devices. SPI data is
transmitted and received at the same time through the use
of a shift register.

When an SPI transfer occurs, data is simultaneously
transmitted (shifted serially out of the shift register) as
new data is received (shifted serially into the other end of
the same shift register).

The SCK synchronizes the shifting and sampling of the data
on the two serial data pins.
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73
SPI Block Diagram
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74
SPI Interface Signals
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836 - SPI
SPORT0
DMA configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
Serial Peripheral Interface
Clock Signal (SCK)




The SCK signal is the SPI clock signal. This control signal is driven by the
master and controls the rate at which data is transferred. The master may
transmit data at a variety of baud rates.

The SCK signal cycles once for each bit transmitted.


output signal if the device is configured as a master, and an
input signal if the device is configured as a slave.
It is an
The SCK is a gated clock that is active during data transfers only for the
length of the transferred word. The number of active clock edges is equal to
the number of bits driven on the data lines.
Slave devices ignore the serial clock if the Serial Peripheral Slave Select
Input (SPISS’) is driven inactive (high).

The SCK is used to shift out and shift in the data driven on the MISO and
MOSI lines. The data is always shifted out on active edges of the clock and
sampled on inactive edges of the clock.

Clock polarity and clock phase relative to data are programmable in the SPI
Control register (SPI_CTL) and define the transfer format.
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76
Serial Peripheral Interface Slave Select Input
Signal
 The SPISS’ signal is the SPI Serial Peripheral Slave
Select Input signal.




This is an active-low signal used to enable a
processor when it is configured as a slave device.
This input-only pin behaves like a chip select and is
provided by the master device for the slave devices.
For a master device, it can act as an error signal
input in case of the multimaster environment.
In multimaster mode, if the SPISS input signal of a
master is asserted (driven low), and the PSSE bit in
the SPI_CTL register is enabled, an error has
occurred. This means that another device is also
trying to be the master device.
 Note: The SPISS signal is the same pin as the PF0 pin.
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Master Out Slave In (MOSI)
& Master In Slave Out (MISO)

Master Out Slave In (MOSI)

The MOSI pin is the Master Out Slave In pin, one of the
bidirectional I/O data pins.




If the processor is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data.
If the processor is configured as a slave, the MOSI pin becomes
a data receive (input) pin, receiving input data.
In an SPI interconnection, the data is shifted out from the MOSI
output pin of the master and shifted into the MOSI input(s) of
the slave(s).
Master In Slave Out (MISO)

The MISO pin is the Master In Slave Out pin, one of the
bidirectional I/O data pins.


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If the processor is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data.
If the processor is configured as a slave, the MISO pin becomes
a data transmit (output) pin,
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78
BF533 Interface with AD1871
Data Transfer
& Synch
Configuration
& Control
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79
ADSP-BF533 as Slave SPI
Device
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80
Interrupt Output
 The SPI has two interrupt output
signals:
 a data interrupt and
 an error interrupt
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81
SPI Data Interrupt Output
 The behavior of the SPI data interrupt signal depends
on the Transfer Initiation Mode bit field (TIMOD)
in the SPI Control register (discussed next).
 In DMA mode (TIMOD = 1X), the data interrupt
acts as a DMA request and is generated when
the DMA FIFO is ready to be
 written to (TIMOD = 11) or
 read from (TIMOD = 10).
 In non-DMA mode (TIMOD = 0X), a data
interrupt is generated
 when the SPI_TDBR is ready to be written to
(TIMOD = 01) or
 when the SPI_RDBR is ready to be read from
(TIMOD = 00).
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SPI Error Interrupt Output
 An SPI Error interrupt is generated in a
master when a Mode Fault Error occurs, in
both DMA and non-DMA modes.
 An error interrupt can also be generated in
DMA mode when there is
 an underflow (TXE when TIMOD = 11) or
 an overflow (RBSY when TIMOD = 10)
error condition.
 In non-DMA mode, the underflow and
overflow conditions set the TXE and RBSY
bits in the SPI_STAT register, respectively,
but do not generate an error interrupt.
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83
SPI Registers


The SPI peripheral includes a number of user-accessible registers.
Some of these registers are also accessible through the DMA bus.
Four registers contain control and status information:





SPI_BAUD,
SPI_CTL,
SPI_FLG, and
SPI_STAT.
Two registers are used for buffering receive and transmit data:


SPI_RDBR and
SPI_TDBR

For information about DMA-related registers, see Chapter 9 of
ADSP-BF533 Blackfin Processor Hardware Reference, “Direct
Memory Access.” also discussed next.

The shift register, SFDR, is internal to the SPI module and is not
directly accessible.
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84
SPI Registers: SPI_BAUD
Register
 The SPI Baud Rate register (SPI_BAUD) is
used to set the bit transfer rate for a
master device.
 When configured as a slave, the value
written to this register is ignored.
 The serial clock frequency is determined by
this formula:
 SCK Frequency = (Peripheral clock
frequency SCLK)/(2 x SPI_BAUD)
 SCK – Clock Divide Factor
 SPI_BAUD = 16 & assuming SCLK = 100
MHz ⇒ SCK = 100 MHz/32 = 3125 kHz.
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85
SPI_BAUD Register
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86
SCLK & CCLK

Read “PLL Clock Multiplier Ratios” section of chapter 8
“Dynamic Power Management” of “ADSP-BF533 Blackfin
Processor Hardware Reference” manual.

Brief summary of the clock sources and clock rates:

The clock source on EZ Kit is 270 MHz oscillator.

The default SCLK is 54 MHz.

The SCLK value can be calculated from the PLL_CTL and
PLL_DIV register values. By default the PLL_CTL = 0x1400,
here the MSEL = 10, so the VCO frequency is 10x27 = 270
MHz.

By default the PLL_DIV = 0x0005, here CSEL = 0 and SSEL
= 5, so


CCLK = 270/1 = 270 MHz and
SCLK = 270/5 = 54 MHz.
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87
Note on SPORT Clock division
and frame sync

The clock division parameters are located in the



SPORTx_TCLKDIV and
SPORTx_RCLKDIV registers.
To specify a clock frequency for the SPORT, use the following equation:
f ( sclk )
SPORTx _ yCLK _ frequency 
2 * SPORTx _ yCLKDIV  1

Where:






f(sclk) is the frequency of the core (54 Mhz default on the EZ-KIT LITE),
SPORTx_yCLK (y is T - for transmit, R – for receive) frequency is the specified clock frequency of
the SPORT, and
SPORTx_yCLKDIV is the value needed to be input into the specified transmit/receive clock
division register.
Frame sync parameters are the number of serial clock cycles before a frame
sync is generated. This value must not be less than the serial word length
(SLEN), otherwise corrupt data will be received.
# of serial clock cycles between frame syncs = SPORTx_yFSDIV + 1
For example, if one wanted a serial clock frequency of 375 kHz, and 32 bit
words were used, then


SPORTx_yCLKDIV = 54MHz/(2*375kHz) - 1 = 72 - 1 = 71 = 0x0048
SPORTx_yFSDIV = 32 - 1 = 31 = 0x001f
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88
SPI_CTL Register
 The SPI Control register (SPI_CTL) is used
to
 configure and
 enable the SPI system.
 This register is used to
 enable the SPI interface,
 select the device as
 a master or
 slave, and
 determine the data transfer
 format and
 word size.
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89
SPI_CTL Register Details


The term “word” refers to a single data transfer of either 8 bits or
16 bits, depending on the word length (SIZE) bit in SPI_CTL.
There are two special bits which can also be modified by the
hardware:



SPE and
MSTR.
The TIMOD field is used to specify the action that initiates
transfers to/from the receive/transmit buffers.




When set to 00, a SPI port transaction is begun when the
receive buffer is read. Data from the first read will need to be
discarded since the read is needed to initiate the first SPI port
transaction.
When set to 01, the transaction is initiated when the transmit
buffer is written.
A value of 10 selects DMA Receive Mode and the first
transaction is initiated by enabling the SPI for DMA Receive
mode. Subsequent individual transactions are initiated by a
DMA read of the SPI_RDBR.
A value of 11 selects DMA Transmit Mode and the transaction is
initiated by a DMA write of the SPI_TDBR.
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SPI_CTL Register Details
 The PSSE bit is used to enable the SPISS input for
master. When not used, SPISS can be disabled,
freeing up a chip pin as general-purpose I/O.
 The EMISO bit enables the MISO pin as an output.
This is needed in an environment where the master
wishes to transmit to various slaves at one time
(broadcast). Only one slave is allowed to transmit
data back to the master. Except for the slave from
whom the master wishes to receive, all other slaves
should have this bit cleared.
 The SPE and MSTR bits can be modified by hardware
when the MODF bit of the Status register is set. See
“Mode Fault Error” on page 10-27 of ADSP-BF533
Blackfin Processor Hardware Reference manual.
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SPI_CTL Register Details
*pSPI_CTL = TIMOD_DMA_TX |
TIMOD_DMA_TX 0x0003 = 0000
SIZE
= 0000
MSTR
= 0001
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SIZE
0000
0001
0000
| MSTR
0000 0011
0000 0000
0000 0000
92
Summary of SPI Register
Functions
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93
BF533 Direct Memory
Access - DMA
BF533 DMA Support
ADSP-BF533 Ez-Kit Lite Audio
Interface
EBIU
SPI
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SPORT0
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95
Processor Memory Architecture
Core
Processor
L1
Memory
DMA
Controller
EBIU
DMA
Peripherals
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96
BF533 DMA Support


The processor has multiple, independent DMA controllers that
support automated data transfers with minimal overhead for the
core.
DMA transfers can occur between


the internal memories and any of its DMA-capable peripherals.
Additionally, DMA transfers can be accomplished between any
of the DMA-capable peripherals and external devices connected
to the external memory interfaces, including the SDRAM
controller and the asynchronous memory controller. DMAcapable peripherals include the





SPORTs,
SPI port,
UART, and
PPI.
Each individual DMA-capable peripheral has at least one dedicated
DMA channel.
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BF533 DMA Support
 The DMA controller supports both


one-dimensional (1D) and
two-dimensional (2D) DMA transfers.
 DMA transfer initialization can be implemented


from registers or
from sets of parameters called descriptor blocks.
 The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary
row and column step sizes up to +/- 32K elements.
Furthermore, the column step size can be less than the row
step size, allowing implementation of interleaved
datastreams. This feature is especially useful in video
applications where data can be de-interleaved on the fly.
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98
Generic Names of the DMA
Memory-Mapped Registers
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99
DMA Channel Map
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100
DMA Channel Map
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101
ADI1836 SPI DMA
Configuration
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836 - DMA
SPORT0
DMA configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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DMA Channel’s Peripheral Map
Register
 Each DMA channel’s Peripheral Map register
(DMAx_PERIPHERAL_MAP) contains bits that:
 Map the channel to a specific peripheral.
 Identify whether the channel is a Peripheral
DMA channel or a Memory DMA channel.
*pDMA5_PERIPHERAL_MAP
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= 0x5000;
104
Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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DMA Configuration Register

The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in
Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this
slide is used to set up DMA parameters and operating modes.
*pDMA5_CONFIG = 0000 0000 0000 0100 = 0x0004;
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Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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main.c (cont 1)
// array for registers to configure the ad1836 names are defined in "Talkthrough.h"
volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] = {
DAC_CONTROL_1
| 0x000,
DAC_CONTROL_2
| 0x000,
DAC_VOLUME_0
| 0x3ff,
DAC_VOLUME_1
| 0x3ff,
DAC_VOLUME_2
| 0x3ff,
DAC_VOLUME_3
| 0x3ff,
DAC_VOLUME_4
| 0x3ff,
DAC_VOLUME_5
| 0x3ff,
ADC_CONTROL_1
| 0x000,
ADC_CONTROL_2
| 0x180,
ADC_CONTROL_3
| 0x000 };
#define
#define
#define
#define
#define
#define
DAC_CONTROL_1
DAC_VOLUME_0
DAC_CONTROL_2
DAC_VOLUME_1
DAC_VOLUME_2
DAC_VOLUME_3
DAC_VOLUME_4
DAC_VOLUME_5
#define ADC_CONTROL_1
#define ADC_CONTROL_2
#define ADC_CONTROL_3
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0x0000
0x2000
0x1000
0x3000
0x4000
0x5000
0x6000
0x7000
|
|
|
|
|
|
0x000
0x3ff
0x000
0x3ff
0x3ff
0x3ff
0x3ff
0x3ff
=
=
=
=
=
=
0x0000
0x23ff
0x1000
0x33ff
0x43ff
0x53ff
0x63ff
0x73ff
0xC000 | 0x000 = 0xC000
0xD000 | 0x180 = 0xD180
0xE000 | 0x000 = 0xE000
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DMA Start Address Register

The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR),
shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also
in the next slide, contains the start address of the data buffer currently targeted
for DMA.
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Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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DMA Count Register

For 1D DMA, it specifies the number of elements to read in. For 2D DMA details,
see “Two-Dimensional DMA” on page 9-45 of ADSP-BF533 Blackfin Processor
Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements.
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Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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DMAx Modify Register


The Inner Loop Address Increment register
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, two’s-complement
byte-address increment. In 1D DMA, this increment is the stride that is applied
after transferring each element.
Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.
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Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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DMA Configuration Register
*pDMA5_CONFIG = WDSIZE_16;
WDSIZE_16 = 0x0004;
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
DMAEN = 0x0001
*pDMA5_CONFIG = 0x0005
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Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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SPI_CTL Register Details
*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR
TIMOD_DMA_TX 0x0003 = 0000 0000 0000 0011
*pSPI_CTL = *pSPI_CTL | SPE
SPE 0x4000 = 0100 0000 0000 0000
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Initialize.c: Init1836()
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP
= 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
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Serial Port Controllers:
SPORT
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836 - DMA
SPORT0
DMA configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
ADSP-BF533 Ez-Kit Lite Audio
Interface
EBIU
SPI
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SPORT0
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Serial Port Controllers (SPORT)

The processor has two identical synchronous serial ports, or SPORTs. These support a
variety of serial data communications protocols and can provide a direct
interconnection between processors in a multiprocessor system.

The serial ports (SPORT0 and SPORT1) provide an I/O interface to a wide variety of
peripheral serial devices.



SPORTs provide synchronous serial data transfer only;
The processor provides asynchronous RS-232 data transfer via the UART.
Each SPORT has one group of pins:




primary data,
secondary data,
clock, and
frame sync
for transmit and a second set of pins for receive.

The receive and transmit functions are programmed separately.

Each SPORT is a full duplex device, capable of simultaneous data transfer in both
directions. The SPORTs can be programmed by writing to memory-mapped registers for



bit rate,
frame sync, and
number of bits per word
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SPORT (cont.)
 Both SPORTs have the same capabilities and are
programmed in the same way.
 Each SPORT has its own set of
 control registers and
 data buffers.
 The SPORTs use frame sync pulses to indicate the
beginning of each word or packet, and the bit clock
marks the beginning of each data bit.
 External bit clock and frame sync are available for the
TX and RX buffers.
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SPORT (cont.)

With a range of clock and frame synchronization options, the SPORTs allow
a variety of serial communication protocols.

The SPORTs can operate at up to an SCLK/2 clock rate with an externally
generated clock, or 1/2 the system clock rate for an internally generated
serial port clock.
The SPORT external clock must always be less than the SCLK frequency.
Independent transmit and receive clocks provide greater flexibility for serial
communications.


SPORT clocks and frame syncs can be internally generated by the system or
received from an external source.

The SPORTs can operate with a transmission format of LSB first or MSB
first, with word lengths selectable from 3 to 32 bits.

They offer selectable transmit modes and optional μ-law or A-law
companding in hardware. SPORT data can be automatically transferred
between on-chip and off-chip memories using DMA block transfers.

Additionally, each of the SPORTs offers a TDM (Time-Division-Multiplexed)
Multichannel mode.
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SPORT Features for Audio
Exercise
 Provides Direct Memory Access transfer to and from
memory under DMA Master control.
 DMA can be
 autobuffer-based (a repeated, identical range
of transfers) or
 descriptor-based (individual or repeated ranges
of transfers with differing DMA parameters).
 Executes DMA transfers to and from on-chip memory.
Each SPORT can automatically receive and transmit
an entire block of data.
 Permits chaining of DMA operations for multiple data
blocks.
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SPORT Pins
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125
SPORT
•Data
to be transmitted
is written
•The
receive
portion of the
SPORT
A
SPORT
For
transmit:
from
an data
internal
processor
register to
accepts
from
the
•Receives
serial
data on and
its DRxPRI
•
The
data
bits
(DTxPRI
DTxSEC)
the SPORT’s SPORTx_TX register
via
•DRxPRI/DRxSEC
pin
and
DRxSEC inputs
and transmit clock
are
synchronous
to
the
the peripheral bus.
(TSCLKx).
•synchronous
to the
serial
clock
on
•Transmits serial
data
on its
DTxPRI
•This data is optionally compressed by
the
RSCLKx
and
DTxSECpin.
outputs.
For hardware
receive:
the
and automatically
transferred
to the
TX
Shift
register.the
•When
an entire
word
is and
received,
It
can data
receive
and
transmit
• The
bits
(DRxPRI
data
is optionally
simultaneously
forexpanded,
full-duplex
DRxSEC)
are
synchronous
tothen
the
•The
bits in
the
Shift register
are
operation.
receive
clock
(RSCLKx).
shifted
out on the
SPORT’s to the
•automatically
transferred
SPORT’s
SPORTx_RX
register,
and
• The• serial
clock is an
output
if the
DTxPRI/DTxSEC
pin,
then
processor generates it, or an input if
• MSB
or LSBgenerated.
first,
the clock
is first
externally
•into
the RX
FIFO where
it is available
Synchronous
to thesignals
serial RFSx
clock
to
the• processor.
• Frame
synchronization
on the
TSCLKx
pin.
and TFSx
are
used to
indicate the
start of a serial data word or stream
of serial words.
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SPORT Generic Operation

Writing to a SPORT’s SPORTx_TX register readies the SPORT for
transmission.




The SPORT generates



The TFS signal initiates the transmission of serial data. Once transmission
has begun, each value written to the SPORTx_TX register is transferred
through the FIFO to the internal Transmit Shift register.
The bits are then sent, beginning with either the MSB or the LSB as
specified in the SPORTx_TCR1 register. Each bit is shifted out on the
driving edge of TSCLKx.
The driving edge of TSCLKx can be configured to be rising or falling.
the transmit interrupt or
requests a DMA transfer as long as there is space in the TX FIFO.
As a SPORT receives bits, they accumulate in an internal receive register.
When a complete word has been received, it is written to the SPORT FIFO
register and


the receive interrupt for that SPORT is generated or
A DMA transfer is initiated.

Interrupts are generated differently if DMA block transfers are
performed. For information about DMA, see Chapter 9, “Direct Memory
Access.”
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Generic Multichannel SPORT
Connectivity
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128
AD1836 and SPORT
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129
Initialize.c : Init_Sport0
//--------------------------------------------------------------------------//
// Function:
Init_Sport0
//
//
//
// Description: Configure Sport0 for TDM mode, to transmit/receive data
//
//
to/from the AD1836. Configure Sport for external clocks and
//
//
frame syncs.
//
//--------------------------------------------------------------------------//
void Init_Sport0(void)
{
// Sport0 receive configuration
// External CLK, External Frame sync, MSB first
// 32-bit data
*pSPORT0_RCR1 = RFSR;
*pSPORT0_RCR2 = SLEN_32;
// Sport0 transmit configuration
// External CLK, External Frame sync, MSB first
// 24-bit data
*pSPORT0_TCR1 = TFSR;
*pSPORT0_TCR2 = SLEN_32;
// Enable MCM 8 transmit & receive channels
*pSPORT0_MTCS0 = 0x000000FF;
*pSPORT0_MRCS0 = 0x000000FF;
// Set MCM configuration register and enable MCM mode
*pSPORT0_MCMC1 = 0x0000;
*pSPORT0_MCMC2 = 0x101c;
}
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Setting SPORT Modes
 SPORT configuration is accomplished by setting bit and field
values in configuration registers.


Each SPORT must be configured prior to being enabled.
Once the SPORT is enabled, further writes to the SPORT
Configuration registers are disabled (except for
SPORTx_RCLKDIV, SPORTx_TCLKDIV, and Multichannel
Mode Channel Select registers).

To change values in all other SPORT Configuration
registers, disable the SPORT by clearing TSPEN in
SPORTx_TCR1 and/or RSPEN in SPORTx_RCR1.
 Each SPORT has its own set of control registers and data
buffers. These registers are described in detail in the
following sections as they relate to audio LAB’s.
 All control and status bits in the SPORT registers are active
high unless otherwise noted.
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SPORTx_RCR1 and
SPORTx_RCR2 Registers

The main control registers for the receive portion of each SPORT are the
Receive Configuration registers:


SPORTx_RCR1 and
SPORTx_RCR2.

A SPORT is enabled for receive if Bit 0 (RSPEN) of the Receive Configuration
1 register is set to 1. This bit is cleared during either a hard reset or a soft
reset, disabling all SPORT reception.

When the SPORT is enabled to receive (RSPEN bit is set), corresponding
SPORT Configuration register writes are not allowed except for
SPORTx_RCLKDIV and Multichannel Mode Channel Select registers.

Writes to disallowed registers have no effect. While the SPORT is
enabled, SPORTx_RCR1 is not written except for bit 0 (RSPEN). For
example:
write (SPORTx_RCR1, 0x0001) ; /* SPORT RX Enabled */
write (SPORTx_RCR1, 0xFF01) ; /* ignored, no effect */
write (SPORTx_RCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_RCR1
still equal to 0x0000 */
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SPORTx Receive Configuration
1 Register
*pSPORT0_RCR1 = RFSR;
RFSR = 0x0000 or 0x0400;
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SPORTx Receive Configuration
2 Register
*pSPORT0_RCR2 = SLEN_32
SLEN_32 = 0x001f;
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SPORTx_RCR1 and
SPORTx_RCR2 Registers

Additional information for the SPORTx_RCR1 and SPORTxRCR2
Receive Configuration register bits:

Receive Enable (RSPEN). This bit selects whether the SPORT is



Setting the RSPEN bit turns on the SPORT and




causes it to sample data from the data receive pins as well as
the receive bit clock and
Receive Frame Sync pins if so programmed.
Setting RSPEN enables the SPORTx receiver, which can generate a
SPORTx RX interrupt.



enabled to receive (if set) or
disabled (if cleared).
For this reason, the code should initialize the ISR and the DMA
control registers first, and should be ready to service RX
interrupts before setting RSPEN.
Setting RSPEN also generates DMA requests if DMA is enabled
and data is received.
Set all DMA control registers before setting RSPEN.
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SPORTx_RCR1 and
SPORTx_RCR2 Registers

Clearing RSPEN causes the SPORT to



stop receiving data;
it also shuts down the internal SPORT receive circuitry.
In low power applications, battery life can be extended by clearing
RSPEN whenever the SPORT is not in use.

Internal Receive Clock Select. (IRCLK). This bit selects the internal
receive clock (if set) or external receive clock (if cleared). The
RCLKDIV MMR value is not used when an external clock is selected.

Data Formatting Type Select. (RDTYPE). The two RDTYPE bits
specify one of four data formats used for single and multichannel
operation.

Bit Order Select. (RLSBIT). The RLSBIT bit selects the bit order of the
data words received over the SPORTs.
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SPORTx_RCR1 and
SPORTx_RCR2 Registers

Serial Word Length Select. (SLEN). The serial word length (the
number of bits in each word received over the SPORTs) is calculated by
adding 1 to the value of the SLEN field. The SLEN field can be set to a
value of 2 to 31; 0 and 1 are illegal values for this field.

Internal Receive Frame Sync Select. (IRFS). This bit selects
whether the SPORT uses an internal RFS (if set) or an external RFS
(if cleared).

Receive Frame Sync Required Select. (RFSR). This bit selects
whether the SPORT requires (if set) or does not require (if cleared)
a Receive Frame Sync for every data word.

Low Receive Frame Sync Select. (LRFS). This bit selects an
active low RFS (if set) or active high RFS (if cleared).

Late Receive Frame Sync. (LARFS). This bit configures late
frame syncs (if set) or early frame syncs (if cleared).
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SPORTx_RCR1 and
SPORTx_RCR2 Registers

Clock Drive/Sample Edge Select. (RCKFE). This bit selects
which edge of the RSCLK clock signal the SPORT uses for sampling
data, for sampling externally generated frame syncs, and for
driving internally generated frame syncs. If set, internally
generated frame syncs are driven on the falling edge, and data
and externally generated frame syncs are sampled on the rising
edge. If cleared, internally generated frame syncs are driven on
the rising edge, and data and externally generated frame syncs
are sampled on the falling edge.

RxSec Enable. (RXSE). This bit enables the receive secondary
side of the serial port (if set).

Stereo Serial Enable. (RSFSE). This bit enables the Stereo Serial
operating mode of the serial port (if set). By default this bit is
cleared, enabling normal clocking and frame sync.

Left/Right Order. (RRFST). If this bit is set, the right channel is
received first in Stereo Serial operating mode. By default this bit is
cleared, and the left channel is received first.
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SPORTx_TCR1 and
SPORTx_TCR2 Registers




The main control registers for the transmit portion of each SPORT
are the Transmit Configuration registers, SPORTx_TCR1 and
SPORTx_TCR2.
A SPORT is enabled for transmit if Bit 0 (TSPEN) of the Transmit
Configuration 1 register is set to 1.
This bit is cleared during either a hard reset or a soft reset,
disabling all SPORT transmission.
When the SPORT is enabled to transmit (TSPEN set),
corresponding SPORT Configuration register writes are not allowed
except for SPORTx_TCLKDIV and Multichannel Mode Channel
Select registers.

Writes to disallowed registers have no effect. While the SPORT
is enabled, SPORTx_TCR1 is not written except for bit 0
(TSPEN). For example:
write (SPORTx_TCR1, 0x0001) ; /* SPORT TX Enabled */
write (SPORTx_TCR1, 0xFF01) ; /* ignored, no effect */
write (SPORTx_TCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_TCR1
still equal to 0x0000 */
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SPORTX Transmit Configuration
1 Register: SPORTx_TCR1
*pSPORT0_TCR1 = TFSR;
TFSR = 0x0000 or 0x0400;
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SPORTX Transmit Configuration
2 Register: SPORTx_TCR2
*pSPORT0_TCR2 = SLEN_32;
SLEN_32 = 0x001f;
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SPORTx_TCR1 and
SPORTx_TCR2 Registers

Additional information for the SPORTx_TCR1 and SPORTx_TCR2 Transmit
Configuration register bits includes:

Transmit Enable (TSPEN). This bit selects whether the SPORT is enabled
to transmit (if set) or disabled (if cleared). Setting TSPEN causes an
immediate assertion of a SPORT TX interrupt, indicating that the TX data
register is empty and needs to be filled. This is normally desirable because
it allows centralization of the transmit data write code in the TX interrupt
service routine (ISR). For this reason, the code should initialize the ISR
and be ready to service TX interrupts before setting TSPEN.



Similarly, if DMA transfers will be used, DMA control should be configured
correctly before setting TSPEN. Set all DMA control registers before
setting TSPEN.
Clearing TSPEN causes the SPORT to stop driving data, TSCLK, and frame
sync pins; it also shuts down the internal SPORT circuitry. In low power
applications, battery life can be extended by clearing TSPEN whenever
the SPORT is not in use.
All SPORT control registers should be programmed before TSPEN is set.
Typical SPORT initialization code first writes all control registers, including
DMA control if applicable. The last step in the code is to write SPORTx_TCR1
with all of the necessary bits, including TSPEN.
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SPORTx_TCR1 and
SPORTx_TCR2 Registers

Internal Transmit Clock Select. (ITCLK). This bit selects the internal
transmit clock (if set) or the external transmit clock on the TSCLK pin (if
cleared). The TCLKDIV MMR value is not used when an external clock is
selected.

Data Formatting Type Select. The two TDTYPE bits specify data formats
used for single and multichannel operation.

Bit Order Select. (TLSBIT). The TLSBIT bit selects the bit order of the data
words transmitted over the SPORT.

Serial Word Length Select. (SLEN). The serial word length (the number
of bits in each word transmitted over the SPORTs) is calculated by adding 1
to the value of the SLEN field:
Serial Word Length = SLEN + 1;

The SLEN field can be set to a value of 2 to 31; 0 and 1 are illegal values
for this field. Three common settings for the SLEN field are 15, to transmit a
full 16-bit word; 7, to transmit an 8-bit byte; and 23, to transmit a 24-bit
word. The processor can load 16- or 32-bit values into the transmit buffer
via DMA or an MMR write instruction; the SLEN field tells the SPORT how
many of those bits to shift out of the register over the serial link. The serial
port transfers bits [SLEN:0] from the transmit buffer.
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SPORTx_TCR1 and
SPORTx_TCR2 Registers

Internal Transmit Frame Sync Select. (ITFS). This bit selects whether
the SPORT uses an internal TFS (if set) or an external TFS (if cleared).

Transmit Frame Sync Required Select. (TFSR). This bit selects whether
the SPORT requires (if set) or does not require (if cleared) a Transmit
Frame Sync for every data word.

Data-Independent Transmit Frame Sync Select. (DITFS). This bit
selects whether the SPORT generates a data-independent TFS (sync at
selected interval) or a data-dependent TFS (sync when data is present in
SPORTx_TX) for the case of internal frame sync select (ITFS = 1). The
DITFS bit is ignored when external frame syncs are selected.

The frame sync pulse marks the beginning of the data word. If DITFS is set, the
frame sync pulse is issued on time, whether the SPORTx_TX register has been
loaded or not; if DITFS is cleared, the frame sync pulse is only generated if the
SPORTx_TX data register has been loaded. If the receiver demands regular frame
sync pulses, DITFS should be set, and the processor should keep loading the
SPORTx_TX register on time. If the receiver can tolerate occasional late frame
sync pulses, DITFS should be cleared to prevent the SPORT from transmitting old
data twice or transmitting garbled data if the processor is late in loading the
SPORTx_TX register.
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SPORTx_TCR1 and
SPORTx_TCR2 Registers

Low Transmit Frame Sync Select. (LTFS). This bit selects an active low TFS (if set)
or active high TFS (if cleared).

Late Transmit Frame Sync. (LATFS). This bit configures late frame syncs (if set) or
early frame syncs (if cleared).

Clock Drive/Sample Edge Select. (TCKFE). This bit selects which edge of the TCLKx
signal the SPORT uses for driving data, for driving internally generated frame syncs,
and for sampling externally generated frame syncs. If set, data and internally
generated frame syncs are driven on the falling edge, and externally generated frame
syncs are sample on the rising edge. If cleared, data and internally generated frame
syncs are driven on the rising edge, and externally generated frame syncs are sampled
on the falling edge.

TxSec Enable. (TXSE). This bit enables the transmit secondary side of the serial port
(if set).

Stereo Serial Enable. (TSFSE). This bit enables the Stereo Serial operating mode of
the serial port (if set). By default this bit is cleared, enabling normal clocking and frame
sync.

Left/Right Order. (TRFST). If this bit is set, the right channel is transmitted first in
Stereo Serial operating mode. By default this bit is cleared, and the left channel is
transmitted first.
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Data Word Formats
 The format of the data words
transferred over the SPORTs is
configured by the combination of:
 transmit SLEN and receive SLEN;
 RDTYPE; TDTYPE; RLSBIT; and
 TLSBIT bits of the




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SPORTx_TCR1,
SPORTx_TCR2,
SPORTx_RCR1, and
SPORTx_RCR2 registers.
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146
SPORTs Multichannel Operation
 In Multichannel mode, RSCLK can either be
 provided externally or
 generated internally by the SPORT, and
 it is used for both transmit and receive
functions.
 Leave TSCLK disconnected if the SPORT is
used only in multichannel mode.
 If RSCLK is externally or internally
provided, it will be internally distributed to
both the receiver and transmitter circuitry.
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147
SPORTs Multichannel Operation

Important Note:

The SPORT Multichannel Transmit Select register and the SPORT
Multichannel Receive Select register must be programmed before
enabling SPORTx_TX or SPORTx_RX operation for Multichannel
Mode.

This is especially important in “DMA data unpacked mode,”
since SPORT FIFO operation begins immediately after RSPEN
and TSPEN are set, enabling both RX and TX.

The MCMEN bit (in SPORTx_MCMC2) must be enabled prior to
enabling SPORTx_TX or SPORTx_RX operation. When disabling
the SPORT from multichannel operation, first disable TXEN and
then disable RXEN.

Note both TXEN and RXEN must be disabled before reenabling.
Disabling only TX or RX is not allowed.
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SPORTs Multichannel Operation
 SPORTx_MTCSn Registers
 The Multichannel Selection registers are used to enable
and disable individual channels.

The four SPORTx Multichannel Transmit Select
registers (SPORTx_MTCSn) specify the active
transmit channels.
 There are four registers, each with 32 bits,
corresponding to the 128 channels:
 Setting a bit enables that channel so that
the serial port selects that word for
transmit from the multiple word block of
data.
 For example, setting bit 0 selects word 0,
setting bit 12 selects word 12, and so on.
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SPORTs Multichannel Operation
 Setting a particular bit in a SPORTx_MTCSn register
causes the serial port to transmit the word in that
channel’s position of the datastream.

Clearing the bit in the SPORTx_MTCSn register
causes the serial port’s data transmit pin to threestate during the time slot of that channel.
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SPORTs Multichannel Operation
 SPORTx_MRCSn Registers
 The Multichannel Selection registers are used to enable
and disable individual channels.

The SPORTx Multichannel Receive Select registers
(SPORTx_MRCSn) specify the active receive
channels.
 There are four registers, each with 32 bits,
corresponding to the 128 channels.
 Setting a bit enables that channel so that
the serial port selects that word for receive
from the multiple word block of data.
 For example, setting bit 0 selects word 0,
setting bit 12 selects word 12, and so on.
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151
SPORTx Multichannel Transmit
Select Registers
*pSPORT0_MTCS0 = 0x000000FF;
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152
SPORTx Multichannel Receive
Select Registers
*pSPORT0_MRCS0 = 0x000000FF;
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153
SPORTx_MCMCn Registers
 SPORTx_MCMCn Registers
 There are two SPORTx Multichannel Configuration
registers (SPORTx_MCMCn) for each SPORT.
 The SPORTx_MCMCn registers are used to
configure the multichannel operation of the SPORT.
The two control registers are shown below.
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SPORTx_MCMCn Registers
*pSPORT0_MCMC1 = 0x0000;
Desired Window Size = 8
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155
SPORTx_MCMCn Registers
*pSPORT0_MCMC2 = 0x101c;
0x101c = 0001 0000 0001 1100
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156
Initialize.c
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836 - DMA
SPORT0
DMA Configuration
SPORT IRS
DMA Support
Endless loop and processing Flag Interrupts
DMA Configuration
Init_DMA()
Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
Setting up DMA1-SPORT0
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
Input/Receive Channel
*pDMA1_PERIPHERAL_MAP = 0x1000;
as
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMA Channel’s Peripheral Map
Register
 Each DMA channel’s Peripheral Map register
(DMAx_PERIPHERAL_MAP) contains bits that:
 Map the channel to a specific peripheral.
 Identify whether the channel is a Peripheral
DMA channel or a Memory DMA channel.
*pDMA1_PERIPHERAL_MAP
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= 0x1000;
160
Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMA Configuration Register

The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in
Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this
slide is used to set up DMA parameters and operating modes.
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
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Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMA Start Address Register

The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR),
shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also
in the next slide, contains the start address of the data buffer currently targeted
for DMA.
*pDMA1_START_ADDR = iRxBuffer1;
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Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMA Count Register

For 1D DMA, it specifies the number of elements to read in. For 2D DMA details,
see “Two-Dimensional DMA” on page 9-45 of ADSP-BF533 Blackfin Processor
Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements.
*pDMA1_X_COUNT = 8;
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166
Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMAx Modify Register


The Inner Loop Address Increment register
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, two’s-complement
byte-address increment. In 1D DMA, this increment is the stride that is applied
after transferring each element.
Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.
*pDMA1_X_MODIFY = 4;
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Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
Setting up DMA2-SPORT0 as
Output/Transmit Channel
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMA Channel’s Peripheral Map
Register
 Each DMA channel’s Peripheral Map register
(DMAx_PERIPHERAL_MAP) contains bits that:
 Map the channel to a specific peripheral.
 Identify whether the channel is a Peripheral
DMA channel or a Memory DMA channel.
*pDMA2_PERIPHERAL_MAP
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= 0x2000;
170
Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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171
DMA Configuration Register

The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in
Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this
slide is used to set up DMA parameters and operating modes.
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
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172
Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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DMA Start Address Register

The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR),
shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also
in the next slide, contains the start address of the data buffer currently targeted
for DMA.
*pDMA2_START_ADDR = iTxBuffer1;
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174
Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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175
DMA Count Register

For 1D DMA, it specifies the number of elements to read in. For 2D DMA details,
see “Two-Dimensional DMA” on page 9-45 of ADSP-BF533 Blackfin Processor
Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements.
*pDMA2_X_COUNT = 8;
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176
Initialize.c : Init_DMA()
//--------------------------------------------------------------------------//
// Function: Init_DMA
//
//
//
// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in
//
//
autobuffer mode to transmit
//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 8;
// Inner loop address increment
*pDMA1_X_MODIFY
= 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 8;
// Inner loop address increment
*pDMA2_X_MODIFY
= 4;
}
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177
Initialize.c
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836 - DMA
SPORT0
DMA Configuration
SPORT IRS
Enable DMA Support
Endless loop and processing Flag Interrupts
DMA Configuration
Init_DMA()
DMAx Modify Register


The Inner Loop Address Increment register
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, two’s-complement
byte-address increment. In 1D DMA, this increment is the stride that is applied
after transferring each element.
Note X_MODIFY is specified in bytes, regardless of the DMA transfer size.
*pDMA2_X_MODIFY = 4;
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180
Initialize.c :
Enable_DMA_Sport()
//--------------------------------------------------------------------------//
// Function:
Enable_DMA_Sport
//
//
//
// Description:
Enable DMA1, DMA2, Sport0 TX and Sport0 RX
//
//--------------------------------------------------------------------------//
void Enable_DMA_Sport0(void)
{
// enable DMAs
*pDMA2_CONFIG = (*pDMA2_CONFIG | DMAEN);
*pDMA1_CONFIG = (*pDMA1_CONFIG | DMAEN);
// enable Sport0 TX and RX
*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);
*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);
}
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DMA Configuration Register
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
*pDMA2_CONFIG = *pDMA2_CONFIG | DMAEN
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
*pDMA1_CONFIG = *pDMA1_CONFIG | DMAEN;
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SPORTX Transmit Configuration
1 Register: SPORTx_TCR1
*pSPORT0_TCR1 = TFSR;
TFSR = 0x0000;
*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);
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SPORTx Receive Configuration
1 Register : SPORTx_RCR1
*pSPORT0_RCR1 = RFSR;
RFSR = 0x0000;
*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);
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184
Initialize.c
1.
2.
3.
4.
5.
6.
7.
8.
9.
EBIU setup
Flash setup
FIO setup
ADI1836 - DMA
SPORT0
DMA Configuration
SPORT IRS
Enable DMA Support
Endless loop and processing Flag Interrupts
Event Controller for
Interrupts and Exceptions
Event Controller
 The Event Controller of the processor
manages five types of activities or
events:





Emulation
Reset
Nonmaskable interrupts (NMI)
Exceptions
Interrupts (11)
 Note the word event describes all five types of
activities. The Event Controller manages
fifteen different events in all: Emulation,
Reset, NMI, Exception, and eleven Interrupts.
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187
Event Controller
 An interrupt is an event that changes
normal processor instruction flow and
is asynchronous to program flow.
 In contrast, an exception is a software
initiated event whose effects are
synchronous to program flow.
 The event system is nested and
prioritized. Consequently, several
service routines may be active at any
time, and a low priority event may be
pre-empted by one of higher priority.
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188
Event Controller

The processor employs a two-level event control
mechanism.



The SIC provides mapping between the many peripheral
interrupt sources and the prioritized general-purpose
interrupt inputs of the core.


The processor System Interrupt Controller (SIC) works with
The Core Event Controller (CEC) to prioritize and control all system
interrupts.
This mapping is programmable, and individual interrupt sources can be
masked in the SIC.
The CEC supports nine (9) general-purpose interrupts (IVG7
– IVG15) in addition to the dedicated interrupt and
exception events that are described in Table 4-6.

It is recommended that the



two lowest priority interrupts (IVG14 and IVG15) be reserved for
software interrupt handlers, leaving
seven prioritized interrupt inputs (IVG7 – IVG13) to support the system.
Refer to Table 4-6 for details.
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189
Core Event Mapping
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190
System Event Mapping
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191
Processor Event Controller
 Processor Event Controller
Consists of 2 stages:
 The Core Event Controller (CEC)
 System Interrupt Controller (SIC)
 Conceptually:
 Interrupts from the peripherals arrive at
SIC
 SIC routes interrupts directly to generalpurpose interrupts of the CEC.
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Core Event Controller (CEC)
 CEC supports
 9 general-purpose interrupts: IVG15-7
 IVG15-14 – (2) lowest priority interrupts
for software handlers.
 IRVG13-7 – (7) highest to support
peripherals.
 Additional dedicated interrupt and
exception events.
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System Interrupt Controller
(SIC)
 SIC provides mapping and routing
of events:
 From: Peripheral interrupt sources
 To: Prioritized general-purpose interrupt
inputs of the CEC.
 Note: Processor default mapping
can be altered by the user via
Interrupt Assignment Register
(IAR).
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BF533 System & Core Interrupt
Controllers
PLL Wakeup interrupt
IVG #
1
Event Source
IVG7
Core Event
Name
IVG #
Emulator
0
EMU
DMA error (generic)
IVG7
PPI error interrupt
IVG7
Reset
1
RST
SPORT0 error interrupt
IVG7
Non Maskable Interrupt
2
NMI
SPORT1 error interrupt
IVG7
Exceptions
3
EVSW
SPI error interrupt
IVG7
UART error interrupt
IVG7
Reserved
4
-
RTC interrupt
IVG8
Hardware Error
5
IVHW
DMA 0 interrupt (PPI)
IVG8
Core Timer
6
IVTMR
DMA 1 interrupt (SPORT0 RX)
IVG9
General Purpose 7
7
IVG7
DMA 2 interrupt (SPORT0 TX)
IVG9
DMA 3 interrupt (SPORT1 RX)
IVG9
General Purpose 8
8
IVG8
DMA 4 interrupt (SPORT1 TX)
IVG9
General Purpose 9
9
IVG9
DMA 5 interrupt (SPI)
IVG10
DMA 6 interrupt (UART RX)
IVG10
DMA 7 interrupt (UART TX)
IVG10
Timer0 interrupt
IVG11
Timer1 interrupt
IVG11
Timer2 interrupt
IVG11
PF interrupt A
IVG12
PF interrupt B
IVG12
DMA 8/9 interrupt (MemDMA0)
IVG13
DMA 10/11 interrupt (MemDMA1)
IVG13
Watchdog Timer Interrupt
IVG13
14 March 2016
General Purpose 10
10
IVG10
General Purpose 11
11
IVG11
General Purpose 12
12
IVG12
General Purpose 13
13
IVG13
General Purpose 14
14
IVG14
General Purpose 15
15
IVG15
Highest
Priority
System Interrupt Source
Lowest
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System Interrupt Processing

Referring to Figure 4-5, note when an interrupt (Interrupt
A) is generated by an interrupt-enabled peripheral:
1.
SIC_ISR logs the request and keeps track of system
interrupts that are asserted but not yet serviced (that is, an
interrupt service routine hasn’t yet cleared the interrupt).
2.
SIC_IWR checks to see if it should wake up the core from
an idled state based on this interrupt request.
3.
SIC_IMASK masks off or enables interrupts from
peripherals at the system level. If Interrupt A is not
masked, the request proceeds to Step 4.
4.
The SIC_IARx registers, which map the peripheral
interrupts to a smaller set of general-purpose core
interrupts (IVG7 – IVG15), determine the core priority of
Interrupt A.
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System Interrupt Processing
(cont.)
5.
ILAT adds Interrupt A to its log of interrupts latched by the core
but not yet actively being serviced.
6.
IMASK masks off or enables events of different core priorities. If
the IVGx event corresponding to Interrupt A is not masked, the
process proceeds to Step 7.
7.
The Event Vector Table (EVT) is accessed to look up the
appropriate vector for Interrupt A’s interrupt service routine (ISR).
8.
When the event vector for Interrupt A has entered the core
pipeline, the appropriate IPEND bit is set, which clears the
respective ILAT bit. Thus, IPEND tracks all pending interrupts, as
well as those being presently serviced.
9.
When the interrupt service routine (ISR) for Interrupt A has been
executed, the RTI instruction clears the appropriate IPEND bit.
However, the relevant SIC_ISR bit is not cleared unless the
interrupt service routine clears the mechanism that generated
Interrupt A, or if the process of servicing the interrupt clears this
bit.
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Interrupt Processing Block
Diagram
It should
beEvent
noted
that
emulation,
reset,
NMI,
and
exception
8.
When
the
event
vector
for
Interrupt
A
has
entered
9.
the
interrupt
service
routine
(ISR)
for
Interrupt
A
7.
The
Vector
Table
(EVT)
iskeeps
accessed
to
look
upthe
the
5.
ILAT
adds
Interrupt
A
to
its
log
of
interrupts
latched
by
6.
IMASK
masks
off
or
enables
events
of
different
core
4.
The
SIC_IARx
registers,
map
the
peripheral
1.
SIC_ISR
logs
the
request
and
track
of
system
3. When
SIC_IMASK
masks
off
or
enables
interrupts
from
2.
SIC_IWR
checks
to
see
ifwhich
it
should
wake
up
the
core
core
pipeline,
the
appropriate
IPEND
bit
is
set,
which
has
been
executed,
the
RTI
instruction
clears
the
appropriate
vector
for
Interrupt
A’s
interrupt
service
the
core
but
not
yet
actively
being
serviced.
priorities.
If
the
IVGx
event
to
A
events,
as
hardware
error
(IVHW)
core
timer
toas
astate
smaller
set
ofcorresponding
general-purpose
core
interrupts
that
are
asserted
but
not
yetand
serviced
(that is,
peripherals
at
the
system
level.
Ifinterrupt
Interrupt
AInterrupt
is
not
from
anwell
idled
based
on
this
request.
clears
the
respective
ILAT
bit.
Thus,
IPEND
tracks
all
appropriate
IPEND
bit.
However,
the
relevant
SIC_ISR
routine
(ISR).
is
not
masked,
the
process
proceeds
to
Step
7.
interrupts
(IVG7
–
IVG15),
determine
the
core
priority
an
interrupt
routine
hasn’t
yet cleared
the
masked,
theservice
request
proceeds
to Step
4.
(IVTMR)
interrupt
requests,
enter
the
interrupt
processing
pending
as well
those being
presently
bit
is not interrupts,
cleared
unless
the as
interrupt
service
routine
of
Interrupt
A.
interrupt).
chain
at the
level andthat
aregenerated
not affected
by the systemserviced.
clears
theILAT
mechanism
Interrupt
A, or if
level
interrupt
registers
(SIC_IWR,
SIC_ISR,
SIC_IMASK,
the process of servicing the interrupt clears this bit.
SIC_IARx).
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Interrupt Service Routine
 ISR address is stored in the Event Vector Table
 Used as the next fetch address when the event
occurs
 Program Counter (PC) address is saved to a
register
 RETI, RETX, RETN, RETE, based on event
 ISR always concludes with “Return” Instruction
 RTI, RTX, RTN, RTE (respectively)
 When executed, PC is loaded with address stored in
RETI, RETX, RETN, or RETE to continue app code
 Optional nesting of higher-priority interrupts
possible
 See app. note EE-192, which covers writing interrupt
routines in C (http://www.analog.com/ee-notes)
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System Peripheral Interrupts
 The processor system has numerous
peripherals, which therefore require
many supporting interrupts. Table 4-7
lists:
 The Peripheral Interrupt source
 The Peripheral Interrupt ID used in the System
Interrupt Assignment registers (SIC_IARx). See
“System Interrupt Assignment Registers
(SIC_IARx)” on page 4-30 of BF533 HRM.
 The general-purpose interrupt of the core to
which the interrupt maps at reset
 The Core Interrupt ID used in the System
Interrupt Assignment registers (SIC_IARx). See
“System Interrupt Assignment Registers
(SIC_IARx)” on page 4-30 of BF533 HRM.
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200
Peripheral Interrupt Source at
Reset State
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Peripheral Interrupt Source at
Reset State
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Initialization of Interrupts
 If the default assignments shown in
Table 4-7 are acceptable, then
interrupt initialization involves only:
1. Initialization of the core Event Vector Table
(EVT) vector address entries. Why is this
needed?
2. Initialization of the IMASK register
3. Unmasking the specific peripheral interrupts in
SIC_IMASK that the system requires
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Initialization of Core Vector
Table

The Event Vector Table (EVT) is a hardware table with sixteen
entries that are each 32 bits wide.

The EVT contains an entry for each possible core event. Entries are
accessed as MMRs, and each entry can be programmed at reset with
the corresponding vector address for the interrupt service routine.

When an event occurs, instruction fetch starts at the address
location in the EVT entry for that event. The processor architecture
allows unique addresses to be programmed into each of the
interrupt vectors; that is, interrupt vectors are not determined by a
fixed offset from an interrupt vector table base address.


This approach minimizes latency by not requiring a long jump from the vector
table to the actual ISR code.
Table 4-9 lists events by priority. Each event has a corresponding
bit in the event state registers:



ILAT,
IMASK, and
IPEND.
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Core Event Vector Table
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Core Event Vector Table
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SPORT Interrupts
Initialization
Init_Sport_Interrupts()
Initialize.c :
Init_Sport_Interrupts()
//--------------------------------------------------------------------------//
// Function:
Init_Interrupts
//
//
//
// Description:
Initialize Interrupt for Sport0 RX
//
//--------------------------------------------------------------------------//
void Init_Sport_Interrupts(void)
{
// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffff2f;
*pSIC_IAR2 = 0xffffffff;
// assign ISRs to interrupt vectors
// Sport0 RX ISR -> IVG 9
register_handler(ik_ivg9, Sport0_RX_ISR);
// enable Sport0 RX interrupt
*pSIC_IMASK = 0x00000200;
ssync();
}
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System Interrupt Assignment
Registers (SIC_IARx)
 The relative priority of peripheral interrupts can
be set by mapping the peripheral interrupt to
the appropriate general-purpose interrupt level
in the core.
 The mapping is controlled by the System
Interrupt Assignment register settings, as
detailed in Figure 4-9, Figure 4-10, and Figure 411.
 If more than one interrupt source is mapped to
the same interrupt, they are logically OR-ed,
with no hardware prioritization. Software can
prioritize the interrupt processing as required
for a particular system application.
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Mapping of Values in SIC_IARx
Register to General Purpose
Interrupt

Table 4-8 defines the
value to write in SIC_IARx
to configure a peripheral
for a particular IVG
priority.
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System Interrupt Assignment
Register
*pSIC_IAR0 = 0xffffffff;
0xffffffff = 1111 1111 1111 1111
1111 1111 1111 1111
All Corresponding Interrupts in
this register are set to lowest priority
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System Interrupt Assignment
Register
*pSIC_IAR1 = 0xffffff2f;
0xffffff2f = 1111 1111 1111 1111
1111 1111 0010 1111
DMA1 (SPORT0 RX)
is set to “2” priority
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System Interrupt Assignment
Register
*pSIC_IAR2 = 0xffffffff;
0xffffffff = 1111 1111 1111 1111
1111 1111 1111 1111
Do not forget to set appropriate
Interrupt Priority Values for PF A
interrupts.
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Initialize.c :
Init_Sport_Interrupts()
//--------------------------------------------------------------------------//
// Function:
Init_Interrupts
//
//
//
// Description:
Initialize Interrupt for Sport0 RX
//
//--------------------------------------------------------------------------//
void Init_Sport_Interrupts(void)
{
// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffff2f;
*pSIC_IAR2 = 0xffffffff;
// assign ISRs to interrupt vectors
// Sport0 RX ISR -> IVG 9
register_handler(ik_ivg9, Sport0_RX_ISR);
// enable Sport0 RX interrupt
*pSIC_IMASK = 0x00000200;
ssync();
}
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Interrupt Handler Support

The Blackfin C/C++ compiler provides support for interrupts and other
events used by the Blackfin processor architecture (see Table 1-25 of
VisualDSP++ 4.5 C/C++ Compiler and Library Manual for Blackfin
Processors).

The Blackfin system has several different classes of events, not all of
which are supported by the ccblkfn compiler. Handlers for these events
are called Interrupt Service Routines (ISRs).

The compiler provides facilities for defining an ISR function, registering
it as an event handler, and for obtaining the saved processor context.
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Defining an ISR
 To define a function as an ISR, the sys/exception.h
header must be included and the function must be declared
and defined using macros defined within this header file.

Where is this file included in the LED Lab #1 example?
 There is a macro for each of the three kinds of events the
compiler supports:



EX_INTERRUPT_HANDLER
EX_EXCEPTION_HANDLER
EX_NMI_HANDLER

Which macro was used in Lab #1 exercise?
 By default, the ISRs generated by the compiler are not reentrant; they disable the interrupt system on entry, and reenable it on exit. You may also define ISRs for interrupts
which are re-entrant, and which re-enable the interrupt
system soon after entering the ISR.
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Example
#include <sys/exception.h>
static int number_of_interrupts;
EX_INTERRUPT_HANDLER(my_isr)
{
number_of_interrupts++;
}

This example declares and defines my_isr() as a handler
for interrupt-type events.

The macro used for defining the ISR is also suitable for
declaring it as a prototype:


EX_INTERRUPT_HANDLER(my_isr);
Example:
Talkthrough.h: EX_INTERRUPT_HANDLER(Sport0_RX_ISR);
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Registering an ISR


ISRs, once defined, can be registered in the Event Vector
Table (EVT) using the register_handler_ex() function or the
register_handler() function, both of which also update the
IMASK register so that interrupt can take effect.
Only the register_handler_ex() function will be discussed
here, as it is an extended version of the register_handler()
function. Refer to “register_handler_ex” on page 3-236 of
VisualDSP++ 4.5 C/C++ Compiler and Library Manual for
Blackfin Processors for more information about it.

The register_handler_ex() function takes three parameters,
defining



the event,
the ISR, and
whether the interrupt should be enabled, disabled, or left in its current
state.
It also returns the previously registered ISR (if any). The event is
specified using the interrupt_kind enumeration from exception.h.
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Registering an ISR
typedef enum {
ik_emulation,
ik_reset,
ik_nmi,
ik_exception,
ik_global_int_enable,
ik_hardware_err,
ik_timer,
ik_ivg7,
ik_ivg8,
ik_ivg9,
ik_ivg10,
ik_ivg11,
ik_ivg12,
ik_ivg13,
ik_ivg14,
ik_ivg15
} interrupt_kind;
ex_handler_fn register_handler_ex(interrupt_kind kind,
ex_handler_fn fn, int enable);

Which enumeration types were used in the LAB exercise?
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register_handler

Register event handlers

Synopsis
#include <sys/exception.h>
ex_handler_fn register_handler (interrupt_kind kind, ex_handler_fn fn);

Description


The register_handler function determines how the hardware event kind is
handled. This is done by


registering the function pointed to by fn as a handler for the event and
updating the IMASK register so that interrupt can take effect.

The kind event is an enumeration identifying each of the hardware events—
interrupts and exceptions—accepted by the Blackfin processor.
Note:

The register_handler_ex function provides an extended and more functional
interface than register_handler.

For the values for interrupt_kind, refer to “Registering an ISR” on page 1-251 of

The fn must be one of the values are listed in the table in the next slide.
VisualDSP++ 4.5 C/C++ Compiler and Library Manual for Blackfin Processors presented
also in the previous slide.
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Table of fn values
 Which function value was used in the
Lab exercise?
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Initialize.c :
Init_Sport_Interrupts()
//--------------------------------------------------------------------------//
// Function:
Init_Interrupts
//
//
//
// Description:
Initialize Interrupt for Sport0 RX
//
//--------------------------------------------------------------------------//
void Init_Sport_Interrupts(void)
{
// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffff2f;
*pSIC_IAR2 = 0xffffffff;
// assign ISRs to interrupt vectors
// Sport0 RX ISR -> IVG 9
register_handler(ik_ivg9, Sport0_RX_ISR);
// enable Sport0 RX interrupt
*pSIC_IMASK = 0x00000200;
ssync();
Unmasking of the Interrupt by setting
corresponding bits in SIC_IMASK register.
}
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SIC_IMASK Register
 The System Interrupt Mask register (SIC_IMASK,
shown in Figure 4-8 Blacfin BF533 HRM) allows
masking of any peripheral interrupt source at the
System Interrupt Controller (SIC), independently of
whether it is enabled at the peripheral itself.
 A reset forces the contents of SIC_IMASK to all 0s to
mask off all peripheral interrupts. Writing a 1 to a bit
location turns off the mask and enables the interrupt.
 Although this register can be read from or written to
at any time (in Supervisor mode), it should be
configured in the reset initialization sequence before
enabling interrupts.
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SIC_IMASK Register
*pSIC_IMASK = 0x00000200;
0x00090000 = 0000 0000 0000 0001
0000 0010 0000 0000
DMA Interrupt
SPORT0 RX
Do not forget
to Unmask
Interrupt
associated
with PF
Interrupt A
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Synchronization
 Synchronization Functions
 void csync(void)
 void ssync(void)
 These two functions provide synchronization.
 The csync() function is a core-only
synchronization—it flushes the pipeline and
store buffers.
 The ssync() function is a system
synchronization, and also waits for an ACK
instruction from the system bus.
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Servicing Interrupts
SPORT0_ISR
SPORT0_ISR
//--------------------------------------------------------------------------//
// Function:
Sport0_RX_ISR
//
//
//
// Description: This ISR is executed after a complete frame of input data
//
//
has been received. The new samples are stored in
//
//
iChannel0LeftIn, iChannel0RightIn, iChannel1LeftIn and
//
//
iChannel1RightIn respectively. Then the function
//
//
Process_Data() is called in which user code can be executed.
//
//
After that the processed values are copied from the
//
//
variables iChannel0LeftOut, iChannel0RightOut,
//
//
iChannel1LeftOut and iChannel1RightOut into the dma
//
//
transmit buffer.
//
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(Sport0_RX_ISR)
{
// confirm interrupt handling
*pDMA1_IRQ_STATUS = 0x0001;
// copy input data from dma input buffer into variables
iChannel0LeftIn = iRxBuffer1[INTERNAL_ADC_L0];
iChannel0RightIn = iRxBuffer1[INTERNAL_ADC_R0];
iChannel1LeftIn = iRxBuffer1[INTERNAL_ADC_L1];
iChannel1RightIn = iRxBuffer1[INTERNAL_ADC_R1];
// call function that contains user code
Process_Data();
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DMA Interrupt Status Registers
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DMAx_IRQ_STATUS/MDMA_yy_
IRQ_STATUS Register


DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS Register
The Interrupt Status register
(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS), shown in Figure 913, contains bits that record whether the DMA channel:






Is enabled and operating, enabled but stopped, or disabled.
Is fetching data or a DMA descriptor.
Has detected that a global DMA interrupt or a channel interrupt
is being asserted.
Has logged occurrence of a DMA error.
Note the DMA_DONE interrupt is asserted when the last
memory access (read or write) has completed.
Note: For a memory transfer to a peripheral, there may be up to
four data words in the channel’s DMA FIFO when the interrupt
occurs. At this point, it is normal to immediately start the next
work unit. If, however, the application needs to know when the
final data item is actually transferred to the peripheral, the
application can test or poll the DMA_RUN bit. As long as there is
undelivered transmit data in the FIFO, the DMA_RUN bit is 1.
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DMAx_IRQ_STATUS Register
*pDMA1_IRQ_STATUS = 0x0001;
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SPORT0_ISR
//--------------------------------------------------------------------------//
// Function:
Sport0_RX_ISR
//
//
//
// Description: This ISR is executed after a complete frame of input data
//
//
has been received. The new samples are stored in
//
//
iChannel0LeftIn, iChannel0RightIn, iChannel1LeftIn and
//
//
iChannel1RightIn respectively. Then the function
//
//
Process_Data() is called in which user code can be executed.
//
//
After that the processed values are copied from the
//
//
variables iChannel0LeftOut, iChannel0RightOut,
//
//
iChannel1LeftOut and iChannel1RightOut into the dma
//
//
transmit buffer.
//
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(Sport0_RX_ISR)
{
// confirm interrupt handling
*pDMA1_IRQ_STATUS = 0x0001;
// copy input data from dma input buffer into variables
iChannel0LeftIn = iRxBuffer1[INTERNAL_ADC_L0];
iChannel0RightIn = iRxBuffer1[INTERNAL_ADC_R0];
iChannel1LeftIn = iRxBuffer1[INTERNAL_ADC_L1];
iChannel1RightIn = iRxBuffer1[INTERNAL_ADC_R1];
// call function that contains user code
Process_Data();
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SPORT0_ISR
// copy processed data from variables into dma output buffer
iTxBuffer1[INTERNAL_DAC_L0] = iChannel0LeftOut;
iTxBuffer1[INTERNAL_DAC_R0] = iChannel0RightOut;
iTxBuffer1[INTERNAL_DAC_L1] = iChannel1LeftOut;
iTxBuffer1[INTERNAL_DAC_L2] = iChannel1LeftOut;
iTxBuffer1[INTERNAL_DAC_R1] = iChannel1RightOut;
iTxBuffer1[INTERNAL_DAC_R2] = iChannel1RightOut;
}
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Processing Input Audio
Data
Process_data()
Process_data()
#include "Talkthrough.h"
#include <btc.h>
//-------------------------------------------------------------------------------------//
// Function:
Process_Data()
//
//
//
// Description: This function is called from inside the SPORT0 ISR every //
//
time a complete audio frame has been received. The new
//
//
input samples can be found in the variables iChannel0LeftIn,
//
//
iChannel0RightIn, iChannel1LeftIn and iChannel1RightIn
//
//
respectively. The processed data should be stored in
//
//
iChannel0LeftOut, iChannel0RightOut, iChannel1LeftOut,
//
//
iChannel1RightOut, iChannel2LeftOut and iChannel2RightOut
//
//
respectively.
//
//-------------------------------------------------------------------------------------//
void Process_Data(void)
{
iChannel1LeftOut = iChannel1LeftIn;
iChannel1RightOut = iChannel1RightIn;
//write data to BTC channel
int nValue;
extern int BTCLeftVolume;
extern int BTCRightVolume;
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Process_data()
nValue = (iChannel0LeftIn >> 8);
//upper 24-bits
nValue = (nValue >> BTCLeftVolume);
//volume
btc_write_value(0, (unsigned int*)&nValue, sizeof(nValue));
iChannel0LeftOut = (nValue << 8);
nValue = (iChannel0RightIn >> 8);
//upper 24-bits
nValue = (nValue >> BTCRightVolume); //volume
btc_write_value(1, (unsigned int*)&nValue, sizeof(nValue));
iChannel0RightOut = (nValue << 8);
}
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Init_Sport0
//--------------------------------------------------------------------------//
// Function:
Init_Sport0
//
//
//
// Description: Configure Sport0 for TDM mode, to transmit/receive data
//
//
to/from the AD1836. Configure Sport for external clocks and
//
//
frame syncs.
//
//--------------------------------------------------------------------------//
void Init_Sport0(void)
{
// Sport0 receive configuration
// External CLK, External Frame sync, MSB first
// 32-bit data
*pSPORT0_RCR1 = RFSR;
*pSPORT0_RCR2 = SLEN_32;
// Sport0 transmit configuration
// External CLK, External Frame sync, MSB first
// 24-bit data
*pSPORT0_TCR1 = TFSR;
*pSPORT0_TCR2 = SLEN_32;
// Enable MCM 8 transmit & receive channels
*pSPORT0_MTCS0 = 0x000000FF;
*pSPORT0_MRCS0 = 0x000000FF;
// Set MCM configuration register and enable MCM mode
*pSPORT0_MCMC1 = 0x0000;
*pSPORT0_MCMC2 = 0x101c;
}
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SPORTx_RCR1 and
SPORTx_RCR2 Registers

The main control registers for the receive portion of each SPORT
are the Receive Configuration registers:


SPORTx_RCR1 and
SPORTx_RCR2.

A SPORT is enabled for receive if Bit 0 (RSPEN) of the Receive
Configuration 1 register is set to 1. This bit is cleared during either
a hard reset or a soft reset, disabling all SPORT reception.

When the SPORT is enabled to receive (RSPEN set), corresponding
SPORT Configuration register writes are not allowed except for
SPORTx_RCLKDIV and Multichannel Mode Channel Select registers.

Writes to disallowed registers have no effect. While the SPORT
is enabled,`SPORTx_RCR1 is not written except for bit 0
(RSPEN). For example:
write (SPORTx_RCR1, 0x0001) ; /* SPORT RX Enabled */
write (SPORTx_RCR1, 0xFF01) ; /* ignored, no effect */
write (SPORTx_RCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_RCR1
still equal to 0x0000 */
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SPORTx Receive Configuration
1 Register
*pSPORT0_RCR1 = RFSR;
RFSR = 0x000;
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SPORTx Receive Configuration
2 Register
*pSPORT0_RCR2 = SLEN_32;
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SPORTx_RCR1 and SPORTxRCR2
Registers

Additional information for the SPORTx_RCR1 and SPORTxRCR2
Receive Configuration register bits:

Receive Enable (RSPEN). This bit selects whether the SPORT is



Setting the RSPEN bit turns on the SPORT and




causes it to sample data from the data receive pins as well as
the receive bit clock and
Receive Frame Sync pins if so programmed.
Setting RSPEN enables the SPORTx receiver, which can generate a
SPORTx RX interrupt.



enabled to receive (if set) or
disabled (if cleared).
For this reason, the code should initialize the ISR and the DMA
control registers, and should be ready to service RX interrupts
before setting RSPEN.
Setting RSPEN also generates DMA requests if DMA is enabled
and data is received.
Set all DMA control registers before setting RSPEN.
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SPORTx_RCR1 and SPORTxRCR2
Registers

Clearing RSPEN causes the SPORT to



stop receiving data;
it also shuts down the internal SPORT receive circuitry.
In low power applications, battery life can be extended by clearing
RSPEN whenever the SPORT is not in use.
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SPORTx_TCR1 and
SPORTx_TCR2 Registers




The main control registers for the transmit portion of each SPORT
are the Transmit Configuration registers, SPORTx_TCR1 and
SPORTx_TCR2.
A SPORT is enabled for transmit if Bit 0 (TSPEN) of the Transmit
Configuration 1 register is set to 1.
This bit is cleared during either a hard reset or a soft reset,
disabling all SPORT transmission.
When the SPORT is enabled to transmit (TSPEN set),
corresponding SPORT Configuration register writes are not allowed
except for SPORTx_TCLKDIV and Multichannel Mode Channel
Select registers.

Writes to disallowed registers have no effect. While the SPORT
is enabled, SPORTx_TCR1 is not written except for bit 0
(TSPEN). For example:
write (SPORTx_TCR1, 0x0001) ; /* SPORT TX Enabled */
write (SPORTx_TCR1, 0xFF01) ; /* ignored, no effect */
write (SPORTx_TCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_TCR1
still equal to 0x0000 */
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SPORTX Transmit Configuration
1 Register: SPORTx_TCR1
*pSPORT0_TCR1 = TFSR;
TFSR = 0x000;
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SPORTX Transmit Configuration
2 Register: SPORTx_TCR2
*pSPORT0_TCR2 = SLEN_32;
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SPORTs Multichannel Operation
 SPORTx_MTCSn Registers
 The Multichannel Selection registers are used to
enable and disable individual channels. The four
SPORTx Multichannel Transmit Select registers
(SPORTx_MTCSn) specify the active transmit
channels.
 There are four registers, each with 32 bits,
corresponding to the 128 channels.
 Setting a bit enables that channel so that the
serial port selects that word for transmit from
the multiple word block of data.
 For example, setting bit 0 selects word 0,
setting bit 12 selects word 12, and so on.
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SPORTs Multichannel Operation
 Setting a particular bit in a SPORTx_MTCSn register
causes the serial port to transmit the word in that
channel’s position of the datastream. Clearing the bit in
the SPORTx_MTCSn register causes the serial port’s data
transmit pin to three-state during the time slot of that
channel.
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SPORT Multichannel
Registers
 SPORTx_MRCSn Registers
 The Multichannel Selection registers are used to
enable and disable individual channels. The SPORTx
Multichannel Receive Select registers
(SPORTx_MRCSn) specify the active receive channels.
 There are four registers, each with 32 bits,
corresponding to the 128 channels.
 Setting a bit enables that channel so that the
serial port selects that word for receive from
the multiple word block of data.
 For example, setting bit 0 selects word 0,
setting bit 12 selects word 12, and so on.
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SPORTx Multichannel Transmit
Select Registers
*pSPORT0_MTCS0 = 0x000000FF;
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SPORTx Multichannel Receive
Select Registers
*pSPORT0_MRCS0 = 0x000000FF;
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main.c
#include "Talkthrough.h"
#include "sysreg.h"
#include "ccblkfn.h"
#include <btc.h>
//--------------------------------------------------------------------------//
// Variables
//
//
// Description: The variables iChannelxLeftIn and iChannelxRightIn contain //
//
the data coming from the codec AD1836. The (processed)
//
//
playback data are written into the variables
//
//
iChannelxLeftOut and iChannelxRightOut respectively, which
//
//
are then sent back to the codec in the SPORT0 ISR.
//
The values in the array iCodec1836TxRegs can be modified to
//
//
set up the codec in different configurations according to
//
//
the AD1885 data sheet.
//
//--------------------------------------------------------------------------//
// left input data from ad1836
int iChannel0LeftIn, iChannel1LeftIn;
// right input data from ad1836
int iChannel0RightIn, iChannel1RightIn;
// left ouput data for ad1836
int iChannel0LeftOut, iChannel1LeftOut;
// right ouput data for ad1836
int iChannel0RightOut, iChannel1RightOut;
//
//
// SPORT0 DMA transmit buffer
volatile int iTxBuffer1[8];
// SPORT0 DMA receive buffer
volatile int iRxBuffer1[8];
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Processing Input Audio
Data
Process_data()
Process_data()
#include "Talkthrough.h"
#include <btc.h>
//-------------------------------------------------------------------------------------//
// Function: Process_Data()
//
//
// Description: This function is called from inside the SPORT0 ISR every
//
//
time a complete audio frame has been received. The new
//
input samples can be found in the variables iChannel0LeftIn,
//
//
iChannel0RightIn, iChannel1LeftIn and iChannel1RightIn
//
respectively. The processed data should be stored in
//
//
iChannel0LeftOut, iChannel0RightOut, iChannel1LeftOut,
//
//
iChannel1RightOut, iChannel2LeftOut and iChannel2RightOut
//
//
respectively.
//-------------------------------------------------------------------------------------//
void Process_Data(void)
{
iChannel0LeftOut = iChannel0LeftIn;
iChannel0RightOut = iChannel0RightIn;
//
//
//
//
iChannel1LeftOut = iChannel1LeftIn;
iChannel1RightOut = iChannel1RightIn;
//write data to BTC channel
int nValue;
extern int BTCLeftVolume;
extern int BTCRightVolume;
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Process_data()
nValue = (iChannel0LeftIn >> 8);
iChannel0LeftOut = (nValue << 8);
nValue = (iChannel0RightIn >> 8);
iChannel0RightOut = (nValue << 8);
//upper 24-bits
//upper 24-bits
}
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