Explanation
Interrupts
System Interconnections
Interrupts
A computer system must provide a method for allowing
mechanisms to interrupt the normal processing.
Interrupts improve processor efficiency
Most external devices are much slower than the processor and
‘busy waiting’ takes up too many resources.
Examples:
External interrupts:
Timing device, Circuit monitoring the power supply, I/O device
requesting data or completed data transfer etc. Timeout errors.
Internal interrupts (caused by an exception condition).
Illegal use of an instruction or data (traps)
example: register overflow, attempt to divide by zero, invalid op code,
stack overflow etcTimer: OS system can perform operations on a regular
basis.
Software Interrupts – Special call instruction that behaves like an interrupt.
Benefits of Interrupts
No Interrupts
Interrupts -Short I/O wait.
1
4
WRITE
1
I/O Command
WRITE
I/O Command
2a
5
2
4
Interrupt Handler
2b
5
END
WRITE
WRITE
END
3a
3
3b
WRITE
WRITE
No Interrupts
1
4
5
4
2
5
3
Interrupts -Short I/O wait.
1
4
5
2a
4
2b
3a
5
3b
Interrupts -Long I/O wait. (More realistic!)
1
4
2
5
4
3
5
Short I/O – the I/O
operation is completed
within the time it takes
to execute instructions
in the program that
occur before the next
I/O command. The
processor is kept busy
the whole time.
Long I/O - The ‘next’
I/O command comes
before first I/O has
completed. Processor
still needs to wait.
Some time is saved !
An example
Busy Wait:
Consider a computer that can execute two instructions
that read the status register and check the flag in 1 µs.
Input device transfers data at an average rate of 100 bytes
per second – equivalent to one byte every 10,000 µs.
The CPU will check the flag 10,000 times between each
transfer.
Interrupt Driven:
CPU could use this time to perform other useful
processing.
Interrupt Cycle
The interrupt cycle is added to the instruction cycle.
Processor checks for interrupt indicated by an interrupt flag.
If there is NO interrupt  Fetch next instruction
If there is an interrupt:
Suspend operation of the program
Save its context
Set PC to start address of the interrupt handler
Process the interrupt
Restore the context of the original program and continue its execution.
Instruction Cycle with Interrupts
Following each execute cycle:
Check for interrupts
Handle active interrupts
Instruction Cycle with Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been
processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns to
previous interrupt
Handling Multiple Interrupts
Sequential approach – once an
interrupt handler has been
started it runs to completion
(+) Simpler
(-) Does not handle priority interrupts well
Example: Incoming data might be lost.
Nested approach – a higher priority
device can interrupt a lower
priority one.
(+) More complex
(-) Interrupts get handled in
order of priority.
Priority Interrupts
Polling
• One common branch address for all interrupts.
• Interrupt sources polled in priority sequence.
• If an interrupt signal is ‘on’, control branches to a service routine for
this source.
• (-) Time overhead to handle many interrupts can be excessive.
• The operation can be sped up with a hardware priority-interrupt unit.
Daisy-Chain Priority
• Hardware solution
• Serial connection of all devices that request interrupts.
• Device with the highest priority takes first position, 2nd highest takes
2nd position etc.
• Interrupt request line shared by all devices.
Daisy-chain Priority Interrupt
A Serial Approach
Processor data bus
VAD 2
VAD 3
VAD 1
Device 1
PI
P0
Device 2
PI
P0
Device 3
PI
Interrupt Request
Interrupt Acknowledge
P0
INT
CPU
INTACK
One stage of the daisy-chain Priority Arrangement
.
Priority In
PI
Interrupt
request
from
device
S
Q
.
Vector Address
.
PO
RF
Priority Out
R
Delay
Open-collector
inverter
From: Computer System Architecture, Morris Mano
Interrupt request
to CPU
PI
RF
PO Enable
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
Parallel Priority Interrupt
Uses a register – whose bits are set separately by the interrupt
signal from each device.
Priority established according to the position of bits in the
interrupt register.
A mask register is used to control the status of each interrupt
request. Mask bits set programmatically.
Priority encoder generates low order bits of the VAD, which is
transferred to the CPU.
Encoder sets an interrupt status flip-flop IST whenever a nonmasked interrupt occurs.
Interrupt enable flip-flop provides overall control over the
interrupt system.
Parallel Priority Interrupt Hardware
Interrupt
Register
I0
0
Printer
From: Computer System Architecture, Morris Mano
Reader
Keyboard
1
I1
2
I2
3
I3
0
1
IEN
Priority Encoder
Disk
IST
y
x
0
0
0
0
0
0
Enable
2
Interrupt to CPU
3
INTACK from CPU
Mask
Register
Priority Encoder
Circuit that implements the priority function.
Logic – if two or more inputs arrive at the same time, the input
having the highest priority will take precedence.
I0
1
Inputs
I1
I2
d
d
I3
d
Outputs
d
Y
IST
0
0
1
0
0
0
0
1
0
0
0
d
d
1
0
0
1
1
d
d
1
0
0
Boolean functions
X = I’0I’1
Y = I’0I1 + I’0I’2
1
0
1
d
1
1
1
0
IST = I0 + I1 + I2 + I3
Interrupt Cycle
The Interrupt enable flip-flop (IEN) can be set or cleared by
program instructions.
A programmer can therefore allow interrupts (clear IEN) or
disallow interrupts (set IEN)
At the end of each instruction cycle the CPU checks IEN and
IST. If either is equal to zero, control continues with the next
instruction. If both = 1, the interrupt is handled.
Interrupt micro-operations:
SPSP – 1
(Decrement stack pointer)
M[SP]  PCc
Push PC onto stack
INTACK  1
Enable interrupt acknowledge
PC VAD
Transfer vector address to PC
IEN 0
Disable further interrupts
Go to fetch next instruction
Software Routines for handling Interrupts
Software routines used to service
interrupt requests and control interrupt
hardware registers.
Each device has its own service program
reached through a jump instruction stored
at the assigned vector address.
Example:
Keyboard sets interrupt bit whilst CPU
is executing instruction at location 749.
At the end of the instruction, 750 is pushed
onto the stack, the VAD for the keyboard is
taken off the bus and placed into the PC.
Control is passed to the keyboard routine.
Once completed, PC is replaced with original
address of next instruction (750)
JMP DISK
JMP PRINTER
JMP READER
Program to service
magnetic disk.
Program to service
line printer.
JMP KEYBOARD
Program to service
character reader.
Main program
Stack
Program to service
Keyboard.
Interconnection Structures
Memory: Outputs data. Inputs read,
write, and timing signals, addresses,
and data.
I/O Module. Outputs data &
interrupt signals. Inputs control
signals, data, and addresses.
CPU: Outputs address, control
signals, and data. Inputs
instructions data, and interrupt
signals.
Bus Interconnection
Communication pathway connecting two or more devices.
Shared transmission medium - usually broadcast.
Typically 50 – 100s of separate lines divided into three functional
groups:
Data lines
• At this level ‘data’ and ‘instruction’ are synonymous.
• Width is a key determinant of performance.
(Example: 32 bit words, data bus 16 bits  2 cycles to transmit one
word).
Address lines
• Identify source or destination of data (ie address in memory)
• Width determines maximum memory capacity of system (ie 8080 has
16 bit address  64K address space). Control lines
Control lines
• Control and timing signals (read, write, ack, clock)
Bus Interconnection
–
–
–
–
Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
Sets of wires
Single Bus Problems
Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can adversely
affect performance
If aggregate data transfer approaches bus capacity
Most modern systems have at least 4 busses to solve this
problem:
Processor bus
Cache bus
Dedicated bus for accessing system cache.
Local I/O bus
High speed I/O bus for connecting performance critical peripherals
such as high-speed networks, disk storage devices.
Standard I/O bus
Connects slower peripherals such as mouse & modems etc.
Traditional ISA (with Cache)
High Performance Architecture
Elements of Bus Design
Type
Dedicated vs. Multiplexed
Dedicated by functionality ie address vs. data or dedication to a
physical subset of components.
Arbitration Method
Only one module can have control of the bus at any one time.
Centralized vs. Distributed
Timing
Synchronous vs. Asynchronous
Bus Width
Address
Data
Data Transfer Type
Read, Write, Read-modify-write, Read-after-write, Block
Bus Arbitration
Hardware arbitration
Serial arbitration – daisy chain
Parallel arbitration
Bus
arbiter 1
Bus
arbiter 2
Bus
arbiter 3
Bus
arbiter 4
Dynamic arbitration algorithms
Bus Ready
System can change the priority
of the devices during normal operation.
Time slice – fixed length time slice of
bus time offered sequentially to each
processor in round robin fashion.
Polling – address of each device in
turn placed on polling lines. A device
may activate bus busy if it is being polled.
LRU – Least recently used.
FIFO – First in first out.
Rotating Daisy-chain – dynamic
extension of the daisy chain.
Priority Encoder
2 X 4 Decoder
Hardware for parallel arbitration
Synchronous Timing
Occurrence of events on the bus coordinated by a
clock.
Bus includes a clock line.
Clock transmits alternating 1s and 0s of equal
duration.
A single 1-0 transmission = 1 clock cycle.
All events start at the beginning of a clock cycle.
Timing of Synchronous Bus Operations
Stable Address
Valid Data In
Valid Data Out
Place stable address on
the line during first clock
signal.
Once the address
stabilizes an address
enable signal is issued.
Read: Read enable
signal activated at start
of next cycle.
Memory module
recognizes address and
after 1 cycle places data
on bus.
Write is similar but
address + data is placed
on the bus early.
Timing of Asynchronous Bus Operations
Occurrence of one event follows the occurrence of a previous event.
For read – place status and address on the line.
Once stabilized, place a read signal on the bus.
Memory decodes address, and places data on the bus.
Processor sends and “ACK” – all lines can then be dropped.
Data Transfer Type
Bus supports various data transfer types
Write (Master to slave)
Read (Slave to master)
Multiplexed address/data bus
Write (Cycle 1 : Address, Cycle 2 : Data)
Read (Cycle 1 : Address, Delay, Cycle ?: Data)
Non-multiplexed address/data bus
Write (Address & Data both sent in same cycle).
Read (Address followed by data once address is stabilized)
Other types of transfer include:
Read after write
Block data transfer (Address + multiple blocks of data)