INPUT/OUTPUT ORGANIZATION:
Interrupts
CS 147
JOKO SUTOMO
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Why we need Interrupts?
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Input/output devices are slower
than memory and CPU.
Different device requires different
amount of time from CPU.
Uncertainty of when device will be
ready.
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Modes of Data Transfer
• Polling
• Wait States
• Interrupts
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Polling


Continuously checking the status
of a peripheral; e.g. read data
from an input keyboard.
Polling is relatively straightforward
in design and programming with
the sacrifice of system
performance.
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Wait States

If a device assert wait signal, the
CPU:

stays in wait states

outputting the address of I/O device

outputting value of control signal.
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Data Transfer With
Interrupt
1) When a peripheral is ready it sends an
interrupt signal the the CPU
2) The CPU stops execution of the program
3) Accepts data from peripheral
4) Returns to the interrupted program
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Types of Interrupts
There are three types of interrupts,
each with several different uses:
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External Interrupts
Internal Interrupts
Software Interrupts
Procedures for processing all types
of interrupts are almost identical
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External Interrupts



Used by CPU to interact with input/output
devices;
e.g. the CPU requests a data transfer and in
input device asserts an interrupt when it is
ready.
Improve system performance by allowing the
CPU to execute instructions.
Also used to initiate transfers.
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Internal Interrupts

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Occurs entirely within the CPU
Used to handle exception that occur
during the execution of valid
instructions; e.g:
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Divide by zero exception
Arithmetic overflow
Page faults
Invalid instruction codes
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Software Interrupts


Generated by specific interrupt
instructions in the CPU’s instruction
set.
These interrupt act like subrutine
call statements except they always
go to a specific address.
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Processing Interrupts


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These events only occur if the interrupt
is enabled.
A handler (software to service the
interrupt) is executed.
CPU returns to where it left off in the
main program.
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Classification

Maskable Interrupt
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Can be ignored by the CPU
Non-maskable Interrupt

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Cannot be disabled, always handled.
CPU responds immediately
Highest priority among interrupts
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Handler

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Handler is essentially a
subroutine.
There may be one handler
routine for each interrupt or
one unified handler routine for
all interrupts.
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Handler

(cont.)
If handler routine is interrupted part
way through:
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Save the contents of internal registers
of the CPU
Save the state information within
Control Unit
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Handler
(cont.)
To illustrate, consider this execute routine for
the LDAC instruction for the Relatively Simple
CPU
LDAC1:
LDAC2:
LDAC3:
LDAC4:
LDAC5:
DR M, PCPC+1, ARAR+1
TR  DR, DR  M, PCPC+1
AR DR, TR
DR M
AC DR
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Handler

(cont.)
When the CPU accesses the handler
routine, the following steps are
performed:
• CPU pushes the current value of the program counter
(PC) onto stack
•CPU loads the address of the handler routine into the PC.
•The handler routine then performs its tasks.
When it finished, it returns to the correct location by popping
the value of the PC off the stack

Getting the Address of the
Handler Routine
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Vectored Interrupts

Non-vectored Interrupts
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Vectored Interrupts
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Vectored interrupts supply the CPU with
information, the interrupt vector, which is
used to generate the address of the
handler routine for the interrupt.
Useful for CPUs that receive interrupt
request from several devices via the same
control line.
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Non-Vectored Interrupts

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A non-vectored interrupt uses a
handler routine at a known
address.
CPU does not need any additional
information to generate this
address and access its handler
routine.
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For Non-vectored Interrupt Request:
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An external device sends an interrupt to
the CPU by asserting its IRQ signal.
When CPU is ready, it asserts its interrupt
acknowledge signal (IACK),
The device sets IRQ low, which cause CPU
to set IACK low.
Handler routine proceeds and starts
transferring data.
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(a) Hardware and (b) timing for a nonvectored interrupt for a single device
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For Vectored Interrupt Request:
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External device sends interrupt to the CPU
by asserting its IRQ signal.
CPU inputs an interrupt vector from the
device and call an interrupt service
routine (handler)
The device sets IRQ low
Handler routine proceeds and starts
transferring data.
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(A) Hardware and (B) Timing for a Vectored Interrupt for
a Single Device
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Prioritizing Multiple Interrupts

Extension of the nonvectored interrupt
hardware

Daisy chaining

Parallel priority
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Extension of the nonvectored
Interrupt
Hardware for multiple nonvectored interrupts
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Priority of Multiple
nonvectored Interrupts

IRQn has the highest priority and IRQ0
has the lowest.
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E.g. IRQ 7 Has higher priority than IRQ 5.
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Extension of the nonvectored
Interrupt:
Implementation Issues
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This method works well when there
are only a few IRQ/IACK pairs.
Number of pins needed by CPU to
accommodate signals become
prohibitive.
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Handling Multiple Interrupt:
Daisy Chaining
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Daisy Chaining:
Implementation Issues

Advantages:
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Straightforward and easy to
implement.
Disadvantages:
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Configuration is sequential, thus may
introduces hardware delays as chain
becomes longer.
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Handling Multiple Interrupt:
Parallel Priority
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Uses priority encoder.
Unlike daisy chaining, IACK signal
simply enables a priority encoder.
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Parallel Priority
Implementing priority Interrutps in parallel
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Parallel Priority
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Advantage:
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All interrupt requests require the same
amount of time.
Priority of the device does not determine the
time needed to acknowledge the interrupt.
Disadvantage:
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The system is much more difficult to expand
than the daisy chain configuration.
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Thank You
Joko Sutomo
CS 147
Prof. Sin-Min Lee
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