EE249 Project:
High-Level Power Estimation
in Metropolis
Mentor:
John Moondanos,
GSRC Visiting Fellow, UC Berkeley
&
Strategic CAD Labs Intel Corp.
DUSD(Labs)
Problem Description: POWER estimation
 Main Concern during the Design Cycle
 Power Consumption is the critical element
 Many stringent power requirements
 Challenging Problem

Need fast estimation methods at the high level

We shouldn’t have to go all the way down to the gate-level of every
implementation
 Much of the technology for low level power estimation exists either
in university research or in CAD vendors.
 This is not the case in high-level design.
2
Goal of the Project
Briefly Review the literature to capture the state of the art

Refer to the end of this presentation for relevant papers
Develop technologies and methodologies for solving the
power estimation problem within the Metropolis
environment

Methodologies will focus more on the system modeling
methodology that is better suited for the capabilities of Metropolis

Technologies will focus more on the algorithms that must be used
for power estimation using the capabilities of the Metropolis
environment.
3
Goal of the Project (cont.)
Sample solution approaches:

At the system level show how Metropolis could be used to
provide a power budget distribution identifying the major power
consumers.

Relative accuracy in the estimation at this level is much more
important than absolute accuracy.

Identify Power bottlenecks.
4
Suggestion for Design Driver for this Project
For the hardware: The PXA800F cell phone processor from
Intel

Some publicly available introductory material on the PXA800F is
available in the “backup material section”

Modeling of the Xscale can happen with the GnuPro simulator
For the Software: We have available Statistical Models for
typical applications that run on the PXA800F
5
Backup Material
Overview of the PXA800F cellular phone Processor
References
6
The Intel® PXA800F Cellular Processor
Full GSM/GPRS Class solution
 High-performance/Low-power Intel® XScale ™
technology core, providing class-leading
headroom for rich data applications
 Intel® Micro Signal Architecture
 Intel® On-Chip Flash Memory

GSM/GPRS Communications Stack, RTOS and
applications code for a single-chip mobile solution
7
The Intel® XScale ™ in the PXA800F
 High-performance, power-efficient processor supports data-intensive applications


Processor core operates at an adjustable clock frequency from 104 to 312 MHz
Instruction cache and Data cache memories
 4 MB integrated Intel On-Chip Flash memory

512 KB integrated SRAM

Memory controller supports synchronous Flash mode, page mode Flash, SRAM,
DRAM, and variable latency
 DMA controller
 Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC

Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP,
Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick,
Dallas* 1-Wire* Interface, keypad, PWM D/A, JTAG

Interfaces for Bluetooth, IrDA, GPS and digital camera peripherals

LCD Controller for up to 120 x 240 display 16-bit color or gray scale
8
Intel Micro Signal Architecture in the PXA800F
 Performs GSM/GPRS baseband signal processing


Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz
execution clock
Instruction cache and 64 KB dual-banked data SRAM
 512 KB integrated Intel On-Chip Flash for field-upgradable signal
processing firmware
 Includes microprocessor instructions such as bit manipulation
 Includes cipher and Viterbi accelerators

Multiple sleep modes and integrated power management minimize power
consumption

Interface support-digital I/Q, voice codec, auxiliary serial port for mixed-
signal analog baseband, I2S audio codec interface, RF synthesizer serial
control interface, JTAG
9
The Memory Subsystem
The Intel® XScale ™

Instruction and Data Cache

4MB of Flash & 512KB of SRAM always at 104MHz

Memory Controller managing accesses to external SRAM
The MSA

Integrated 64KB SRAM for microcontroller like instructions
•

Special instructions for maximizing GSM/GPRS performance
512KB of flash for program store
10
PXA800F Block Diagram
Smart Battery I/F
UARTs for
Bluetooth, IRDA
Synch Serial Port
GSM Sim card I/F
External Power
Management I/F
11
PXA800F Block Diagram
Memory Stick
Pulse Width
Modulator for
buzzer
Secure Card I/F
Programmable
Clock
Timing Control Unit
For basestation
timing
Encrypt/Decrypt
GSM data offloading
MSA
12
PXA800F Block Diagram
DSP Synchronous
Serial Ports
interfacing with RF,
speech
High Speed Logger
For debug
Full Bandwidth (HiFi) digital audio I/F
Viterbi error
decoding offloading
MSA
13
PXA800F Block Diagram
Peripheral
Bus 1
Peripheral
Bus 2
14
References
 “High-level power modeling, estimation, and optimization”,Macii, E.; Pedram, M.;
Somenzi, F., IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, Volume: 17 Issue: 11 , Nov. 1998 ,Page(s): 1061 -1079
 “High-level power estimation” ,Landman, P.; Low Power Electronics and Design,
1996., International Symposium on , 12-14 Aug. 1996, Page(s): 29 -35
 “Towards a high-level power estimation capability”, Nemani, M.; Najm, F.N.; IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Volume: 15 Issue: 6, June 1996, Page(s): 588 -598
 Integrated hardware-software co-synthesis for design of embedded systems under
power and latency constraints, A. Doboli, March 2001, Proceedings of the
conference on Design, automation and test in Europe
15
References
 A methodology for high level power estimation and exploration”,Krishna, V.;
Ranganathan, N.;, VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on ,
19-21 Feb. 1998, Page(s): 420 -425
 Probabilistic bottom-up RTL power estimation”, Ferreira, R.; Trullemans, A.-M.;
Costa, J.; Monteiro, J., Quality Electronic Design, 2000. ISQED 2000. Proceedings.
IEEE 2000 First International Symposium on , 20-22 March 2000, Page(s): 439 -446
 Power modeling for high-level power estimation”, Gupta, S.; Najm, F.N.;, Very
Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 8 Issue: 1 ,
Feb. 2000, Page(s): 18 -29
 Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Tony D. Givargis, Frank Vahid, Jörg Henkel, January 2001 Proceedings of the
conference on Asia South Pacific Design Automation Conference
16