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EGR 426 W’10
Due Date: By beginning of next lab section
Using Architecture Wizard and Chipscope Analyzer
Objectives
• To become familiar with using Architecture Wizard in Xilinx ISE 10.1i
• To become familiar with real-time debugging using Chipscope Pro Analyzer
10.1i
Part I – Using Architecture Wizard to configure a DCM component
1. Start ISE from the Start menu by selecting Start -> Programs -> Xilinx ISE Design Suite 10.1
– > ISE -> Project Navigator.
2. The next step is to create a new ISE project. Make sure you select HDL as your top-level
module.
3. In the Device Properties window, you will be selecting your Target device, Simulator tool,
Synthesis tool and Hardware language in which you will be writing your design code.
NOTE: For NEXYS board, Device is XC3S500E, Package is FG320 and Speed is -5
4. Now you will add a new VHDL module and name it as ledcount.vhd.
5. Now declare 2 input signals as “clk” and “reset” and one output bus “ledout” of width 4.
Right-click on ledcount.vhd under Sources window and select New Source. In the
New Source window, select IP (CoreGen & Architecture Wizard) and enter my_dcm as
the file name and then click Next.
The Architecture Wizard in Xilinx ISE act as intelligent assistants that facilitate easy
creation of customized instances of the various built-in complex blocks found in Xilinx
FPGAs.
6. In the Select Core Type window, expand FPGA Features and Design and then Clocking
and then under your “Device” folder, select Single DCM (Figure 1)
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Figure 1: Architecture Wizard Selection Box
7. Click Next followed by Finish to open the Xilinx Clocking Wizard – General Setup
window. In the Xilinx Clocking Wizard – General Setup window, set the following options
(as shown in Figure 2):
•
•
•
•
CLK0, CLKDV and LOCKED boxes: Checked
RST box: Unchecked
Input Clock Frequency: 50 MHz
Divide by value: 10 (To slow down the clock to 5 MHz)
Note: Based on the input frequency, the wizard also calculates output frequencies to ensure
these frequencies are within the specified range.
8. Click Next twice followed by Finish to add my_dcm.xaw file to the project.
NOTE: This source file will not be included in the design hierarchy until the component
has been instantiated into one of the HDL source files AS SHOWN IN Figure 3.
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Figure 2. Xilinx Clocking Wizard – General Setup Window
Figure 3: DCM listed in design hierarchy
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9. Select my_dcm.xaw (under Sources window) and double-click View HDL Instantiation
Template to open the instantiation template in the text editor
10.
Now you need to instantiate the DCM module in your code. In the Sources in Project
window, double-click *.vhd to open the source code in the text editor. Select my_dcm.xaw
in the Sources in Project window. In the Processes for Source window, you need to doubleclick View HDL Instantiation Template to open the instantiation template in the text editor.
11.
Copy the instantiation block into your code and save the file. Your instantiated block should
look like Figure 4.
Figure 4: Instantiated DCM block
12.
“clkout” is the output of DCM which is running at 5 MHz now (after dividing the original
clock 50 MHz by 5). Now, write the code for clock divider to slow down the clock from
5 MHz to 1Hz.
13.
Use the 1Hz clock to increment the “ledout” signal by 1 on every clock cycle.
14.
Add the .ucf file to your design and double-click on Assign Package pins under Processes
window. Assign the pins according to pin assignments given in the table below for your
board.
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Table: Pin assignments for different boards
15.
Pin Name
NEXYS
500E / 1200E
CLK
LED[0]
LED[1]
LED[2]
LED[3]
RESET
B8
J14
J15
K15
K14
G18 (Switch)
Select top-level file and double-click on Generate Programming File under Processes
window. After .bit file is generated, apply power to your board and then download the .bit
file using ADEPT tool.
16. The program then gets downloaded onto the FPGA and you will see 4 LED’s counting in
binary.
17.
Once you are done, slide the switch to OFF position to turn off the board.
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Part II – Verification of design on FPGA using Chipscope Pro Analyzer
10.1i
The objective is to verify the functioning of a simple counter implementation using ChipScope.
The counter implemented here is a 4-bit counter operating at around 1 Hz. The aim is not to
implement complex digital designs but to show the user a method to integrate ChipScope into an
existing design in order to verify its operation in a simple and efficient manner. ChipScope is a
virtual logic analyzer.
NOTE: ChipScope is not included in ISE 10.1i, but is a program available through the Xilinx
university program.
The steps are:
• Integrate the ChipScope into the counter design
• Analyze the design using ChipScope
1. Right click on the top module of the design intended for verification or debugging, and select
new source. Then select ChipScope Definition and Connection File as shown in Figure 5.
Figure 5: ChipScope Module Selection
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2. Click Next and select the hierarchy level at which the analysis is intended to be
performed and then press Next and then do Finish. The first two steps will cause a new
file (with file name as given) to be created in the source window under the project
hierarchy as shown in Figure 6.
Figure 6: ChipScope Module Location
3. Double click on this new source file which causes a new window to pop up as shown
below. Keep the default settings with Use SRLs and Use RPMs as checked. This will
enable the tool to use Shift Register LUTs instead of flip flops and multiplexers thereby
effectively reducing the size and improving the performance of the core generator.
Figure 7: SRL and RPMs
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4. Click Next and again leave the default conditions. Click Next and then select the
number of trigger ports and their respective widths depending on the design
requirement.
Triggers are those signals which initiate or trigger a certain sequence of actions
influencing certain signals under consideration.
Here, signal LEDOUT is the only trigger taken into consideration (which is four bits
wide) to represents the counter output. Therefore, Number of input trigger ports is set
to 1 and the Trigger width is set to 4 as shown in Figure 8.
Figure 8: Trigger Options
5. Now Match Type should be selected. This defines the type of trigger one wants.
For example: Basic mode, triggers depending on the specific value to which trigger is set.
Range mode, triggers depending on the range of values in which the trigger is defined.
Extended mode triggers depending on one or more occurrences of exact or range of
trigger values to which trigger is set.
A combinatorial logic (like AND/OR) or conditional logic (IF/THEN) between 2 or more
signals can also be implemented into a trigger signal.
Since LEDOUT signal has definite values, Basic mode can be chosen for the Match Type
in the present case as shown in Figure 9.
Figure 9: Match Type
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6. Now uncheck or check the Trigger Conditions Settings i.e., Enable Trigger Sequencer
and Enable Storage Qualification depending on the design requirements.
Enable Trigger Sequencer can be used to enable a 16 level trigger sequencer which aids
in configuring a multi level state machine to trigger upon a user defined traversal scheme
of match units.
Enable Storage Qualification can be used to filter data that is captured based on the user
defined conditions that can be combined with trigger events.
As the present trigger (LEDOUT signal) is a simple and straight forward trigger, so both
the boxes can be unchecked which saves little amount of logic space on the FPGA as
shown in the Figure below (LUT and FF count).
Figure 10: Trigger and Storage Settings
7. Click Next and depending on the design requirement uncheck or check the Data Same
As Trigger option.
If data is not same as trigger then define the Data Width.
The Data Depth is defined depending again on the requirements. It is recommended to
put maximum limit as it can be adjusted during the analysis phase.
Select the Rising or Falling edge of the clock signal depending on whichever edge
desired to sample the data.
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As in the present design, the output data (LEDOUT) is also used as trigger, the Data
Same As Trigger icon is checked. Since the width of counter is 4-bit, data width is
selected as 4. Rising edge is selected for clock edge for sampling data as shown below.
Figure 11: Data Options
8. Click Next and then click Modify Connections. Once Modify Connections is clicked,
the Select Net window appears. Select the appropriate signals from the list of nets and
make connections to the respective clock, trigger and data signals as shown in Figure 12.
Figure 12: Net Selections
Note: Sometimes certain nets do not show up in the list, which means that during
optimizations the tool has found that there is more than one net with same logic. As
a result it optimizes it to a single net thereby resulting in absence of few wanted nets.
This would require more detailed analysis of the design or modification of the same
to make the necessary connections for debugging.
Once all the connections are made press OK. Then press Return to Project Navigator
and Save Project changes.
9. Now re-implement the design using the Implement Design icon and then click Generate
Programming File under Processes window.
10. Once these steps are done successfully one is ready to analyze the design using the
Analyze Design Using ChipScope icon (present along with the implement design and
configure design icons in the processes window of the ISE tool). By double clicking this
icon a new window appears as shown below.
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Figure 13: ChipScope Analyzer
11. Connect power supply (obtained from instructor) to the board, change jumper JP7
from USB to WALL, connect JTAG cable (obtained from your instructor), apply power
to the board and click on the icon (top left-hand corner) to open the JTAG chain, click
on this icon and a new window appears as shown below. It shows all the devices it has
found in the JTAG chain, press OK.
Figure 14: JTAG Chain
12. Click OK to accept the list. Now right-click the FPGA device under New Project tab and
click on Configure. Select New File and assign the .bit file to the device. Click OK to
assign the selected bit file to the device.
13. Under New Project window, double-click on Trigger Setup and Waveform to show two
additional windows as shown in Figure 15. Under Trigger Setup window, click on
Value field and change the value from “XXXX” to “0110”. Set the trigger to activate
when LEDOUT becomes 0110 (indicating two outer LED’s should glow and inner two
should be off or vice-versa).
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Figure 15: Trigger and data setup
14. Now hit the play button. Keep checking the LED’s on the board when the trigger
condition occurs (two outer LED’s should glow and inner two should be off or viceversa). Once trigger condition occurs, the samples are captured on the trigger port and
displayed in the waveform as shown below.
15. Now you can change the Trigger value to something else and try it out yourself.
16. Close the Chipscope Analyzer. Go back to ISE project and double click on your *.cdc
file. Add another signal in the data port (This signal will only be used as your data and
not your trigger source). Perform all the steps again and see if you can see the newly
added signal in the waveform along with the LEDOUT signals.
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Figure 16: Waveforms
Laboratory Deliverables
• None for this laboratory assignment
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