Chapter 8.
Sequential machine
••• •••
••• •••
0 1 0
1 1 1
Input X
x1
x2
Z
Serial Adder
Combinational
circuit
M
Current state S
Next state S
M
Sequential machine M = ( I, O, S, , )
I : set of input
O : set of output
S : set of states
 (state transition) : I  S  S for i  I, s  S (i,s)  S’
 : Output function, if  : I  S  O “Mealy machine”
 : S  O “Moore machine”
••• •••
Output Z
0 0 1
Mealy machine
I
Moore machine
I
I1 I2 ••• In
S
S
S1
S2
I1 I2 ••• ••• In
S1
S2
Next state/output
Si/Oj
Si
Sn
S
1
2
3
4
Oj
Sn
Moore machine  Mealy machine
I
Output
0 1
Z
1
4
4
2
0
1
1
0
2
3
3
1
I
S

1
2
3
4
Mealy machine  Moore machine
0 1
1/0 2/1
4/0 3/1
4/0 3/1
2/1 1/0
I
S
1
2
3
4
I
0 1
1/0 2/1
4/1 3/0
4/1 1/0
2/1 3/1
S

1
2
3
4
3’
0 1
Z
1
4
4
2
4
0
1
0
1
1
2
3
1
3’
1
•State equivalence and machine minimization.
Two finite state machine m1 and m2 are equivalent iff for any state of m1, say S1, there is
some state of m2, say S2, such that starting with m1 in state s1 and m2 in state S2 and applying
say sequence of inputs, results in an identical sequence of outputs from m1 and m2. In such
case, S1 and S2 are called equivalent states.
Simplification of completely specified machines
The sets of equivalent states of a machine from a portion of the states of the machine. The
minimal machine corresponding to this machine will have a state for each equivalence class
of the original machine. The states, S1 and S2, are k-equivalent if for any input sequence of
length  k, the same output seq. is produced regardless of whether S1 and S2 were the initial
state. Two states which are not k-equivalent, are called k-distinguishable.
P1: partition imposed by grouping states whose outputs agree for any input sequence length
by 1. Compute Pi for i>1 such that two states Si and Sk are in the same block of Pi (i.e.,
are i-equivalent) iff Si and Sk are (i-1)-equivalent (i.e., in the common block of Pi-1) and
for each input, the next states of Si & Sk are (i-1)-equivalent.(i.e., are in the common block
of Pi-1)
I
S
A
B
C
D
E
0
1
A/0
A/0
A/0
A/0
A/0
B/0
C/0
D/0
E/1
E/1
Pk : partition imposed by grouping states whose outputs agree for any input
sequence length of k.
P1 : ABC , DE (Produce the same output)
P2 : AB, C , DE
P3 : A, , B, C, DE
P4 : A, , B, C , DE
, ,  , 
(transform)
We can say, D & E are equivalent state.

We can reduced state table.
I
S




I
S
A
B
C
D
E
F
0
1
/0 /0
/0 /0
/0 /0
/0 /1
0
1
E/0
F/0
E/0
F/0
C/0
B/0
D/1
D/0
B/1
B/0
F/1
C/0
 reduced machine. We can say, minimal machine.
P1 : ACE, BDF (Same outputs)
P2 : ACE, BD , F (Same outputs & same state)
P3 : AC, E, BD, F
P4 : AC , E , BD , F
, ,  , 
Simplification of incompletely specified machines
Two states, Si and Sj, a machine M are compatible iff for every input sequence applicable
to both Si and Sj, the same output sequence will be produced whenever both outputs are
specified, regardless or whether Si and Sj is the initial state. (outputs are not conflicting)
While the equivalence partition consists of disjoint blocks, the subsets of compatible may
be overlapping.
Example)
S
I1 I2 I3
1
2
3
4
5
6
3/0 – 2/–
– 4/0 6/–
5/1 – –/0
– 1/1 –
1/– – 6/–
4/– 5/– 6/–
1- compatible  (different output)
(1,3), (2,4)
2- compatible
(1,5)
3- compatible
(3,5), (4,6)
4- compatible
(1,3) (already incompatible)
Compatible pairs of states
(1,2)
(2,3)
(3,4)
(4,5)
(5,6)
(1,3) (1,4) (1,5) (1,6)
(2,4) (2,5) (2,6)
(3,5) (3,6)
(4,6)
Maximal Compatible Set
(1,2,6) (1,4)
(2,3,6) (2,5,6)
(3,4) (4,5)
Set of maximal compatible : set of compatible states (i.e., a compatibility class) which
cannot be contained in any larger compatibility class.
We can find (from maximal compatible set)
Lower bound required by the reduced machine  3 (to cover all states)
(eg – {1,2,6},{3,4},{4,5}: the min # of maximum compatibles which cover all states)
Upper bound : min (# of maximum compatible, # of original state)  6 (previous example)
Suppose & pick
(1,2,6)
a
(2,3,6)
b
c
(2,3,6)
a
(4,5) (1,2,6)
(4,5)
b
(4,5)
Require another state
 we can’t find 3 state
machine.
 try another possible
case or try find 4
state machine.
c
(1,4)
Suppose & pick
(1,2,6)  
a
b
c
(3,4) (4,5) (1,2,6)
(3,4)  
a
b
c
(4,5) (1,2,6)
(4,5)  
a
b
c
(1,2,6) (1,2,6) (1,2,6)
Reduced machine (only 3 state = lower bound)  minimum state machine
a



b
c
/0 /0 /–
/1 /1 –/0
/– /1 /–
<closed cover>
Cover : every state of the original machine must be included
Closed : For any compatibility class and any input, the next state of all states in this class,
must also be in a common compatibility class used as a state of the reduced
machine.
1- compatible
S
I1
I2
I3
I4
(A,C), (C,D), (B,F), (C,E)
A
B
C
D
E
F
C/0
F/–
–/1
A/0
–
–
A/–
B/0
–
–
E/–
B/1
–
A/–
D/0
–
B/1
F/–
Compatible pairs
(A,B) (A,E) (A,F)
(B,D) (B,E) (C,F)
(D,E) (D,F)
–
–
–
E/1
A/1
D/1
2- compatible
(A,D), (E,F)
3- compatible
(B,C), (E,F)
4- compatible
maximum
compatibility class
(A,B,E), (A,F),
(B,D,E), (C,F), (D,F)
Number of states in minimal machine
lower bound : 3
upper bound : 5
We have to pick (C,F)
(C,F)  (D,F)  (A,B,E)
If we pick (C,F) then (D,F) will be another, then to make a 3-state machine. We have to
choose(A,B,E)
(C,F)
(D,F)
–
I1
I2
(A,B,E)
I1
I1
I4
I3
(D,F)
(D,F)
I3
I4
I2
I4
I3
(A,B,E) (A,B,E) (C,F)or(D,F) (D,E)
(C,F) (A,B,E) (A,B,E) (A,B,E)
Next, only let C is a state.
I2
We can’t find a 3-states
machine starting with (C,F)
(B,D,E)
I1
(A,B,E), (D,F) – we can’t find a 3-state machine
I2
(A,F), (B,D,E)
(A,F) (B,D,E)
Add one more state
Start with C then
If pick (C,F), (D,F), (A,B,E), (D,E)




I3
(A,B)
We can’t find a 3-states machine
Reduced table
(D,E)
I1
I2
I3
S




I4
(A,B,E) (D,E) (A,B,E) (A,B,E)
or (A,B,E)
I1
–/1
/0
/0
/0
I2
/1
/1
/0
/–
I3
I4
/0
/–
/1
/1
/1
/1
/1
/1
Synchronous sequential machine – common clock
Asynchronous sequential machine – non common clock
What constitute input change
Clock skew : different time between each circuit
Flip-flop
R/S R

R

clock
’
S
’
S
output transition
00
01
10
11
0


1
output
transition
0


1
Required input
S
R
0
1
0
–
–
0
1
0
J/K flip-flop
D flip-flop
output
transition
Required input
J
K
0


1
–
–
1
0
0
1
–
–
T flip-flop
output
transition
Required input
D
output
transition
Required input
T
0


1
0
1
0
1
0


1
0
1
1
0
Synthesis of synchronous sequential circuits
1. From the specification of problem, from a state table (or a state diagram)
2. Minimize the machine
3. Select a state assignment and determine the type of memory elements
4. Drive output transition and output tables
5. Draw a circuit diagram
A
0/0
even blocks of zero or
odd blocks of one
1/0
1/1
B
0/0
1/0
C
1/0
0/0
0/0
0/1
D
1/0
E
Sequential
machine
B: in a sum of zeros, seen an odd # of zeros
C: in a sum of ones seen an odd # of ones
D: in a sum of zeros seem am even # of zeros
E: in a sum of zeros seen an even # of ones
I
0
S
A
B
C
D
E
B/0
D/0
B/0
B/0
B/0
I
1
P1 : ACD, BE
P2 : AD, C , B, E
P3 : AD, C, B, E
C/0
C/1
E/0
C/0
C/1
S




Reduced

0
1
/0
/0
/0
/0
/0
/1
/0
/1
Example)
I
0
S




/0
/0
/0
/1
1
y1y2
/0
/1
/0
/0
Let, =00, =01,
00
01
10
11
=10, and =11, then

0 1
01/0 10/0
00/0 10/1
01/0 11/0
01/0 11/1
Y1Y2
Y1
J1
K1
Y2
J2
J1
K2
x
y1y2
0
1
0
1
0
1
x
y1y2
0
1
0
1
0
1
x
y1y2
0
1
00
0

0
1
–
–
00

0
1
0
–
–
00
0
1
01
0

0
1
–
–
01


–
–
1
1
01
0
1
10

1
–
–
1
0
10


1
1
–
–
10
–
–
11

1
–
–
1
0
11
1
1
–
–
0
0
11
–
–
J1=x,
K1=x’,
J2=x’+y1,
K2=x+y1’
Output (Z)
x
y1y2
0
00
0
0
01
0
1
10
1
0
11
0
0
1
x
y
Z
Combinational
Circuit
Z=y1y2x’+y1’y1x
M
x
y1
Z
y2
Iterative networks: a cascade of identical circuits
(or cells)
xk•••x2x1
Combinational
Circuit Q
y1 J1
K1
y2 J2
K2
yi
x1
x2
Q
Q
Z1
Z2
Zk•••Z2Z1
M
Yi
xk
Q
••• •••
Q
Zk
Asynchronous Sequential circuit
I
Combinational
circuit
yi
Z
Total state: next state equal to the
present state.
Yi

Stable state

State table
One stable state
P.S.
Ij
Si
Primitive flow table assumption:
Only one stable state per row, and outputs are specified only for stable state.
Prob. 11-9
bar
l
x 1x 2
00 01 10 11
state
A
A/0
B
No bar under beams or between beams
B
C
B/0 D
One bar is under B1
C
C/0 E
D
F
Short bar between beams
D/0
Long bar under both beams
E
G E/0
H
Short bar under B2 only
F
A F/0
I
Long bar under B2 only and nothing under B1
G
G/1
J
H
Short bar passed both beams & nothing under B 1
J H/0 Short bar under B2 and another bar under B1
I
I/0
J
C
J/1 D
Long bar under B2 and another bar under B1
Short bar just cleared B2 and another under B1
Maximal compatible class
(ABCI), (ABDFI), (CHJ), (DGI), (EG), (EH), (F,J)
Best closed cover
(ABCI), (DFI), (EG), (DHJ)
x1x2




00
/0

/1

01

/0
/1

10
11
/0


/1

/0

/0
State assignment in asynchronous sequential circuit
I
y1
Z
Combinational
circuit
Not common clock
yk
Yk

Y1

Race occurs anytime multiple state variables must change during a state transition
Critical race : A race which may result in reaching an erroneous stable state
(vs. Non critical race)
The assignment of multiple vars must be such that the circuit will operate correctly even if
different delays are associated with the secondary elements.
x1x2
y1y2
A
B
C
D
If x1x2=00
If x1x2=01
00
01
10
11
C
C
C
C
AA
A
D
D
C
D
D
B
D
C
C
x1x2
y1y2
00
01
11
10
00
01
10
11
11
11
11
11
00
00
00
10
10
11
10
10
01
10
11
11
current state y1y2=00  y1y2=11(stable state)
current state y1y2=11  y1y2=00 or 10
x1x2
y1y2
A 00
B 01
C 10
D 11
00
01
10
11
10
10
10
10
00
00
00
11
11
10
11
11
01
11
10
10
For valid state assignment, each transition is accomplished by change of secondary state
1. In which only one secondary variable change
2. In which a multiple change of secondary variables does not result in a critical race
Multiple transition time state assignment
00








01




10
11









01
00
 10

11 









Same we can say
(, ), (, ) adjacent

000
001

 010
101
 110


100
avoid race
 000
 001
 010
011
 100
 101
 110
111
00
01
10
11
000
000
010
– –
000
––
––
––
010
001
010
––
101
001
––
––
000
000
000
––
100
––
––
––
001
001
110
––
100
––
100
––
o Single transition time state assignment
000

100
001
010
001
010
100
101 
 011
010
111
100
111

110
 000
 001
 010
 011
100
 101
 110
111
00
01
10
11
000
000
000
011
000
000
000
––
011
011
011
011
101
101
101
101
000
000
000
000
000
000
110
––
101
101
110
110
101
101
110
110
Y1 = f(y1, y2, y3, x1, x2)
Y2 = f(y1, y2, y3, x1, x2)
Y3 = f(y1, y2, y3, x1, x2)
13. State Identification and Fault-Detection Experiment
a machine : reduced, completely specified
I
a machine
(block box)
Z
A block box which cannot inspect the internal device and their interconnection.
 The experiment consists of a set of inputs and their corresponding output sequences.
 Identify the unknown initial state and the final state of the machine.
 Equivalent to fault-detection problem to determine whether the machine is operating
correctly.
o Homing sequence: to identify the final state.
The input sequence which, when applied starting in any initial state, allows the final
state to be uniquely determined by observing the output sequence produced.
I
S
A
B
C
D
(A, B, C, D)
0
1
C/0
D/1
A/1
C/0
B/0
C/0
A/0
D/0
0
0
(C)
1
0
1
(A, D)
1
0
(A, B, C, D)
Input seq: 00
Output seq: 01 A
Output seq: 10 C
All machine has homing sequence
(A) (C)
o Synchronizing sequence: the input sequence which
(A, B, C, D)
drives a machine to a
known
state, independent of the
1
0
output sequence produced.
I
(A, B, C, D) (B, C, D)
0 1
S
A
B
C
D
A/1
B/0
C/0
D/1
B/0
C/0
D/0
D/1
1
0
(B, C, D)
(C, D)
0
1
111: synchronizing sequence
(C, D)
(D)
I
S
A
B
C
D
0
1
A/0
B/1
C/1
C/0
B/0
D/0
A/0
A/1
(A, B, C, D)
0
(A, B, C)
0
1
1
(A, B, D)
0
1
(A, B, C) (A, B, D) (A, B, C) (A, B, D)
This machine does not have synchronizing sequence