Basic Logic Design
with Verilog
TA: Chen-han Tsai
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
Outline
Introduction to HDL/ Verilog
Gate Level Modeling
Behavioral Level Modeling
Test bench
Summary and Notes
Simulation using Silos
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Introduction to HDL/ Verilog
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
What is HDL/Verilog
Why use HDL (Hardware Description Language)?
HDL ←→ layout by human
Reduce cost and time
Verilog is one of the most popular HDLs
VHDL (another popular HDL)
Key features of Verilog
Supports Various levels
Behavior level (Register Transfer Level, RTL)
Gate level
Switch level
Simulate design functions
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Hardware Design Flow
Designer
Level
RTL
Simulation
RTL
Editor
Cost
High
Low
Low
High
RTL Code
Gate Level
Simulation
Verilog
Post Gate
Level
Simulation
Logic
Synthesizer
Gate Level Code
Place & Route
Physical Layout
Tape Out
Chip EE, NTU
Lecture Note on Vrilog, Course #90132300,
C.H Tsai, 10/29/2004
An Example
1-bit Multiplexer
to “select” output
in1
sel
0
out
in2
1
if (sel==0)
out = in1;
else
out = in2;
sel
in1
in2
out
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
out = (sel’‧in1) + (sel‧in2)
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Gate Level Description
in1
iv_sel
in2
n1
sel
a1
a2
a1_o
o
1
out
a2_o
iv_sel
Gate Level: you see only gates and wires in the code
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Behavioral Level Description
always block
assign
RTL: you may see high level behavior in the code
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Verilog HDL Syntax
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
A Simple Verilog Code
module name
in/out port
declaration
syntax
port/wire
declaration
kernel hardware
gate-connection/
behavior
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Module
Basic building block in Verilog.
Module
Created by “declaration” (can’t be nested)
2. Used by “instantiation“
1.
Interface is defined by ports
May contain instances of other modules
All modules run concurrently
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Module Instantiation
Adder
instance
example
Adder
Adder
Adder_tree
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Port Connection
Connect module port by order list
FA1 fa1(c_o, sum, a, b, c_i);
Not fully connected
FA1 fa3(c_o,, a, b, c_i);
Connect module port by name
FA1 fa2(.A(a), .B(b), .CO(c_o),.CI(c_i), .S(sum));
Recommended
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Verilog Language Rule
Case sensitive
Identifiers:
Digits 1…9
Underscore _
Upper and lower case letters from the alphabet
Terminate line with semicolon “;”
Comments:
Single line: // it’s a single line comment example
Multiline: /* when the comment exceeds single line,
multiline comment is necessary*/
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Register and Net
Registers
Keyword : reg, integer, time, real
Storage element
Assignment in “always” block
Nets
Keyword : wire, wand, wor, tri
triand, trior, supply0, supply1
Doesn’t store value, just a connection
input, output, inout are default “wire”
Can’t appear in “always” block assignment
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Value and Number expressions
Verilog value set consists of four basic values:
0 represent a logic zero or false condition
1 represent a logic one or true condition
x represent an unknown logic value
z represent a high-impedance stage
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Value and Number
Expressions : Examples
659
// unsized decimal
‘h 837ff // unsized
hexadecimal
‘o7460 // unsized octal
4af
// illegal syntax
4’b1001 // 4-bit binary
5’D 3
// 5-bit decimal
3’b01x // 3-bit number with
unknown LSB
12’hx
// 12-bit unknown
8’d -6 // illegal syntax
-8’d 6 // phrase as - (8’d6)
// underline usage
27_195_000
16’b0001_0101_0001_1111
32’h12ab_f001
// X and Z is sign-extended
reg [11:0] a;
initial
begin
a = ‘hx;
a = ‘h3x;
a = ‘h0x;
end
Lecture Note on Vrilog, Course #90132300, EE, NTU
// yields xxx
// yields 03x
// yields 00x
C.H Tsai, 10/29/2004
Net Concatenations :
An Easy Way to Group Nets
Module B
Module A
Module C
3‘o7
Representations
Meanings
{b[3:0],c[2:0]}
{a,b[3:0],w,3’b101}
{4{w}}
{b,{3{a,b}}}
{b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}
{a,b[3] ,b[2] ,b[1] ,b[0],w,1’b1,1’b0,1’b1}
{w,w,w,w}
{b,a,b,a,b,a,b}
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
(excerpts from CIC training course： Verilog_9807.pdf)
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
(excerpts from CIC training course： Verilog_9807.pdf)
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Compiler Directives
`define
`define RAM_SIZE 16
Defining a name and gives a constant value to it.
`include
`include adder.v
Including the entire contents of other verilog source
file.
`timescale
`timescale 100ns/1ns
Setting the reference time unit and time precision of
your simulation.
Only 1, 10, and 100 are legal values.
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
System Tasks
$monitor
$monitor ($time,"%d %d %d",address,sinout,cosout);
Displays the values of the argument list whenever any
of the arguments change except $time.
$display
$display ("%d %d %d",address,sinout,cosout);
Prints out the current values of the signals in the
argument list
$finish
$finish
Terminate the simulation
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Gate Level Modeling
Gate Level Modeling
Primitives
Case Study
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
Gate Level Modeling
Steps
Design the smallest sub-modules
Construct modules with built sub-modules
Connections
Use “assign a = b;” to connect a and b (a is driven
by b)
HDL: Hardware Description Language
Architecture figure first, then start to write
code!!
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Primitives
Primitives are modules ready to be
instanced
Verilog build-in primitive gate
not, buf
and, or, not, buf, xor, nand, nor, xnor
Design ware
Vender-provided primitive gates
User-built primitive gate
Your building block modules (sub-modules)
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
A
Co
B
Full
Adder
S
Ci
Ci
A
B
Co
S
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Co = (A‧B‧Ci’)+(A‧B’‧Ci)+(A’‧B‧Ci)+(A‧B‧Ci)
= (A‧B‧Ci’)+(A‧B’‧Ci)+ (B‧Ci)
= { A‧[ (B‧Ci’)+(B’‧Ci) ] } + (B‧Ci)
B’
Ci
B
Ci’
A0
O0
A1
A
B
Ci
A2
O1
Co
A3
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
S = (A’‧B’‧Ci)+(A’‧B‧Ci’)+(A‧B’‧Ci’)+(A‧B‧Ci)
= { A’‧[ (B’‧Ci)+(B‧Ci’) ] } + { A‧[ (B’‧Ci’)+(B‧Ci) ] }
B’
Ci
A4
B
Ci’
A5
B’
Ci’
B
Ci
O2
A’
A
A7
A6
O4
S
A9
O3
A8
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Design hierarchy
B’
Ci
B
Ci’
AND
OR
O0
A1
A
B’
Ci
A4
B
Ci’
A5
B’
Ci’
B
Ci
Co connect
A0
B
Ci
A2
O1
Co
O4
S
A3
O2
A’
A
A7
A6
A9
O3
A8
S connect
Full Adder
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Basic gate: 1-bit AND
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Basic gate: 1-bit OR
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Connect co
Instance AND, OR gates
B’
Ci
B
Ci’
A0
O0
A1
A
B
Ci
A2
O1
Co
A3
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Connect s
Instance AND, OR gates
B’
Ci
A4
B
Ci’
A5
B’
Ci’
B
Ci
O2
A’
A
A7
A6
O4
S
A9
O3
A8
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Full Adder Connection
Instance co, s
B’
Ci
B
Ci’
O0
A1
A
B’
Ci
A4
B
Ci’
A5
B’
Ci’
B
Ci
Co connect
A0
B
Ci
A2
O1
Co
O4
S
A3
O2
A’
A
A7
A6
A9
O3
A8
S connect
Full Adder
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Code
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
However…
Further Reduction is Possible
B’
Ci
B
Ci’
A1
A
A4
B
Ci’
A5
B
Ci
Ci
O0
B’
Ci
B’
Ci’
B’
A0
O2
B
Ci
A’
A
A7
B
Ci’
A2
O1
A0
O0
A1
Co
A3
A6
O4
S
A9
A
B
Ci
A’
A
-1
A2
O1
Co
O4
S
A3
A6
A9
O3
A8
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Behavioral Level Modeling
Behavioral Level Modeling
Case Study
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
Behavioral Level Modeling
High level description
User friendly
Concise code
Widely used for some common operations
+,-,*
&,|,~
Two main formats
always block
assign
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
A
Co
B
Full
Adder
S
Ci
{Co,S} = A + B + Ci
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Case Study
1-bit Full Adder
LHS signals in always
block should be declared
as “reg”
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Test bench
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
Test bench Usage
Test bench
data_i
input ports
Design
Top Module
answer_o
Equal?
output ports
data_o
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Summary
Design module
Gate level or behavior level
Real hardware
Modules exists all the time
Each module has architecture figure
Plot architecture figures before you write verilog codes
Test bench
Feed input data and compare output values versus
time
Usually behavior level
Not real hardware, just like C/C++
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Note
Verilog is a platform
Support hardware design (design module)
Also support C/C++ like coding (test bench)
How to write verilog well
Know basic concepts and syntax
Get a good reference (a person or some code files)
Form a good coding habit
Naming rule, comments, format partition (assign or always
block)
Hardware
Combinational circuits (today’s topic)
畫圖(architecture), then 連連看(coding)
Sequential circuits (next topic)
register: element to store data
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Simulation using Silos
Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai
Create new project
Write your verilog design code
Create a new project:
Project -> New -> (enter your project name)
Include your verilog file(s)
(choose your .v file) -> (click Add bottom) ->
(click OK)
Note that testbench should be included
Then run and debug
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004
Run and Debug
Run
Press F5 or click the “GO” icon on tool bar
An output window is generated to show whether
there exists errors.
Debug
Press “open analyzer” on the toolbar
Press “open explorer” on the toolbar
Choose signals you want to watch
Click right button and select “Add signal to analyzer”
Then you can debug with waveform
Lecture Note on Vrilog, Course #90132300, EE, NTU
C.H Tsai, 10/29/2004