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• Charge Pump PLL
– Loop Component Modeling
– Loop Filter and Transfer Function
• Loop Filter Design
• Loop Calibration
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• The charge pump PLL is one of the most popular PLL structures since 1980s
• Featured with a digital phase detector and a charge pump
• Advantages
– Fast lock and tracking
– No false lock f i f o
Phase
Detector
Charge
Pump
Loop
Filter
VCO f o
N-Divider
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• Gives the phase difference between the input clock signal and VCO output signal
• Different types
– Nonlinear (such as Bang-Bang)
– Linear (such as Hogge’s Phase Detector)
• Linear PD output a digital signal whose duty ratio is proportional to the phase difference
– In Hogge’s PD, if the phase difference is θ e output digital signal duty ratio is

2
 e
, the
C. Hogge,
“
A Self-correcting clock recovery circuit
”
, Dec, 1985
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Circuit
Structure
1
2

Output
Waveform
When locked
Y. Tang, et., al., "Phase detector for PLL-based high-speed data recovery," Nov. 2002
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• Convert a digital signal into current
I
P
UP
I up
DN
I dn
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• Low pass filter
– 1 st order
– 2 nd order (higher roll-off speed at high frequency)
– 3 rd order & higher
I p
I p
C1
V
C
C1
C2
V
C
R R
F ( s )

R

1 sC
1
F ( s )
 s
2
RC
1 sRC
1
C
2


1 s ( C
1

C
2
)
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• Tuning gain K
VCO parameter is the most important
• Usually coarse tuning and fine tuning
K
VC O s
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f i f o
Phase
Detector
Charge
Pump
Loop
Filter
VCO f o
θi
θo
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nd
• Using a 1 st order LPF: Active PI type
• Open-loop transfer function
I p
K
VCO
(sRC
1

1 )
G o
( s )

2 πs
2
C
1
• Closed-loop transfer function
G c
(s)
 s
I s
2  s p
K
VCO
R

I
2 π
I p
K
VCO
R

2
π p
K
VCO
2 πC
1
I p
K
VCO
2
πC
1
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rd
• Using a 2 nd order LPF
• Let m=C2/C1
• Open-loop transfer function
G o
( s )
 s
3
I p
K
VCO
2

RC
1
C
2
 s
(
2 sRC
1
( C
1

1 )

C
2
)
 s
I s p
3
K
VCO
2
 mRC
1
• Closed-loop transfer function
R

 s
2
I p
K
VCO
2

C
1
( m

1 )
G c
( s )
 s
I p
K
VCO
R
2
 s
3 mRC
1
 s
2
( m

1 )
 s
I

I p
K
VCO
2

C
1 p
K
VCO
R
2


I p
K
VCO
2

C
1
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• When m becomes 0, the 3 rd order loop degenerates into 2 nd order loop
• 3 rd order loop gives an extra high frequency pole, which increases the high frequency roll-off in jitter transfer
• 3 rd order loop is widely used and can be treated as 2 nd order loop for simplification
• Unfortunately, the 3 rd order loop shows different jitter transfer from the 2 nd order loop
• We focus on 3 rd order loop
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rd
• Define natural frequency ω n
& damping ratio ξ
 2 n

I p
K
VCO
2

C
1
2
 n

I p
RK
VCO
2

• Then totally 3 loop parameters: ω n
, ξ &m
• Simplified transfer function
G c
( s )
 m
2

 n
2
 n s
  n
2 s
3 
( m

1 ) s
2 
2
 n s
  n
2
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• 3-dB frequency – easy to control
• Roll-off speed– easy to meet with 2 nd and 3 rd order transfer function
• Jitter transfer (jitter peaking)
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nd
• Jitter peaking can be reduced or eliminated by increasing the damping ratio
– Eliminated when damping ratio ξ >1
• Large damping ratio leads to slow closedloop response
• Usually suggested ξ=5 to meet the jitter peaking spec
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rd
• Usually believed to be similar as the 2 nd order loop
• Actually quite different from the 2 nd order loop case
• Jitter peaking always exists even with very large ξ
• Need to be treated carefully
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Jitter peaking is dependent on ξ and m
• m=0 (2nd loop) jitter peaking can be reduced or eliminated by using large ξ
• m>0 (3rd loop)
 ξ is quite small, increasing
ξ will decrease the jitter peaking;
 ξ is larger than a threshold value ξ m
, increasing ξ will increase the jitter peaking
Jitter peaking versus damping ratio and capacitance ratio
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How to achieve the minimum jitter peaking
• For given m, there exists the minimum jitter peaking
--the minimum jitter peaking can be viewed as a function of m: JP(m)
• The minimum jitter peaking under a given m is achieved only by using a proper ξ
-ξ should be a function of m:
ξ m
(m)
JP(m)
ξm(m)
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Sampling effect of phase detector
• The phase detector has sampling effect, especially when its rate is not much higher than the loop cut-off frequency
• Approximate TF of phase detector :
H
PD
( s )

1 e
-sT
P sT
P

1
2

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• It causes the jitter peaking worse
 when ξ is very small, jitter peaking decreases when ξ increases;
 when ξ becomes larger than ξ m
, jitter peaking increases with ξ;
 when ξ is larger than ξ m2
, jitter peaking decreases when ξ is increased further
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JP(m) and ξ m
(m) with sampling effect
JP(m) with sampling effect ξ m
(m) with sampling effect
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m
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Design procedures of charge pump PLLs for jitter transfer characteristic optimization
1.
Decide the maximum tolerated jitter peaking and find capacitance ratio m using JP(m).
2.
Use ξ m
(m) to find the optimal damping ratio value ξm;
3.
Decide ω n according to the application, choose reasonable K
VCO
, and calculate I p
, R, C
1 and C
2
;
4.
Use time domain simulation to verify that the expected jitter transfer performance can be achieved
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• Target: to design a
2.5GHz CP PLL, meet the jitter specification
• Design parameters: m=0.005
and ξ=5.0
• Simulation result: jitter peaking is only 0.078dB
Jitter transfer characteristic of the designed PLL
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More Discussion on Loop Transfer Function
• The above discussion suggests to use very small m to meet the jitter peaking
• However, if m is too small, the effect of the second capacitor can even be ignored
• Compromise should be made between jitter peaking and other performance
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• Purpose: make the loop transfer characteristic meet the spec
• Calibration types:
– Component calibration
– Loop calibration
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• Purpose: minimize the mismatching between UP and DOWN current
• Method: switch small current sources
UP
DN
I up
I dn
UP
I up
I
CAL
I
CAL … I
CAL
I
CAL
DN
I dn
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• Use the UP or Down current to charge/discharge a capacitor
• Compare the time difference and calculate the calibration code
UP
I up
Ref CLK
Vref Counter
R/S
Comparator
DN
I dn
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• Purpose: to speed frequency tracking
• Method: make use of the coarse tuning functionality of the VCO
• When extreme high frequency range is desired, double VCOs can be used to help achieve fine frequency tuning resolution
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• Apply different coarse tuning voltage
(output from a low resolution coarse tuning
DAC)
• Measure VCO output frequency respectively
– Compare to the reference frequency
• Write the desired DAC code into register
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• Purpose: calibrate the loop transfer function time constant so that the 3-dB frequency meets the spec
• Method: switch small CAL capacitors
C
CAL
C
CAL …
CAL
C
CAL
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Vref
Time Constant Calibration Procedure
V
X
( t )

Vref
RC
 t
Counter #
 f ref

RC
R
C
Ref CLK
Vref
Vx
Counter
R
Comparator
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• Purpose: calibrate the loop transfer gain to the desired value
• Method: switch different charge pump output current (K usually)
VCO is not changeable
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