CS3220 Final Solution
2.
3.
See the slides, 2014-09-15-isa.pptx
 Instructions and their formats
 Data types
 Number of Register and their sizes
 Addressing modes
 Size of instruction word
4.
See the slides, 2014-11-03-branch-prediction.pptx
http://en.wikipedia.org/wiki/Branch_predictor
5.
http://en.wikipedia.org/wiki/Hazard_(computer_architecture)


Structural Hazard: When two or more instructions want to use the same resource at the same
time.
o Example: A machine with single memory which is accessed both during **Fetch** and
**WriteBack** stage. During ** Fetch** stage, an instruction is read from the memory and
during the **WriteBack** stage the data is written and/or read from memory. This
simultaneous access cannot be handled by this machine, therefore it could cause stalls in
the processors.
Control Hazard: When the processor does not know the outcome of a branch instruction.
Therefore it cannot insert the next instruction during the ** Fetch ** stage. The processor needs to
be stalled until the outcome of the branch is available so the processor can start fetching the
instructions from that address.
o Example:
LW R1, 0(R3)
LW R0, 4(R3)
BEQ R0, R1, START

SHL R2, R0, 2
START:
ADD R2, R0, R1
Data Hazard: When there is a kind of dependency between two instructions. Data Hazard has
three types:
1. RAW
2. WAW
3. WAR
o Example (RAW): (one is enough)
ADD R1, R2, R3
ADD R5, R1, R4
6.
http://www1.ece.neu.edu/~dschaa/docs/parallelism.html
1. Instruction Level Parallelism (ILP): The number of instructions that can be executed
simultaneously in a computer program.
2. Thread Level Parallelism (TLP):
3. Data Level Parallelism (DLP): This type of parallelism is achieved when same instruction is
executed on different data (SIMD)
7.
module detector(clk, rst, x, z);
input clk;
input rst;
input x;
output z
reg [2:0] state;
// design
parameter start
= 3’b000;
parameter got1
= 3’b001;
parameter got10
= 3’b010;
parameter got101 = 3’b011;
parameter got1010
= 3’b100;
always @(posedge clk)
begin
if(rst)
begin
state <= start;
end
case (state)
start:
if(bit_in == 1’b0) state <= start;
else state <= got1;
got1:
if(bit_in == 1’b1) state <= got1;
else state <= got10;
got10:
if(bit_in == 1’b1) state <= got101;
else state <= start;
got101:
if(bit_in == 1’b0) state <= got1010;
else state <= got1;
got1011:
if(bit_in == 1’b1) state <= got101;
else state <= start;
endcase
end
assign z = (state == got1010);
endmodule
8.
See the slides, 2014-11-05-devices_interrupts.pptx
Polling the devices to detect events is inefficient.
Steps:
(1) Monitor the IRQ signal
(2) Save address of next instruction
(3) Check which interrupt was raised
(4) Jump to interrupt handler routine
9.
Five stages:
(a) Fetch (IF)
(b) Decode (ID)
(c) Execution (EX)
(d) Memory read (MEM)
(e) Write back (WB)
Forwarding:
(a) MEM, WB  EX (RAW hazard)
(b) EX  IF (branch)
(c) MEM  ID (load)
For the case (c), the forwarding is likely to be infeasible since it will create a long delay that drags down
the processor’s frequency.
Also for example in the following piece of code, forwarding can not be solely use to resolve the
dependency. Here ADD needs the R1 contents at the beginning of the **EX** stage while LW will load the
data at the end of ** MEM ** stage. Therefore, we need one cycle stall between these two instructions and
then we can use the forwarding between WB and EX to execute the ADD instruction.
LW R1, R2(0)
ADD R1, R2, R3
10.
Exception occurs when software needs to interfere the processor’s job while the interrupts are triggered
by hardware.
11.
module Stack (clk, rst, push, pop, dataIn, dataOut, empty, full);
parameter ADDR_BITWIDTH = 4;
parameter DATA_BITWIDTH = 32;
parameter N_ENTRIES = (1 << ADDR_BITWIDTH);
input clk;
input rst;
input push;
input pop;
input [DATA_BITWIDTH - 1: 0] dataIn;
output [DATA_BITWIDTH - 1: 0] dataOut;
output empty;
output full;
reg [ADDR_BITWIDTH: 0] head = 0;
reg [DATA_BITWIDTH - 1: 0] data [0: N_ENTRIES - 1];
always @(posedge clk) begin
if(rst)
head <= 0;
else begin
if(push == 1’b1 & head[ADDR_BITWIDTH] != 1’b1) begin
head <= head + 1;
data[head] <= dataIn;
end
else begin
if (head >= 1)
head <= head – 1;
else
head <= head;
end
end
end
assign dataOut = (head >= 1) ? data[head - 1] : 0;
assign empty = (head == 0);
assign full = (head == N_ENTRIES);
endmodule