Introduction to Experiment 6
Internal FPGA Memories,
Pseudo Random Number Generator,
Advanced Testbenches
ECE 448
Spring 2009
Sources
• Lecture 14 Xilinx FPGA Memories
• Lecture 11 Advanced Testbenches
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 11, Xilinx Spartan-3 Specific Memory
•Sundar Rajan, Essential VHDL: RTL Synthesis
Done Right
Chapter 14, starting from “Design Verification”
(handout distributed in class)
ECE 448 – FPGA and ASIC Design with VHDL
2
Sources
• XAPP463 Using Block RAM in Spartan-3 Generation FPGAs
Google search: XAPP463
• XAPP464 Using Look-Up Tables as Distributed RAM in
Spartan-3 Generation FPGAs
Google search: XAPP464
• XST User Guide, Section: Coding Techniques
Google search: XST User Guide (PDF)
http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode.html (HTML)
• ISE In-Depth Tutorial, Section: Creating a CORE Generator
Module
Google search: ISE In-Depth Tutorial
ECE 448 – FPGA and ASIC Design with VHDL
3
joystick
from CONTROL
CURRENT
ADDRES
Curr_Addr
INPUT
INTERFACE
PRNG
Addr
RAM
CONTROL
Din
Dout
Curr_Addr
OUTPUT
INTERFACE
Two 7-segment 8 LEDs
displays
SORTING/
EDIT
from CONTROL
Task 1 – Browsing Mode
8 LEDs
(in binary
notation)
Current Address
Joystick up =
Increment Address
Joystick down =
Decrement Address
Address
Data
00
01
02
03
04
05
….
00
01
02
03
04
05
….
FA
FB
FC
FD
FE
FF
FA
FB
FC
FD
FE
FF
256x8 RAM
Value at
Current Address
Two 7-Segment
Displays
(in hexadecimal
notation)
Task 2 – Edit Mode
8 LEDs
(in binary
notation)
Current Address
Joystick up =
Increment Address
Joystick down =
Decrement Address
Address
Data
00
01
02
03
04
05
….
00
01
02
03
04
05=>06
….
FA
FB
FC
FD
FE
FF
FA
FB
FC
FD
FE
FF
256x8 RAM
Value at
Current Address
Two 7-Segment
Displays
(in hexadecimal
notation)
Joystick Enter = Edit
Joystick up =
Increment Data
Joystick down =
Decrement Data
Joystick Enter = Approve
Task 3 – Initialize
Joystick Enter =
Initialize with
Pseudorandom
Values
Address
Data
00
01
02
03
04
05
….
25
87
94
26
B5
C6
….
FA
FB
FC
FD
FE
FF
7A
5B
34
43
89
78
256x8 RAM
Pseudo Random Number Generator (PRNG)
• A pseudorandom number generator (PRNG) is an algorithm for
generating a sequence of numbers that approximates the
properties of random numbers. The sequence is not truly random in
that it is completely determined by a relatively small set of initial
values.
• A PRNG can be started from an arbitrary starting state, using a seed
state. It will always produce the same sequence thereafter when
initialized with that state. The maximum length of the sequence
before it begins to repeat is determined by the size of the state,
measured in bits.
• PRNG Circuit can be constructed from a Linear Feedback Shift
Register (LFSR) circuit
*from http://en.wikipedia.org/wiki/PRNG
Linear Feedback Shift Register (LFSR)
• A linear feedback shift register (LFSR) is a shift
register whose input bit is a linear function of
its previous state.
• The only linear functions of single bits are xor
and inverse-xor; thus it is a shift register
whose input bit is driven by the exclusive-or
(xor) of some bits of the overall shift register
value.
*from http://en.wikipedia.org/wiki/LFSR
8-bit LFSR (Linear Feedback Shift Register)
with the period of 28-1
R7
R6
R5
R4
R3
R2
R1
8
R
=
D flip-flop with set or reset determining its initial
value after “soft” reset
Run for 8 clock cycles before using a new output value.
R0
Task 4 – Sorting
Joystick Enter =
sorting using one of the following types
sorting signed numbers in the descending order
sorting signed numbers in the ascending order
sorting unsigned numbers in the descending order
sorting unsigned numbers in the ascending order
Joystick Up
changing sorting type
Address
Data
00
01
02
03
04
05
….
25
37
44
56
57
78
….
FA
FB
FC
FD
FE
FF
B4
B6
B8
CC
D4
FF
256x8 RAM
Task 5 – Advanced Testbench
Processes
Generating
Input
Stimuli
Process
Comparing
Actual
Outputs
vs.
Expected
Outputs
Design Under
Test (DUT)
Yes/No
Testvector
file(s)
Design
Correct/Incorrect
Task 5 – Format of an input file
6
B4
89
A3
58
61
78
number of entries to be sorted (in decimal)
empty line
numbers to be sorted in the initial order
(in the hexadecimal notation, one number per line)
empty line
58
61
78
89
A3
B4
numbers after sorting
(in the hexadecimal notation, one number per line)
Task 6 : Different Memory Types
Memory
Distributed
(MLUT-based)
Block RAM-based
(BRAM-based)
Memory
Inferred
Manually
Using Core Generator
Task 7: Dual-port Memory
• Replace Single-Port RAM with Dual-Port RAM
and redesign Sorting Logic accordingly
• Calculate the gain in terms of
- average execution time
- smaller resource utilization.
Introduction to Core Generator
(Hands-on Session)