Lab 4 Comments:
• The Main Points:
– Simulation:
• allowed you to test a circuit before you actually built the
circuit
• Simulator was based on device models
• Device models were used to simulate propagation delays in
actual devices
• Static logic hazards were located, tested (they caused
glitches), and removed.
Lab 5 Comments:
•
The Main Points:
–
The logic analyzer is a test device that is used to view the
signal activity of an actual circuit
•
–
as opposed to the simulated circuit of Lab 4
The Xilinx Design Methodology was the steps you took to:
1. model a circuit
2. simulate the model (verify how it will behave)
3. implement a circuit (on the FPGA) with the same output characteristics
as the model
–
Implementing circuits on the FPGA was much easier than
wiring the circuit using discrete logic gates (previous
experiments).
Experiment 6
Combinational Building Blocks:
Encoders and Decoders
Instructional Objectives:
• To learn concurrent statements in VHDL.
• To design combinational building blocks in
VHDL and to implement them on the
Spartan 3 (Nexys) or Spartan 3E (Nexys 2)
FPGA.
VHDL Basics
• ENTITY– black box description of circuit
– declares inputs and outputs, their type, and their
size
• ARCHITECTURE – what’s inside the box
– Specifies the implementation of your circuit
VHDL Entity
ENTITY modulename IS
PORT (
input1 : IN STD_LOGIC;
input2 : IN STD_LOGIC;
output1 : OUT STD_LOGIC_VECTOR(0 TO 7);
output2 : OUT STD_LOGIC);
END modulename;
VHDL Architecture
ARCHITECTURE myarch OF modulename IS
internal signal declarations;
BEGIN
concurrent statement1;
concurrent statement2;
concurrent statement3;
END myarch;
Concurrent Statements:
Signal Assignment (<=)
ARCHITECTURE my_arch OF module_name IS
SIGNAL internal_sig : STD_LOGIC;
BEGIN
-- a comment begins with two hyphens
internal_sig <= input1 AND input2;
output1 <= “10101010”;
output2 <= internal_sig XOR output1(3);
END my_arch;
Concurrent Statements:
Conditional Signal Assigment
ARCHITECTURE myarch OF modulename IS
BEGIN
output2 <= b WHEN (sel = “01”) ELSE
c WHEN (sel = “10”) ELSE
d WHEN (sel = “11”) ELSE
a; -- default
END myarch;
Concurrent Statements:
Selected Signal Assignment
ARCHITECTURE myarch OF modulename IS
BEGIN
WITH sel SELECT
output2 <= b WHEN “01”,
c WHEN “10”,
d WHEN “11”,
a WHEN OTHERS;
END myarch;
Experiment 6 Overview
P1:
Design and implement a Binary-Coded-Decimal
(BCD) to 7-segment Display Decoder
P2:
Design and implement an 8:3 Priority Encoder
P3:
Integrate the circuit from the two previous steps
and use the BCD-7seg Decoder to display your
output
Nexys Development Board
a
f
g
e
c
d
Four 7-segment
LED Displays
See Reference Manual
(ignore multiplexing)
b
7-Segment Display Control
COMMON-CATHODE Display
1 = Vcc
1
0
(Works like you expect: 1 = ON)
COMMON-ANODE Display
0 = Gnd
Nexys Board: (0 = ON!)
So the 7 segment cathode signals (CA..CG) on Nexys Bd are active low
Nexys Development Board
AN0
CE CF
CD CA CG CB CC DP
AN1
CE CF
CD CA CG CB CC DP
AN2
CE CF
CD CA CG CB CC
CA
(from CB
FPGA)
• The individual display segment cathode signals from FPGA
(CA..CG and DP) connect to ALL 4 displays at the same time (!!)
• You must use the common anode signals (AN0..AN3) to turn ON
the 1 display you want to use, and turn OFF the rest.
Nexys Development Board
3.3V
1
0
Common anodes
(AN0..AN3)
connected to Vcc
via a transistor
Controlled by
FPGA outpus
Need 1 or 0 (?)
from FPGA
to Turn ON
a Display??
Lab Report Comments:
VHDL CODE:
• Use the title banner in all your source
code files
Example VHDL Code Header
-- Company: Cal Poly SLO
-- Engineer: Stu Dent & Labpa R. Tner
--- Create Date: 10-06-07
-- Design Name: BCD-to-7 Segment Decoder
-- Component Name:
-- Target Device: Digilent Nexys Development Board
-- Tool versions: ISE 9.1
-- Description: CPE 169 Experiment #6 – Procedure #1
-- This device converts a single-digit (0-9) 4-bit BCD code to the control
-- signals to display the digit on 1 of 4 available 7-seg. displays
-- Dependencies:
-- Revision:
-10-13-07: added a few comments (like the instructor said we should!)
--- Additional Comments:
Lab Report Comments:
VHDL CODE:
•
•
•
•
Use the title banner in all your VHDL files
Put some comments into your VHDL code
Use indents, spacing, skipped lines to make
structure obvious and code readable.
Don’t allow your VHDL code to wrap around
between lines
– examine your outputs before you submit them!
•
Print your VHDL code from Xilinx environment
and include with your report
– don’t put code into the body of the report
Lab Report Comments:
Circuit Diagrams:
– Titled with a descriptive name for the circuit
– Brief verbal description of the circuit's
function / purpose (what does it do?)
– Circuit schematic and/or block diagram
• Include all input/output signals
– When circuits are implemented in VHDL, signal names on
schematics should match signal names used in your
VHDL code
• Show all input/output signal sources / destinations
on the Development Board (switches, LEDs, etc.)
Lab Report Comments:
Timing Diagrams / ModelSim:
•
Title and annotate all timing diagrams
–
•
Show and explain your “Test Vectors”
–
–
–
•
and all diagrams for that matter!
Make clear how you verified proper operation
If not clear, annotate your test input values and results
(1’s and 0’s, BCD code,…whatever appropriate format for the
signals/vectors.)
Annotate expected outputs where actual outputs displayed
Print timing simulations from ModelSim and include
with your report
–
Annotated!
Test Vectors & Simulation
Objective: Verify that each device
functions as specified
– Thoroughly Verify
• ALL important functions / behaviors
demonstrated
• ALL output signals operate properly
• Common errors / problems shown NOT to occur
– Efficiently Verify
• Test all possible cases (truth table) only if
number of inputs reasonable
• Else, devise more clever subset of test
conditions that are “thorough enough”
Xilinx Notes
• Try placing your Xilinx Projects on the lab
computer “C:” drive while you work in lab
– Choose this location when you create your new ISE Project
– Default Xilinx directory will be used if you don’t redirect your
project file storage when you create the project
Goes to C:\Xilinx\... by default
Set up your own subdirectory on C: drive
C:/Stu_Mary
Xilinx Notes
• Try placing your Xilinx Projects on the lab
computer “C:” drive while you work in lab
– DO NOT put ISE Projects in folders / directories that have
any blank spaces in their names!!
• Xilinx ISE will have trouble finding the files
• …and you will get totally FRUSTRATED
!!!
– Avoid using the “Desktop”
• Pathname has spaces C:\Documents and Settings\...\Desktop
• If they’re on C: drive, your files may not be
available to you later!
– You will need to reuse them for future labs!!!
– COPY whole project to your own FlashDrive before leaving
DIGITAL ALARM SYSTEM
(Experiment #9)
TODAY!
Next
Week
TODAY!
Exp 9
Xilinx Design Methodology
1) VHDL
source
is used to generate
a description of
1) BE
SURE
TO code
PERFORM
ALL STEPS
your circuit design.
IN THE PROPER ORDER TO AVOID
2) The VHDL source code generated in step 1) is
PROBLEMS
USING THE XILINX TOOLS
translated into a form which can be used by other
software used in the design flow.
2) REFER
TO
THE
DETAILED
3) The Test
Bench
Waveform
softwarePROCEDURES
is used to generate
signals WEEK’S
which are used
to verify
proper circuit#5)
operation
IN LAST
LAB
(Experiment
the ModelSim XE simulator.
ANDin THIS
WEEK’S LAB (Experiment #6)
4) The circuit inputs and outputs are internally “mapped” to
FPGA pins YOU
which are
externally hardwired
IF (When!!)
ENCOUNTER
A to input and
output devices on the Nexys board.
Download to
FPGA (ExPort)
3)
PROBLEM, REFER TO #2 ABOVE!
- Make sure that you have followed the proper
5) The circuit design is downloaded into the FPGA.
procedures in the proper order before
asking (and waiting!) for help.
6) Proper operation of the circuit is verified.
IN CASE YOU DO NOT FINISH
• The Xilinx and Digilent Tools are all
available on-line for FREE
Procedure for Downloading
them is posted on the
CPE-169 Website