LABORATORY 9 Digital Logic Circuits

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CS 2204 Laboratory
Digital Design
Haldun Hadimioglu
Computer and Information Science
3/30/2003
CS 2204
Title : Digital Logic and State
Machine Design
Credits : 4
Year : Sophomore
Format : Lectures and Laboratory
3-hour lectures
3-hour laboratory sessions
3/30/2003
Digital Design
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CS 2204
Content : Digital circuit fundamentals
Theory, analysis, design
Digital clock
Car alarm
Traffic light controller
Vending machine controller
Four function calculator
Precursor to courses :
Computer Architecture : computer design (junior)
Advanced hardware design : chip design (senior)
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Digital Design
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CS 2204 Laboratory
Emphasis on design
20 students per lab
2-student teams formed first week
Teams do lab projects and homework
How to approach a large design
Problem analysis and solving
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Digital Design
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CS 2204 Laboratory
Introduces current digital design
techniques and tools
Team-oriented, top-down, core-based
design
Modern hardware development
environment
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Digital Design
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CS 2204 Laboratory
Hardware development environment
Computer Aided Design (CAD) Software :
Xilinx Foundation (industry software)
Simulates hardware
Testing hardware : Digilent board
FPGA Chip on Digilent board
FPGA : Field Programmable Gate Array
Emulates hardware
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Digital Design
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CS 2204 Laboratory
Why CAD Design ?
Circuit design and test before
physical implementation
Shorter and cheaper development
Design objectives reached faster
Speed, cost, power consumption, size, weight,
reliability,..
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Digital Design
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CS 2204 Laboratory
Term Project Spring 2003 :
Game playing circuit
Human vs machine play against each
other
Derived from dominoes
Chance and thinking determine winner
Pieces of circuit completed in 3 to 4
week experiments (deadlines)
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Historical Trend
Mechanical components replaced by
Analog components and
Digital components
Analog components replaced by
Digital components
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Digital Revolution
Computers (laptops to supercomputers)
Microprocessors (Sun Sparc to Intel
Pentium 4)
Car engine controllers
Calculators
Video games
CD Players
Digital cameras
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Benefits of Digital Circuits
Moore’s Law holds since the 1960s
Every two years, number of
transistors on chips doubles
Every two years memory size doubles
Smaller size devices
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Digital Chip
Electronic components are placed in
Die area in center of the chip
There can be
50 million components
transistors
on a microprocessor die
A chip
The die
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Is It Always A Chip ?
NO !
Design on computers kept as
Circuit diagrams : traditional
Hardware Description Language (HDL)
programs : since 1980s
Companies license their design as
Intellectual Property (IP)
Circuit diagram/HDL program files
Used as core circuits
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Digital Circuits
A digital circuit consists of Gates and Flip-Flops
on chips
All chips on Printed Circuit Boards (PCBs)
Notch
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
14 V cc
13 B 4
12 A 4
11 Y 4
10 B 3
6
9
7
8
A3
Y3
7408 AND gate Chip
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Digital Design
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CS 2204 Digital Components
Gates
k
k
OR
m
k+m
m
OR gate
AND
k
k.m
NOT
k
NOT gate (inverter)
AND gate
Flip-flops
D
J
Q
Q
K
C
Q
D Flip-flop
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C
Q
J-K Flip-flop
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A Digital Circuit
Car seat-belt alarm
Alarm sound if engine is running AND
seat-belt is NOT fastened
engine
Seat belt
Digital
circuit
alarm
engine
alarm
AND
Seat belt
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NOT
OR
Digital Design
AND
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Another Digital Circuit
a
b
c
Digital
circuit
if a is 0 => y =a
if a is 1 => y = c
y(a, b, c)
Circuit
Diagram
(Traditional)
p
a
NOT
q
AND
b
OR
y(a, b, c)
c
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AND
r
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The Same circuit
a
b
c
Digital
circuit
y(a, b, c)
if a is 0 => y =a
if a is 1 => y = c
VHDL
Program !
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--MULTIPLEXER
--VHDL STRUCTURAL MODELING
entity multiplexer is
port (A, B, C : in
y
: out
end multiplexer;
BIT;
BIT);
architecture structure of
multiplexer is
signal p, q, r: BIT;
begin
p <= NOT a;
q <= p AND b;
r <= a AND c;
y <= p OR q;
end structure;
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1-bit Adder Design
A 1-bit Adder, Full Adder :
a ci
b
co s
a
s
1-bit
b
0 0
0
0 0
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0 1
1 0
1 1
0
0
...
1
0 1
0 1
1 1
Digital Design
Adder
co
ci
19
The 1-bit Adder
Circuit
Diagram
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Designing the 1-bit Adder
--FULL ADDER
--STRUCTURAL MODELING
entity fulladder is
port (A, B, CIN
SUM, COUT
end fulladder;
: in
: out
BIT;
BIT);
architecture structure of fulladder is
signal s1, s2, s3,s4,s5: BIT;
begin
s1 <= A xor B;
SUM <= s1 xor CIN;
s2 <= A and B;
s3 <= B and CIN;
s4 <= A and CIN;
s5 <= s2 or s3;
COUT <= s4 or s5;
end structure;
3/30/2003
Digital Design
VHDL
Program
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