Dynamic Scheduling
A scheme to overcome data hazards
EE524/CptS561 Advanced Computer Architecture
Advantages of Dynamic Scheduling
• Dynamic scheduling - hardware rearranges the
instruction execution to reduce stalls while
maintaining data flow and exception behavior
• It handles cases when dependences unknown at
compile time
– it allows the processor to tolerate unpredictable delays such as
cache misses, by executing other code while waiting for the miss
to resolve
• It allows code that compiled for one pipeline to run
efficiently on a different pipeline
• It simplifies the compiler
• Hardware speculation, a technique with significant
performance advantages, builds on dynamic
scheduling
EE524/CptS561 Advanced Computer Architecture
HW Schemes: Instruction Parallelism
• Key idea: Allow instructions behind stall to proceed
DIVD
ADDD
SUBD
F0,F2,F4
F10,F0,F8
F12,F8,F14
• Enables out-of-order execution and
allows out-of-order completion (e.g., SUBD)
– In a dynamically scheduled pipeline, all instructions still pass
through issue stage in order (in-order issue)
• Will distinguish when an instruction begins
execution and when it completes execution; between
2 times, the instruction is in execution
• Note: Dynamic execution creates WAR and WAW
hazards and makes exceptions harder
EE524/CptS561 Advanced Computer Architecture
Dynamic Scheduling Step 1
• Simple pipeline had 1 stage to check both
structural and data hazards: Instruction
Decode (ID), also called Instruction Issue
• Split the ID pipe stage of simple 5-stage
pipeline into 2 stages:
• Issue—Decode
instructions,
structural hazards
check
for
• Read operands—Wait until no data hazards,
then read operands
EE524/CptS561 Advanced Computer Architecture
Tomasulo Algorithm
• Control & buffers distributed with Function Units (FU)
– FU buffers called “reservation stations”; have pending operands
• Registers in instructions replaced by values or pointers to
reservation stations(RS); called register renaming;
– Avoids:
WAR
RX
inst. i
WAW hazards
RX 
inst. j
– More reservation stations than registers, so can do optimizations
compilers cannot
• Results to FU from RS, not through registers, over Common
Data Bus that broadcasts results to all FUs
• Load and Stores treated as FUs with RSs as well.
• Integer instructions can go past branches, allowing
FP ops beyond basic block in FP queue.
EE524/CptS561 Advanced Computer Architecture
Tomasulo scheme
From memory
From instruction unit
6
FP
FP
5
4
Load
Operation
3
buffers
queue
Registers
Operand
buses
2
1
Store
3
buffers
2
1
Operation bus
3
To memory
2
Reservation
Stations
2
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Reservation Station Components
Op—Operation to perform in the unit (e.g., + or –)
Vj, Vk—Value of Source operands
– Store buffers has V field, result to be stored
Qj, Qk—Reservation stations producing source registers
(value to be written)
– Note: No ready flags as in Scoreboard; Qj,Qk=0 => ready
– Store buffers only have Qi for RS producing result
Busy—Indicates reservation station or FU is busy
Register result status—Indicates which functional unit
will write each register, if one exists. Blank when no
pending instructions that will write that register.
EE524/CptS561 Advanced Computer Architecture
Three Stages of Tomasulo Algorithm
1. Issue—get instruction from FP Op Queue
If reservation station free (no structural hazard),
control issues instr & sends operands (renames registers).
2. Execution—operate on operands (EX)
When both operands ready then execute;
if not ready, watch Common Data Bus for result
3. Write result—finish execution (WB)
Write on Common Data Bus to all awaiting units;
mark reservation station available
• Normal data bus: data + destination (“go to” bus)
• Common data bus: data + source (“come from” bus)
– 64 bits of data + 4 bits of Functional Unit source address
– Write if matches expected Functional Unit (produces result)
– Does the broadcast
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 0
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 No
0 Mult2 No
Register result status
Execution
complete
S1
Vj
S2
Vk
RS for j
Qj
RS for k
Qk
Clock
F2
F4
F6
F8
0
F0
Write
Result
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
F30
FU
EE524/CptS561 Advanced Computer Architecture
Cycle: 0
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
LD F6, 34(R2)
FP Registers
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
2
Stations
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 1
Load buffers
6
5
4
3
2
1
34+R2
From instruction unit
FP operation queue
From memory
FP Registers
F6 : load1
LD F2, 45(R3)
LD F6, 34(R2)
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
2
Stations
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 2
Load buffers
6
5
4
3
2
45+R3
1
34+R2
From instruction unit
FP operation queue
From memory
FP Registers
F2 : load2
F6 : load1
MULTD F0,F2,F4
LD F2, 45(R3)
LD F6, 34(R2)
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
2
Stations
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 3
Load buffers
6
5
4
3
2
45+R3
1
Mem[34+R2]
From instruction unit
FP operation queue
From memory
FP Registers
F0 : mult1
F2 : load2
F6 : load1
SUB F8,F6,F2
MULTD F0,F2,F4
LD F2, 45(R3)
LD F6, 34(R2)
Store buffers
Operand
buses
3
2
1
Operation bus
3
To memory
2
Reservation
2
Stations
M
load2
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 4
Load buffers
6
5
4
3
2
Mem[45+R3]
1L1: Mem[34+R2]
From instruction unit
FP operation queue
From memory
FP Registers
F0 : mult1
F2 : load2
DIVD F10,F0,F6
F6
F6 Mem[34+R2]
: load1
SUB F8,F6,F2
F8: add1
MULTD F0,F2,F4
LD F2, 45(R3)
LD F6, 34(R2)
Store buffers
Operand
buses
3
2
1
Operation bus
To memory
L1: Mem[34+R2]
3
2
1
2
Reservation
S
Mem[34+R2]
load1
load2
Stations
M
load2
“F4”
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 5
Load buffers
6
5
4
3
2L2: Mem[45+R3]
1
From instruction unit
FP operation queue
From memory
FP Registers
F0 : mult1
ADD F6,F8,F2
F2
Mem[45+R3]
F2 
: load2
DIVD F10,F0,F6
F8: add1
F10: mult2
SUB F8,F6,F2
MULTD F0,F2,F4
LD F2, 45(R3)
Store buffers
Operand
buses
3
2
1
Operation bus
To memory
L2: Mem[45+R3]
3
Reservation
2
1
Stations
S
D
Mult1
Mem[45+R3] 2
M Mem[45+R3]
load2
“F4”
1
Mem[R2] load2
Mem[45+R3]
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 6
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
ADD F6,F8,F2
F6: add2
DIVD F10,F0,F6
F8: add1
SUB F8,F6,F2
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
A
add1
M[R3]
1
S
Mem[R2] M[R3]
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 7
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
ADD F6,F8,F2
F6: add2
DIVD F10,F0,F6
F8: add1
SUB F8,F6,F2
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
A
add1
M[R3]
1
S
Mem[R2] M[R3]
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 8
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
ADD F6,F8,F2
F6: add2
DIVD F10,F0,F6
F8:
F8
add1
M()-M()
SUB F8,F6,F2
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
A
M()-M()
add1
1
S
Mem[R2] M[R3]
M[R3]
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
FP Multipliers
FP adders
Common data bus (CDB)
Add1: M()-M()
EE524/CptS561 Advanced Computer Architecture
Cycle: 9
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
ADD F6,F8,F2
F6: add2
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
A
M()-M()
M[R3]
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 10
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
ADD F6,F8,F2
F6: add2
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
A
M()-M()
M[R3]
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 11
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
ADD F6,F8,F2
F6:
F6
add2
(M()-m())+M()
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
A
M()-M()
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
M[R3]
1
FP Multipliers
FP adders
Common data bus (CDB)
Add2: (M()-M())+M()
EE524/CptS561 Advanced Computer Architecture
Cycle: 12
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 13
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 14
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 15
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 : mult1
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
D
Mult1
M[R3]
2
Stations
M
M[R3]
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 16
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
F0 
: mult1
M()*F4
DIVD F10,F0,F6
F10: mult2
MULTD F0,F2,F4
Store buffers
Operand
buses
3
2
1
Operation bus
3
2
To memory
Reservation
D
Stations
M
M()*F4
Mult1
M[R3]
M[R3]
2
“F4”
1
1
FP Multipliers
FP adders
Common data bus (CDB)
Mult1: M()*F4
EE524/CptS561 Advanced Computer Architecture
Cycle: 17
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
DIVD F10,F0,F6
F10: mult2
Store buffers
Operand
buses
3
2
1
Operation bus
3
Reservation
2
To memory
D
M()*F4
M[R3]
2
1
Stations
1
FP Multipliers
FP adders
Common data bus (CDB)
EE524/CptS561 Advanced Computer Architecture
Cycle: 57
6
Load buffers
From instruction unit
FP operation queue
From memory
5
4
3
2
1
FP Registers
DIVD F10,F0,F6
F10:
F10
mult2
M()*F4 / M()
Store buffers
Operand
buses
3
2
1
Operation bus
3
Reservation
2
To memory
D
M()*F4
M[R3]
2
1
Stations
1
FP Multipliers
FP adders
Common data bus (CDB)
Mult2: M()*F4 / M()
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 1
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 No
0 Mult2 No
Register result status
Execution
complete
S1
Vj
S2
Vk
RS for j
Qj
RS for k
Qk
Clock
F2
F4
F6
F8
1
F0
FU
Write
Result
Load1
Load2
Load3
Busy
No
Yes
No
No
Address
34+R2
F10
F12 ...
F30
Load1
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 2
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
2
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 No
0 Mult2 No
Register result status
Execution
complete
S1
Vj
S2
Vk
RS for j
Qj
RS for k
Qk
Clock
F2
F4
F6
F8
2
F0
FU
Write
Result
Load1
Load2
Load3
Load2
Busy
Yes
Yes
No
Address
34+R2
45+R3
F10
F12 ...
F30
Load1
Note: Unlike 6600, can have multiple loads outstanding
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 3
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
2
MULTDF0
F2
F4
3
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Execution
complete
3
Write
Result
S1
Vj
S2
Vk
RS for j
Qj
R(F4)
Load2
Clock
F0
F2
F4
F6
Mult1
Load2
3
FU
Load1
Load2
Load3
Busy
Yes
Yes
No
Address
34+R2
45+R3
F10
F12 ...
RS for k
Qk
F8
F30
Load1
• Note: registers names are removed (“renamed”) in Reservation
Stations; MULT issued vs. scoreboard
• Load1 completing; what is waiting for Load1?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 4
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 Yes
0 Add2 No
Add3 No
0 Mult1 Yes
0 Mult2 No
Register result status
Clock
4
FU
Issue
1
2
3
4
Execution
complete
3
4
Write
Result
4
Load1
Load2
Load3
S1
Op
Vj
SUBD M(34+R2)
S2
Vk
RS for j
Qj
MULTD
R(F4)
Load2
F4
F6
F8
M(34+R2)
Add1
F0
F2
Mult1
Load2
Busy
No
Yes
No
Address
F10
F12 ...
45+R3
RS for k
Qk
Load2
F30
• Load2 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 5
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
2 Add1 Yes
0 Add2 No
Add3 No
10 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
5
FU
Issue
1
2
3
4
5
Execution
complete
3
4
Write
Result
4
5
Load1
Load2
Load3
RS for j
Qj
Busy
No
No
No
Address
F12 ...
S1
Op
Vj
SUBD M(34+R2)
S2
Vk
M(45+R3)
RS for k
Qk
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
F10
Mult1
M(45+R3)
M(34+R2)
Add1
Mult2
F30
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 6
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
1 Add1 Yes
0 Add2 Yes
Add3 No
9 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
6
•
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
Write
Result
4
5
Load1
Load2
Load3
RS for j
Qj
Busy
No
No
No
Address
F12 ...
S1
Op
Vj
SUBD M(34+R2)
ADDD
S2
Vk
M(45+R3)
M(45+R3)
RS for k
Qk
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
F10
Mult1
M(45+R3)
Add2
Add1
Mult2
Add1
F30
Issue ADDD here vs. scoreboard?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 7
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 Yes
0 Add2 Yes
Add3 No
8 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
7
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
Write
Result
4
5
Load1
Load2
Load3
Busy
No
No
No
Address
F12 ...
7
S1
Op
Vj
SUBD M(34+R2)
ADDD
S2
Vk
M(45+R3)
M(45+R3)
RS for j
Qj
RS for k
Qk
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
F10
Mult1
M(45+R3)
Add2
Add1
Mult2
Add1
F30
• Add1 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 8
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
2 Add2 Yes
0 Add3 No
7 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
8
FU
Issue
1
2
3
4
5
6
Op
Execution
complete
3
4
Write
Result
4
5
7
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
8
S2
Vk
RS for j
Qj
RS for k
Qk
ADDD M()-M()
M(45+R3)
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
Add2
M()-M() Mult2
F30
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 9
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
1 Add2 Yes
0 Add3 No
6 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
9
FU
Issue
1
2
3
4
5
6
Op
Execution
complete
3
4
Write
Result
4
5
7
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
8
S2
Vk
RS for j
Qj
RS for k
Qk
ADDD M()–M()
M(45+R3)
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
Add2
M()–M() Mult2
F30
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 10
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 Yes
0 Add3 No
5 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
10
FU
Issue
1
2
3
4
5
6
Op
Execution
complete
3
4
Write
Result
4
5
7
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
8
10
S1
Vj
S2
Vk
RS for j
Qj
RS for k
Qk
ADDD M()–M()
M(45+R3)
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
Add2
M()–M() Mult2
F30
• Add2 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 11
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
4 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
11
•
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
Write
Result
4
5
7
8
10
11
Address
F10
F12 ...
S2
Vk
RS for j
Qj
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
(M-M)+M()
M()ĞM() Mult2
Op
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
RS for k
Qk
F30
Write result of ADDD here vs. scoreboard?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 12
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
3 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
12
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
Write
Result
4
5
6
7
10
11
Address
F10
F12 ...
S2
Vk
RS for j
Qj
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
(M-M)+M()
M()–M() Mult2
Op
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
RS for k
Qk
F30
• Note: all quick instructions complete already
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 13
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
Add3 No
2 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
13
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
Write
Result
4
5
7
8
10
11
Address
F10
F12 ...
S2
Vk
RS for j
Qj
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
(M–M)+M()
M()–M() Mult2
Op
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
RS for k
Qk
F30
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 14
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
1 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
14
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
Write
Result
4
5
7
8
10
11
Address
F10
F12 ...
S2
Vk
RS for j
Qj
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
(M–M)+M()
M()–M() Mult2
Op
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
RS for k
Qk
F30
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 15
Instruction status
Instruction
j
k
LD
F6
34+
R2
LD
F2
45+
R3
MULTDF0
F2
F4
SUBD F8
F6
F2
DIVD F10 F0
F6
ADDD F6
F8
F2
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
15
FU
Issue
1
2
3
4
5
6
Execution
complete
3
4
15
7
Write
Result
4
5
Address
F10
F12 ...
8
10
11
S2
Vk
RS for j
Qj
MULTD M(45+R3)
DIVD
R(F4)
M(34+R2)
Mult1
F0
F2
F4
F6
F8
Mult1
M(45+R3)
(M–M)+M()
M()–M() Mult2
Op
S1
Vj
Load1
Load2
Load3
Busy
No
No
No
RS for k
Qk
F30
• Mult1 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 16
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
2
MULTDF0
F2
F4
3
SUBD F8
F6
F2
4
DIVD F10 F0
F6
5
ADDD F6
F8
F2
6
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 No
40 Mult2 Yes DIVD
Register result status
Execution
complete
3
4
15
7
Clock
16
FU
Write
Result
4
5
16
8
10
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
11
S1
Vj
S2
Vk
M*F4
M(34+R2)
F0
F2
F4
M*F4
M(45+R3)
RS for j
Qj
RS for k
Qk
F6
F8
(M–M)+M()
M()–M() Mult2
F30
• Note: Just waiting for divide
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 55
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
2
MULTDF0
F2
F4
3
SUBD F8
F6
F2
4
DIVD F10 F0
F6
5
ADDD F6
F8
F2
6
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 No
1 Mult2 Yes DIVD
Register result status
Execution
complete
3
4
15
7
Clock
55
FU
Write
Result
4
5
16
8
10
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
11
S1
Vj
S2
Vk
M*F4
M(34+R2)
F0
F2
F4
M*F4
M(45+R3)
RS for j
Qj
RS for k
Qk
F6
F8
(M–M)+M()
M()–M() Mult2
F30
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 56
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
2
MULTDF0
F2
F4
3
SUBD F8
F6
F2
4
DIVD F10 F0
F6
5
ADDD F6
F8
F2
6
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 No
0 Mult2 Yes DIVD
Register result status
Execution
complete
3
4
15
7
56
10
S1
Vj
Write
Result
4
5
16
8
M*F4
M(34+R2)
Clock
F0
F2
F4
M*F4
M(45+R3)
56
FU
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
11
S2
Vk
RS for j
Qj
RS for k
Qk
F6
F8
(M–M)+M()
M()–M() Mult2
F30
• Mult 2 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Tomasulo Example Cycle 57
Instruction status
Instruction
j
k
Issue
LD
F6
34+
R2
1
LD
F2
45+
R3
2
MULTDF0
F2
F4
3
SUBD F8
F6
F2
4
DIVD F10 F0
F6
5
ADDD F6
F8
F2
6
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
Add3 No
0 Mult1 No
0 Mult2 No
Register result status
Execution
complete
3
4
15
7
56
10
S1
Vj
Write
Result
4
5
16
8
57
11
S2
Vk
RS for j
Qj
RS for k
Qk
Clock
F0
F2
F4
F6
F8
M*F4
M(45+R3)
(M–M)+M()
M()–M() M*F4/M
57
FU
Load1
Load2
Load3
Busy
No
No
No
Address
F10
F12 ...
F30
• Again, in-order issue,
out-of-order execution, completion
EE524/CptS561 Advanced Computer Architecture
Tomasulo Drawbacks
• Complexity
– delays of 360/91, MIPS 10000, IBM 620?
• Many associative stores (CDB) at high speed
• Performance limited by Common Data Bus
– Multiple CDBs => more FU logic for parallel assoc stores
EE524/CptS561 Advanced Computer Architecture
Tomasulo Loop Example
Loop: LD
MULTD
SD
SUBI
BNEZ
F0
F4
F4
R1
R1
0
F0
0
R1
Loop
R1
F2
R1
#8
• Assume Multiply takes 4 clocks
• Assume first load takes 8 clocks (cache miss?),
second load takes 4 clocks (hit)
• To be clear, will show clocks for SUBI, BNEZ
• Reality, integer instructions ahead
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 0
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 No
0 Mult2 No
Register result status
Clock
R1
F0
0
80
Qi
Issue
S1
Vj
F2
Execution Write
complete Result
S2
Vk
F4
Busy Address
No
No
No
Qi
No
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 1
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 No
0 Mult2 No
Register result status
Clock
R1
F0
1
80
Qi
Load1
Issue
1
S1
Vj
F2
Execution Write
complete Result
S2
Vk
F4
Busy Address
Yes
80
No
No
Qi
No
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 2
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
2
80
Qi
Load1
Issue
1
2
S1
Vj
Execution Write
complete Result
S2
Vk
R(F2)
F2
F4
Busy Address
Yes
80
No
No
Qi
No
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 3
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
3
80
Qi
Load1
Issue
1
2
3
S1
Vj
Execution Write
complete Result
S2
Vk
R(F2)
F2
F4
Busy Address
Yes
80
No
No
Qi
Yes
80 Mult1
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
• Note: MULT1 has no registers names in RS
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 4
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
4
72
Qi
Load1
Issue
1
2
3
S1
Vj
Execution Write
complete Result
S2
Vk
R(F2)
F2
F4
Busy Address
Yes
80
No
No
Qi
Yes
80 Mult1
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 5
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
5
72
Qi
Load1
Issue
1
2
3
S1
Vj
Execution Write
complete Result
S2
Vk
R(F2)
F2
F4
Busy Address
Yes
80
No
No
Qi
Yes
80 Mult1
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 6
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
6
72
Qi
Load2
Issue
1
2
3
6
S1
Vj
Execution Write
complete Result
S2
Vk
R(F2)
F2
F4
Busy Address
Yes
80
Yes
72
No
Qi
Yes
80 Mult1
No
No
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
• Note: F0 never sees Load1 result
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 7
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
R1
7
72
Qi
iteration
1
1
1
2
2
2
Issue
1
2
3
6
7
S1
Vj
Op
MULTD
MULTD
F0
Load2
F2
Execution Write
complete Result
Busy Address
Yes
80
Yes
72
No
Qi
Yes
80 Mult1
No
No
R(F2)
R(F2)
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
Load2
BNEZ R1
F4
F6
S2
Vk
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
• Note: MULT2 has no registers names in RS
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 8
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
R1
8
72
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
MULTD
MULTD
F0
Load2
F2
Execution Write
complete Result
Busy Address
Yes
80
Yes
72
No
Qi
Yes
80 Mult1
Yes
72 Mult2
No
R(F2)
R(F2)
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load1
SUBI R1
Load2
BNEZ R1
F4
F6
S2
Vk
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 9
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
R1
9
64
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
MULTD
MULTD
F0
Load2
F2
Execution Write
complete Result
9
Load1
Load2
Load3
Store1
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
R(F2)
R(F2)
Load1
Load2
F4
F6
F8
Busy Address
Yes
80
Yes
72
No
Qi
Yes
80 Mult1
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
• Load1 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 10
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
4 Mult1 Yes
0 Mult2 Yes
Register result status
Clock
R1
10
64
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
Load1
Load2
Load3
10
Store1
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
MULTD
MULTD
M(80) R(F2)
R(F2)
Load2
F0
F2
F6
Load2
F4
F8
Busy Address
No
Yes
72
No
Qi
Yes
80 Mult1
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
• Load2 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 11
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
3 Mult1 Yes
4 Mult2 Yes
Register result status
Clock
R1
11
64
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
Load1
Load2
Load3
10
11
Store1
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
MULTD
MULTD
M(80) R(F2)
M(72) R(F2)
F0
F2
Load3
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 Mult1
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 12
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
2 Mult1 Yes
3 Mult2 Yes
Register result status
Clock
R1
12
64
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
Load1
Load2
Load3
10
11
Store1
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
MULTD
MULTD
M(80) R(F2)
M(72) R(F2)
F0
F2
Load3
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 Mult1
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 13
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
1 Mult1 Yes
2 Mult2 Yes
Register result status
Clock
R1
13
64
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
Load1
Load2
Load3
10
11
Store1
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
MULTD
MULTD
M(80) R(F2)
M(72) R(F2)
F0
F2
Load3
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 Mult1
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 14
Instruction status
Instruction
j
k
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
LD
F0
0 R1
MULTDF4
F0 F2
SD
F4
0 R1
Reservation Stations
Time Name Busy
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes
1 Mult2 Yes
Register result status
Clock
R1
14
64
Qi
iteration
1
1
1
2
2
2
Op
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
Load1
14
Load2
Load3
10
11
Store1
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
MULTD
MULTD
M(80) R(F2)
M(72) R(F2)
F0
F2
Load3
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 Mult1
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
• Mult1 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 15
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 No
0 Mult2 Yes MULTD
Register result status
Clock
R1
F0
15
64
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
Load1
14
15
Load2
Load3
10
11
Store1
15
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
M(72) R(F2)
F2
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 M(80)*R(F2)
Yes
72 Mult2
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult2
• Mult2 completing; what is waiting for it?
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 16
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
16
64
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
F2
Execution Write
complete Result
9
10
Load1
14
15
Load2
Load3
10
11
Store1
15
16
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
R(F2)
Load3
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 M(80)*R(F2)
Yes
72 M(72)*R(72)
No
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 17
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
17
64
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
F2
Execution Write
complete Result
9
10
Load1
14
15
Load2
Load3
10
11
Store1
15
16
Store2
Store3
S2
RS for j RS for k
Vk
Qj
Qk
R(F2)
Load3
F4
F6
F8
Busy Address
No
No
Yes
64 Qi
Yes
80 M(80)*R(F2)
Yes
72 M(72)*R(72)
Yes
64 Mult1
Code:
LD
F0
MULTDF4
SD
F4
SUBI R1
BNEZ R1
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 18
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
18
56
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
14
15
18
10
11
15
16
S2
Vk
R(F2)
F2
F4
Busy Address
No
No
Yes
64 Qi
Yes
80 M(80)*R(F2)
Yes
72 M(72)*R(72)
Yes
64 Mult1
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load3
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 19
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
19
56
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
14
15
18
19
10
11
15
16
S2
Vk
R(F2)
F2
F4
Busy Address
No
No
Yes
64 Qi
No
Yes
72 M(72)*R(72)
Yes
64 Mult1
Load1
Load2
Load3
Store1
Store2
Store3
RS for j RS for k
Qj
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load3
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 20
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
20
56
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
14
15
18
19
10
11
15
16
20
S2
RS for j
Vk
Qj
R(F2)
F2
F4
Busy Address
No
No
Yes
64 Qi
No
Yes
72 M(72)*R(72)
Yes
64 Mult1
Load1
Load2
Load3
Store1
Store2
Store3
RS for k
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load3
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Loop Example Cycle 21
Instruction status
Instruction
j
k
iteration
LD
F0
0 R1
1
MULTDF4
F0 F2
1
SD
F4
0 R1
1
LD
F0
0 R1
2
MULTDF4
F0 F2
2
SD
F4
0 R1
2
Reservation Stations
Time Name Busy Op
0 Add1 No
0 Add2 No
0 Add3 No
0 Mult1 Yes MULTD
0 Mult2 No
Register result status
Clock
R1
F0
21
56
Qi
Load3
Issue
1
2
3
6
7
8
S1
Vj
Execution Write
complete Result
9
10
14
15
18
19
10
11
15
16
20
21
S2
RS for j
Vk
Qj
R(F2)
F2
F4
Busy Address
No
No
Yes
64 Qi
No
No
Yes
64 Mult1
Load1
Load2
Load3
Store1
Store2
Store3
RS for k
Qk
Code:
LD
F0
MULTDF4
SD
F4
Load3
SUBI R1
BNEZ R1
F6
F8
0 R1
F0 F2
0 R1
R1 #8
Loop
F10 F12 ... F30
Mult1
EE524/CptS561 Advanced Computer Architecture
Tomasulo Summary
• Reservations stations: renaming to larger set of
registers + buffering source operands
– Prevents registers as bottleneck
– Avoids WAR, WAW hazards of Scoreboard
– Allows loop unrolling in HW
• Not limited to basic blocks
(integer units gets ahead, beyond branches)
• Helps cache misses as well
• Lasting Contributions
– Dynamic scheduling
– Register renaming
– Load/store disambiguation
• 360/91 descendants are Pentium II; PowerPC
604; MIPS R10000; HP-PA 8000; Alpha 21264
EE524/CptS561 Advanced Computer Architecture
Branch correction
Fetch
Unit
Reorder buffer information
Dispatch unit
w/ 8-entry
instruction queue
Instruction
Cache
Completion
unit w/
reorder
buffer
Instruction
dispatch
buses
Register nos.
GP operand buses
Instruction
Operation
buses
Register
nos.
Register nos.
Register nos.
FP operand buses
Reservation
Stations
XSU0
XSU1
MCFXU
LSU
GP result buses
FPU
BPU
FP result buses
Result status buses
Data
Cache
EE524/CptS561 Advanced Computer Architecture