Introduction to VLSI
(ECE 349b)
Wei Wang
Electrical and Computer Engeering Dept.
The University of Western Ontario
London, ON, Canada
Winter 2003
1
Lecture 1
Course Introduction
Jan. 6 2003
Modern VLSI Design 3e: Chapter 1
week1-2
Partly from 2002 Prentice Hall PTR
General
1. Welcome remark
2. Definition of VLSI
3. Importance of VLSI
Modern VLSI Design 3e: Chapter 1
week1-3
Partly from 2002 Prentice Hall PTR
Course Requirement
1. Expectations
1.
Academic & industry
2. Rules
1.
Attendance & Assignment
2.
Lab
3.
Midterm & final
Modern VLSI Design 3e: Chapter 1
week1-4
Partly from 2002 Prentice Hall PTR
Information
1. Text book in library:

Call no.: TK7874.65.W65 2002
2. Class notes and lab manual:

Ftp sun30.engga.uwo.ca

Username: ece480a

Password: ec.48.EC
Modern VLSI Design 3e: Chapter 1
week1-5
Partly from 2002 Prentice Hall PTR
Information (cont’d)
1. Labs:

2 UNIX labs: EC 2135 (Weeks of Feb. 4 and 18)

Two PC labs: EC1000 (Weeks of Mar. 4 and 18)

(Tuesday, Wednesday and Thursday morning)
2. Assignments:

Two weeks from the post date
3. Drop-off box : in front of lab
Modern VLSI Design 3e: Chapter 1
week1-6
Partly from 2002 Prentice Hall PTR
Wei Wang
Office:
EC 1006
Office hours: Monday and Wednesday
2:00 to 3:00 pm
Email:
Modern VLSI Design 3e: Chapter 1
wwang@eng.uwo.ca
week1-7
Partly from 2002 Prentice Hall PTR
Overview
Why VLSI?
Moore’s Law.
ASIC: Abstraction and Hierarchy.
FPGA: cheaper ASIC
Modern VLSI Design 3e: Chapter 1
week1-8
Partly from 2002 Prentice Hall PTR
VLSI and you
Microprocessors:


personal computers;
microcontrollers.
DRAM/SRAM.
Special-purpose processors.
Many other applications: telecom, DSP,etc.
Modern VLSI Design 3e: Chapter 1
week1-9
Partly from 2002 Prentice Hall PTR
Moore’s Law
Gordon Moore: co-founder of Intel.
Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
Exponential improvement in technology is a
natural trend: steam engines, dynamos,
automobiles.
Modern VLSI Design 3e: Chapter 1
week1-10
Partly from 2002 Prentice Hall PTR
Moore’s Law plot
Modern VLSI Design 3e: Chapter 1
week1-11
Partly from 2002 Prentice Hall PTR
Lecture 2
Overview of VLSI
Jan. 8 2003
Modern VLSI Design 3e: Chapter 1
week1-12
Partly from 2002 Prentice Hall PTR
Overview
Why VLSI?
Moore’s Law.
ASIC: Abstraction and Hierarchy.
FPGA: cheaper ASIC
Modern VLSI Design 3e: Chapter 1
week1-13
Partly from 2002 Prentice Hall PTR
ASIC and FPGA
Application-specific integrated circuit
design
Field programmable gate array


ASIC: 2 UNIX labs (our main focus)
FPGA: 2 PC labs
Modern VLSI Design 3e: Chapter 1
week1-14
Partly from 2002 Prentice Hall PTR
ASIC
Top-down approaches
Modern VLSI Design 3e: Chapter 1
week1-15
Partly from 2002 Prentice Hall PTR
Levels of abstraction
Specification: function, cost, etc.
Architecture: large blocks.
Logic: gates + registers.
Circuits: transistor sizes for speed, power.
Layout: determines parasitics.
Modern VLSI Design 3e: Chapter 1
week1-16
Partly from 2002 Prentice Hall PTR
Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
Throughput,
design time
registertransfer
Function units,
clock cycles
logic
Literals,
logic depth
transistors
circuit
nanoseconds
rectangles
layout
microns
Modern VLSI Design 3e: Chapter 1
week1-17
cost
Partly from 2002 Prentice Hall PTR
CAD Tools
English
VHDL/verilog
(schematic)
Gate netlist
specification
Synopsys
behavior
registertransfer
logic
(schematic)
circuit
Transistor netlist
layout
Modern VLSI Design 3e: Chapter 1
week1-18
Cadence
Partly from 2002 Prentice Hall PTR
ASIC: Hierarchical name
Interior view of a component:

components and wires that make it up.
Exterior view of a component = type:


body;
pins.
cout
a
Full
adder
b
Modern VLSI Design 3e: Chapter 1
week1-19
sum
cin
Partly from 2002 Prentice Hall PTR
ASIC:Instantiating component types
Each instance has its own name:


add1 (type full adder)
add2 (type full adder).
Each instance is a separate copy of the type:
cout Add2.a
Add1.a
a Add1(Full
adder)
b
Modern VLSI Design 3e: Chapter 1
sum
a Add2(Full
adder)
b
cin
week1-20
sum
cin
Partly from 2002 Prentice Hall PTR
Net lists and component lists
Net list:
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Modern VLSI Design 3e: Chapter 1
Component list:
top: in1=net1 n1=topin1
n2=topin2 n3=topine
out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1
xin2=topin2
xin3=botin1 B=net2
out=net3
i2: in=net3 out=outnet
week1-21
Partly from 2002 Prentice Hall PTR
Component hierarchy
top
i1
Modern VLSI Design 3e: Chapter 1
xxx
week1-22
i2
Partly from 2002 Prentice Hall PTR
Hierarchical names
Typical hierarchical name:

top/i1.foo
component pin
Modern VLSI Design 3e: Chapter 1
week1-23
Partly from 2002 Prentice Hall PTR
Layout and its abstractions
Layout for dynamic latch:
Modern VLSI Design 3e: Chapter 1
week1-24
Partly from 2002 Prentice Hall PTR
Stick diagram
Modern VLSI Design 3e: Chapter 1
week1-25
Partly from 2002 Prentice Hall PTR
Transistor schematic
Modern VLSI Design 3e: Chapter 1
week1-26
Partly from 2002 Prentice Hall PTR
Mixed schematic
inverter
Modern VLSI Design 3e: Chapter 1
week1-27
Partly from 2002 Prentice Hall PTR
Lecture 3
Overview of VLSI (cont’d)
Jan. 10 2003
Modern VLSI Design 3e: Chapter 1
week1-28
Partly from 2002 Prentice Hall PTR
Overview
Why VLSI?
Moore’s Law.
ASIC: Abstraction and Hierarchy.
FPGA: cheaper ASIC
Modern VLSI Design 3e: Chapter 1
week1-29
Partly from 2002 Prentice Hall PTR
Characteristics of ASIC
Expensive
Many cycles of design: Simulation,
synthesis
Design for testing (DFT)
Modern VLSI Design 3e: Chapter 1
week1-30
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 1
week1-31
Partly from 2002 Prentice Hall PTR
Layout of ASIC
Pentium IV
Technology:
Area:
Speed:
Power:
Modern VLSI Design 3e: Chapter 1
week1-32
0.13 um
35 mm square
2.2GHz
55 W
Partly from 2002 Prentice Hall PTR
Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
Throughput,
design time
registertransfer
Function units,
clock cycles
logic
Literals,
logic depth
transistors
circuit
nanoseconds
rectangles
layout
microns
Modern VLSI Design 3e: Chapter 1
week1-33
cost
Partly from 2002 Prentice Hall PTR
CAD Tools
English
VHDL/verilog
(schematic)
Gate netlist
specification
Synopsys
behavior
registertransfer
logic
(schematic)
circuit
Transistor netlist
layout
Modern VLSI Design 3e: Chapter 1
week1-34
Cadence
Partly from 2002 Prentice Hall PTR
Characteristics of FPGA
Programmability
Simulation, synthesis
Test
Modern VLSI Design 3e: Chapter 1
week1-35
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 1
week1-36
Partly from 2002 Prentice Hall PTR
Layout of FPGA
Modern VLSI Design 3e: Chapter 1
week1-37
Partly from 2002 Prentice Hall PTR
Top-down vs. bottom-up design
Top-down design adds functional detail.

Create lower levels of abstraction from upper levels.
Bottom-up design creates abstractions from lowlevel behavior.
Good design needs both top-down and bottom-up
efforts.
Modern VLSI Design 3e: Chapter 1
week1-38
Partly from 2002 Prentice Hall PTR
Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
Throughput,
design time
registertransfer
Function units,
clock cycles
logic
Literals,
logic depth
transistors
circuit
nanoseconds
rectangles
layout
microns
Modern VLSI Design 3e: Chapter 1
week1-39
cost
Partly from 2002 Prentice Hall PTR
CAD Tools
English
VHDL/verilog
(schematic)
Gate netlist
specification
behavior
registertransfer
logic
(schematic)
circuit
Transistor netlist
layout
Modern VLSI Design 3e: Chapter 1
Xilinx Foundation tools
week1-40
Partly from 2002 Prentice Hall PTR
Contents of the Course
ASIC
FPGA
Transistor and Layout
Gate and Schematic
Systems and VHDL/Verilog
Modern VLSI Design 3e: Chapter 1
week1-41
Partly from 2002 Prentice Hall PTR
Contents of the Course (cont’d)
2 ASIC labs
Transistor/Layout
2 FPGA labs
(Cadence)
Gate and Schematic
Systems/VHDL
Modern VLSI Design 3e: Chapter 1
(Xilinx
Foundation)
(Synopsys)
week1-42
Partly from 2002 Prentice Hall PTR
The Future Is Not
What It Used To Be
Modern VLSI Design 3e: Chapter 1
week1-43
Partly from 2002 Prentice Hall PTR
Future of VLSI
Nanotechnology
Biotechnology
Information technology
Modern VLSI Design 3e: Chapter 1
week1-44
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 1
week1-45
Partly from 2002 Prentice Hall PTR