CS2204
Digital Logic and
State Machine Design
Introduction to VHDL
Haldun Hadimioglu
Spring 2014
Outline
Introduction
Language Overview
VHDL Details
Conclusions
Future Directions
NUDT Tianhe-2 supercomputer
Fastest computer in world : 3,120,000 cores
1.024 Peta Bytes of RAM memory
12.4 Peta Bytes of disk space
Acknowledgements
John Wakerly, Cisco Systems, Stanford University
Vijay Polavarapu, Polytechnic University
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Introduction
VHDL is a hardware description language (HDL)
We use VHDL to write a program
A VHDL program describes hardware
Just like a schematic describes hardware
A VHDL program describes a chip
An HDL program is used to develop a chip
Design
Synthesis
Simulation of chip
Intel 8-Core Xeon
7500 die with 2.3
billion transistors
Why an HDL program, why not schematics ?
Real life circuits are too complex to be designed
(described) by schematics
There would be too many and complex schematics
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Introduction
VHDL was developed in the 1980s under Department of
Defense (DoD) sponsorship
Mandated for federally-sponsored VLSI designs
VHDL stands for ?
VHSIC Hardware Description Language
VHSIC : Very High Speed Integrated Circuit
VHSIC was a DoD research program to encourage research on
high-speed integrated circuit (chip) technologies
Today VHDL is widely used across the industry, around
the world
Established as IEEE standard IEEE 1076 in 1987
Extended in IEEE standard IEEE 1164 in 1993
In 1996, IEEE 1076.3 became a VHDL synthesis standard
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Introduction
VHDL has ADA flavour
ADA is a software language developed under
the DoD sponsorship in the 1980s
Another common HDL language : Verilog
HDL
Verilog has C flavour
Knowing one HDL language helps one learn
another HDL language faster
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Introduction
A VHDL program is a collection of modules
Top-down design (hierarchical designs) for large
projects
Designs described at various levels of abstraction
More details at lower levels
Block-based (modular) design
Team-based design
Each team member works on a different block (module)
Core-based design
Complex blocks (modules) can be licensed as VHDL programs
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Language Overview : Basics
Software : Statements are executed sequentially
The sequence of statements is significant, since they are executed in
that order
Java, C++, C, Ada, Pascal, Fortran,…
Hardware : Events happen concurrently
A software language cannot be used for describing and simulating
hardware
Concurrent software languages cannot be used either
Because we do not have powerful tools yet
Programs in C/C++, etc. will be converted to hardware in the future
It is already done for
Matlab
LabVIEW
C++
Modified C++ language (SystemC)
C
Catapult C from Mentor Graphics
works on ANSI C++ and SystemC
Vivado from Xilinx works on C
First these programs are converted to HDL programs and then to
hardware
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Language Overview : Basics
VHDL is STRONGLY typed
VHDL is not case sensitive
“A” or “a” does not matter
IBM BG/Q supercomputer
microprocessor die with 1.47
Billion transistors
A VHDL program describes a digital
system
A digital system consists of blocks
A VHDL program is a collection of modules
A module consists of an entity and an architecture
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Language Overview : Module
Entity: shows inputs and outputs
The black box view of the module
Architecture : internal description : implementation
It can be written in one of three different detail levels
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Language Overview : Module
Sound the alarm if
A VHDL program
A text file
(caralarm.vhd)
 the engine is on and
 the belt is not fastened
A Schematic
A schematic sheet
(caralarm.sch)
entity declarations
architecture definition
engine
AND
alarm
NOT
belt
alarm = engine belt
CS2204 Digital Logic &
State Machine Design
Spring 2014
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_1164.all;
entity caralarm is
port (
engine: in STD_LOGIC;
belt: in STD_LOGIC;
alarm: out STD_LOGIC
);
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
library IEEE;
entity caralarm is
port (
engine: in STD_LOGIC;
belt: in STD_LOGIC;
alarm: out STD_LOGIC
);
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
Language Overview : Xilinx VHDL Programs for Car Alarm Circuit
end caralarm;
end caralarm;
architecture caralarm_dataflow of caralarm is
architecture caralarm_dataflow of caralarm is
begin
begin
alarm <= engine and not belt ;
alarm <= ‘1’ when engine = ‘1’ and belt = ‘0’
else ‘0’ ;
end caralarm_dataflow ;
end caralarm_dataflow ;
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Language Overview : Full Adder VHDL Program
Data-flow description of the Full Adder circuit :
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
ki
mi
ci
si
Full
Adder
si = ki mi ci + ki mi ci + ki mi ci + ki mi ci
co = ki mi + ki ci + mi ci
co
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State Machine Design
Spring 2014
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Language Overview : VHDL System Description
A VHDL program describes a system
A system is a digital system
A system is a collection of
one or more modules
A module consists of
an entity and
an architecture
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State Machine Design
Spring 2014
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Language Overview : Design Flow
VHDL compiler analyzes VHDL code for syntax errors
and checks for compatibility with other modules
Synthesizer converts VHDL program to a circuit with
components
Place and route fits the circuit to a die
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State Machine Design
Spring 2014
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VHDL Details : Entity Syntax
The entity describes the black-box view
The entity declares ports
Inputs and outputs
Digital circuit input signals
Digital circuit output signals
Syntax :
entity caralarm is
port (
engine: in STD_LOGIC;
belt: in STD_LOGIC;
alarm: out STD_LOGIC
);
end caralarm
entity entity-name is
port (signal-names : mode signal-type ;
signal-names : mode signal-type ;
….
signal-names : mode signal-type)
end entity-name ;
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State Machine Design
Spring 2014
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VHDL Details : Architecture Syntax
The architecture describes the internal operations
By means of concurrent statements that use
Signals inherited from the entity
Variables used in functions, procedures and processes
architecture architecture-name of entity-name is
type declarations
signal declarations
constant declarations
function definitions
component declarations
begin
architecture caralarm_dataflow of caralarm is
concurrent statement
begin
alarm <= engine and not belt ;
….
end caralarm_dataflow ;
concurrent statement
end architecture-name ;
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State Machine Design
Spring 2014
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VHDL Details : Full Adder Example
entity entity-name is
port (signal-names : mode signal-type ;
signal-names : mode signal-type ;
…..
signal-names : mode signal-type) ;
end entity-name ;
architecture architecture-name of entity-name is
type declarations
signal declarations
constant declarations
function definitions
component declarations
begin
concurrent statement
….
concurrent statement
end architecture-name ;
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State Machine Design
Spring 2014
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VHDL Details : Types
Types are required for every
© IBM
Signal
Variable
Function parameter
Function result
IBM dual-core BlueGene/L
microprocessor die & its chip
Type specifies a set/range of values for an object and a set of
operators associated with it
Predefined types
User defined types
Types must match in
Assignment statements
Comparisons
Function calls
CS2204 Digital Logic &
State Machine Design
IBM BlueGene/L Supercomputer
Spring 2014
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VHDL Details : Types
Predefined types
bit
bit_vector
boolean
character
integer
real
string
time
Intel dual-core Itanium 2 1.72-billiontransistor die & its wafer
User-defined types
Most commonly used one : Enumerated types
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State Machine Design
Spring 2014
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VHDL Details : Types
Enumerated type is defined by listing its values
User defined enumerated type :
type type-name is (value-list) ;
type COLOR is (RED, ORANGE, YELLOW, BLUE, INDIGO, VIOLET) ;
Subtypes of a type allowed :
subtype subtype-name is type-name start to end ;
subtype LONGWAVE is color RED to YELLOW ;
subtype subtype-name is type-name start downto end ;
Constants are allowed :
constant constant-name : type-name := value ;
constant BUS_SIZE : integer := 32 ;
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State Machine Design
Spring 2014
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VHDL Details : Predefined Operators
Boolean operations
And
Or
Nand
nor
xor
xnor
Not
AND
OR
NAND
NOR
Exclusive OR
Exclusive NOR
Complement
Intel Xeon E7 10-core die at 32 nm
process with 2.6 billion transistors
AMD Bulldozer
8-core die
with 1.2 billion
transistors
CS2204 Digital Logic &
State Machine Design
Intel Xeon E7 wafer
Spring 2014
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VHDL Details : Predefined Operators
Integer operations
+
addition
subtraction
*
multiplication
/
division
mod modulo division
rem modulo remainder
abs absolute value
**
exponentiation
Cray Titan Supercomputer the 2nd
fastest computer in the world with
AMD and TESLA chips
7.1 Billion transistors
NVIDIA TESLA GPU chip
World’s densest chip
CS2204 Digital Logic &
State Machine Design
Spring 2014
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VHDL Details : Libraries
Libraries keep information about a project
The collection of libraries maintains the state of the
design
Intermediate files used in analysis, simulation and synthesis
Previously analyzed entities and architectures
Entity and architecture definitions for different modules can be
in different files
IBM Power 7 8–core
die with 1.2 billion
transistors
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State Machine Design
Spring 2014
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VHDL Details : Library
Compiler maintains a “work” library
VHDL compiler generated information about a
project
To keep track of definitions via entity and architecture
names
It also contains analysis results
No need to explicitly include in the VHDL program
Library work ;
Resource library contains shared definitions
IEEE standard definitions library must be included
in the VHDL program
Library ieee ;
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State Machine Design
Spring 2014
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VHDL Details : Package
A package contains definitions of objects
Signal
Type
Constant
Procedure
Component declarations
Standard logic defined by a “package”
IEEE 1164 STD_LOGIC
Intel 8-Core Poulson (Itanium)
die with 3.1 billion transistors
Must be included in the VHDL program
Keyword “use” needed to specify a package
Use ieee.std.logic.1164.all
Uses all definitions in the ieee library containing package
std.logic.1164
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State Machine Design
Spring 2014
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VHDL Details : Standard Logic Types
Commonly used IEEE-1164 types:
STD_LOGIC (one bit)
STD_LOGIC_VECTOR(range) (multi-bit vector)
INTEGER (built-in integer type)
library IEEE;
Compiler knows where to
find this (system-dependent)
use IEEE.std_logic_1164.all;
entity caralarm is
Library
name
port (
engine: in STD_LOGIC;
belt: in STD_LOGIC;
Package name
alarm: out STD_LOGIC);
Use all
definitions
in package
end caralarm;
architecture caralarm_dataflow of caralarm is
begin
alarm <= engine and not belt ;
end caralarm_dataflow ;
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State Machine Design
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VHDL Details : Design Hierarchy Levels
Structural
Explicit components and the connections between
them are defined
It is the same as schematic design
The VHDL programmer does schematic design in text
Dataflow
Most statements are assigning expressions to signals
The tools are heavily involved in converting the text to
hardware
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
Behavioral
An algorithm that describes the circuit’s output is
developed
The tools may not be able to convert the text to hardware
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State Machine Design
Spring 2014
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VHDL Details : Structural Level
A structural description is just like the schematic
All components and interconnections are described
It is a replica of the schematic !
It is not practical !
I0
2-to4
DCD
Y0
Entity Part :
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
Y1
Y2
V2to4dec
EN
Y3
I1
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State Machine Design
Spring 2014
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VHDL Details : Structural Description of a 2-to4 Decoder
 All components and interconnections are described
 Includes component statements
A component statement is a concurrent statement
Architecture Part :
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
2-to-4 Decoder Schematic
Built-in library
component
Positional
correspondence
with component
definition
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State Machine Design
Spring 2014
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VHDL Details : Dataflow Level
Dataflow Description
The detail is less compared with structural
description
Data dependencies described, not the components and
connections
Concurrency is used to model parallel operations of
interconnected hardware elements
Concurrent statements include assignment and select
statements
Structural (very detailed)
Dataflow (less detailed)
“when-else”
Behavioral (least detailed)
“with-select”
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State Machine Design
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VHDL Details : Dataflow Description of a 3-to-8 Decoder
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
Y_L0
A0
Y_L1
A1
Y_L2
A2
3-to-8
DCD
Entity Part :
G1
Y_L5
G2A_L
Y_L6
G2B_L
CS2204 Digital Logic &
State Machine Design
Y_L3
Y_L4
Y_L7
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VHDL Details : Dataflow Description of a 3-to-8 Decoder
Architecture Part :
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
Y_L0
A0
Y_L1
A1
Y_L2
A2
3-to-8
DCD
Y_L3
Y_L4
G1
Y_L5
G2A_L
Y_L6
G2B_L
Y_L7
All assignment statements operate concurrently
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State Machine Design
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VHDL Details : 3-to-8 Decoder Translation to Hardware
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State Machine Design
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VHDL Details : Behavioral Level
Behavioral description
May not be synthesizable
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
May lead to a very large circuit
Primarily used for simulation
Normally uses VHDL “processes”
Each VHDL process executes in parallel with
other VHDL processes and concurrent statements
But “sequential” statements can be used within a
process
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State Machine Design
Spring 2014
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VHDL Details : Process
Sensitivity List
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
A sequence of sequential
statements
Activated when any signal in
the sensitivity list changes
Primarily a simulation concept,
but can be synthesized
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State Machine Design
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VHDL Details : Behavioral Description of a 3-to-8 Decoder
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
Y0
A0
Y1
A1
Y2
A2
3-to-8
DCD
G1
Y5
G2
Y6
Y7
G3
CS2204 Digital Logic &
State Machine Design
Y3
Y4
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VHDL Details : Another Behavioral Description of a 3-to-8 Decoder
Y0
A0
Y1
A1
Y2
A2
3-to-8
DCD
Y3
Y4
G1
Y5
G2
Y6
G3
Y7
May not be synthesizable
May have a slow or inefficient realization
Structural (very detailed)
Dataflow (less detailed)
Behavioral (least detailed)
But fine for simulation and verification
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State Machine Design
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VHDL Details : Is it always VHDL-only System Description ?
One can mix schematic and VHDL
Xilinx example
1. Start a schematic project
2. Write a VHDL program
3. Convert the VHDL program to a Xilinx
macro (Custom Design Block, CDB)
4. The macro is appended to the component
library list
5. Place the CDB in the schematic just like
any other Xilinx component
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State Machine Design
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Conclusions
VHDL simplifies design of complex digital circuits
VHDL allows core-based, top-down, team-based design
VHDL and other HDLs will be used in foreseeable
future as chip densities increase
Sophomores will learn more VHDL/Verilog HDL in the
future
Eventually, C/C++/Matlab/LabVIEW/Java/…
programs will be converted to hardware
We will use C/C++/Matlab/LabVIEW/Java/… to design chips
The key is developing powerful CAD tools
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State Machine Design
Spring 2014
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Future Directions : Moore’s Law will Continue to Hold
In spite of claims that it will not continue to hold
3-D transistors and 3-d chips will help Moore’s law continue to hold
www.ieee.org
Power must be
controlled
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State Machine Design
Spring 2014
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Future Directions : Intel ‘s Past Roadmap
AMD Tahiti GPU chip with
4.313 Billion transistors
Intel 62-core Xeon Phi processor 2012 5,000,000,000
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State Machine Design
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Future Directions : Power Density a Major Concern !
 Power Density was Increasing Exponentially !
1000
Power was doubling every 4 years
Rocket
Nozzle
Watts/cm 2
Nuclear Reactor
100
Pentium® 4
Pentium® III
Pentium® II
Hot plate
10
Pentium® Pro
Pentium®
i386
i486
Process Length
1
1.5m
1m
0.7m
0.5m
0.35m
0.25m
0.18m
0.13m
0.1m
0.07m
Courtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred
Pollack, Intel Corp. Micro32 conference key note - 1999. Courtesy Avi Mendelson, Intel.
CS2204 Digital Logic &
State Machine Design
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Future Directions : Power Density a Major Concern !
www.nanowerk.com
 Power Density was Increasing Exponentially !
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State Machine Design
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Future Directions : Microprocessor speed
The microprocessor speed was doubling every two years until multi-core
processors emerged
The processor speed was increasing 50% a year !
But, memory speed has been increasing 10 % a year !
Microprocessor speed for an application depends on
Number of operations in the application (lower better)
The quality of the code
Number of parallel operations performed (higher better)
Do more operations in parallel
Perform each operation faster
Because of Moore’s Law : transistors are smaller and wires are shorter
Higher clock frequencies
Until 2005 increasing the clock frequency was the main way to increase
the speed
Power consumption (heat generation) increases with the frequency
Heat generation increases with the power consumption
The chip has to be cooled by
A heat sink or a fan or a liquid
Since 2005 power consumption changed way to increase speed
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State Machine Design
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Future Directions : Multi-Core Microprocessors
Since 2005 microprocessor speed increase depends
on
Number of operations in the code (the quality of the code)
Number of parallel operations performed
Multi-core microprocessors with reduced frequency consume
less power (generate less heat)
Two/Four/Eight cores perform more operations in parallel
The speed increase continues into the future with more cores on chip
Clock frequency
Number of cores per chip doubles every two years
The memory can become a bottleneck
The memory speed increases 10% a year
More cores increase the demand on the memory
The memory wall problem
Parallel Programming has to be improved dramatically
Parallel programming wall
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State Machine Design
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Future Directions : Multi-Core Microprocessors
 Double number of cores every two years
Make sure to handle
errors due to
Alpha particles, neutrons
Defective transistors
Make sure to handle
Power Wall
Memory Wall
Parallel programming Wall
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State Machine Design
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CS2204 Digital Logic &
State Machine Design
Scalable High Performance Main
Memory System Using PCM
Technology, Moinuddin K. Qureshi,
et.al., ISCA 2009, IBM
From Intel
www.anandtech.com
Intel Technology Journal, November 2005
Future Directions : Intel & IBM Vision for Next 5-8 Years
Intel
Spring 2014
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Future Directions : Next 5-8 Years
Applications
Intel : Recognition, Mining, Synthesis as platform 2015
Workload Model (on massively parallel core chips)
IBM : Presence information, knowing where and things are and
how to best match them, people are sensorized
Microsoft : Intention machine, computer predicts user
intentions and delivers useful information
CMU : Computational thinking, computer science based approach
to solving problems, designing systems, understanding human
behavior
Traditional computing will continue
A C/C++/Java/.. program for an application becomes Software
A compiler generates the machine language program file
A new type of computing
A C/C++/Java/.. program for an application becomes Hardware
A hardware compiler generates the GDS II file (the chip layout)
The result is a custom chip
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State Machine Design
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Future Directions : New Computing Types ?
Any other new possibility ?
A C/C++/Java/.. program for an application becomes Hardware
A CAD tool generates the bit file to reconfigure the FPGA
There can be more opportunities with FPGA chips !
Xilinx Vivado
works on C
They are increasingly used in commercial products !
FPGAs are becoming cost competitive with microprocessors
FPGAs are becoming speed competitive with custom chips
FPGAs are used for applications where
Speed and programmability matter
Latest FPGAs also have microprocessor cores
They can run software as well
The application is divided into software and hardware
A machine code that is run by the cores and
A bit file to program the reconfigurable areas
Hybrid computing
These cores can be hard or soft cores
Hard means the manufacturer places a specific core on the die
Soft means the user places any core any where on the die
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State Machine Design
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Future Directions : New Computing Types
A C/C++/Java/.. program becomes
Xilinx Vivado
works on C
Part software and part hardware
FPGA with cores and reconfigurable areas runs applications
Software is run by processor cores and
Hardware is in the reconfigurable area
Hybrid computing
When such an FPGA runs an application, some operations are in hardware
and simultaneously some operations in software
Processor core
to run software
Reconfigurable area
to do operations in
hardware
These FPGAs are available
now but we need much
better tools
Software tools (compilers) and CAD tools must merge
Reconfigurable areas & cores can allow recovering from errors due to
Alpha particles, neutrons
Defective transistors
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State Machine Design
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Future Directions : New Computing Types
In summary, in the future a C/C++/Java/.. program will be converted to
Software (like today)
C++ programs become software, the machine code
All operations happen in software !
Xilinx Vivado
works on C
Hardware
C++ programs become custom chips
All operations happen in hardware !
Hardware (better than what we have today)
C/++ programs become hardware, the bit file for an FPGA
All operations happen in hardware !
Part hardware and part software
C/C++ programs run on FPGA chips with processors and configurable areas
Some operations are in hardware and simultaneously some operations in software
Software is run by processor cores
A machine code that is run by processors
Hardware is in the reconfigurable area
A bit file to program the reconfigurable areas
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State Machine Design
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Future Directions : Year 2020
SEMATECH : consortium of semiconductor
manufacturers from America, Asia and Europe
SEMATECH predictions for year 2020 (from its
2012 International Technology Roadmap for
Semiconductors (ITRS) study)
Clock speed : 5.3 GHz
Number of transistors on a microprocessor chip : 35 Billion
32Gbit DRAM chips
Process length : 11.9 nm
http://www.sematech.org
Make sure to handle errors due to
Alpha particles, neutrons
Defective transistors
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State Machine Design
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Future Directions : 2020 and Beyond
A PC in 2020 ?
Electronic with chips
IBM Deep Blue
1997
Electronic with chips
30 cores +
480 special chips
IBM Watson 2011
Electronic with chips
2880 cores & 0.08 PFLOPS
+ 16 TB RAM
Thinking ?
CS2204 Digital Logic &
State Machine Design
Same raw
processing power
as human brain
20 PFLOPS +
2.5 Peta (1015) 33 Exa (1018)
Bytes
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Future Directions : 2020 and Beyond
There are three computers at or higher speed than the
raw speed of the human brain
Thinking ?
NUDT Tianhe-2 supercomputer
Fastest computer in world : 3,120,000 cores
1.024 Peta Bytes of RAM memory
12.4 Peta Bytes of disk space
NUDT Tianhe-2 supercomputer with max speed of (54 PFLOPS) (54 x 1015 FLOPS)
Third computer at or higher speed than human brain
(54,000,000,000,000,000 floating-point operations a second, FLOPS)
(54,000,000,000,000,000 real number calculations a second)
It does not have same raw processing power as human brain because its memory
size is smaller than human brain memory : 2.5 PBytes – 33 Exa (1018) Bytes
IBM Sequoia & Cray Titan are first two computers at or higher speed of human brain
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State Machine Design
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Future Directions : 2020 and Beyond
Future Computers That Are 'Normally Off'
Advanced spin-transfer torque
magnetoresistive random access
memory (STT-MRAM) technology
to create a new type of computer :
A "normally off" one
Spintronics couples magnetism
with electronics at the quantum
mechanical level
ACM TechNews April 14, 2014
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State Machine Design
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Future Directions : New Systems
The first carbon nanotube computer has been built
Only carbon nanotube transistors used
From : Nature, September 25, 2013
IBM’s A braininspired computer
powered by what
it calls “electronic
blood”
BBC News,
October 18, 2013
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State Machine Design
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Future Directions : Memcomputing
Processing and memory on the same chip
Passive electronic components that have the memory capability
Both processing and nonvolatile memory capability !
Brain like, analog and self-healing computing on a chip
Memristors : Components relating electric charge and magnetic flux
The missing fourth electronic component
Resistors, capacitors and inductors
They have storage capability
FPGAs can be implemented with memristors !
Memcapacitors
They have storage capability
Meminductors
They have storage capability
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State Machine Design
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Future Directions : Hybrid Switching Elements
CMOL : A circuitry composed of CMOS and molecular nanodevices
A closer look at FPGA-like
reconfigurable logic circuits
Interface between CMOS and nanodevices
Figures from :
Konstantin K.
Likharev
A larger view of FPGA-like reconfigurable logic circuits
Two CMOS cells and a nanodevice
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State Machine Design
Spring 2014
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Future Directions : Possible New Structures
Nanotechnology
Programmable materials
NEMS
Bio NEMS
Nano medicine
Drug delivery
Smart diagnosis
1 Watt supercomputer
IBM Blue Gene/L molecular dynamics demo
Quantum computing
Molecular computing
Molecular self assembly
Testing of molecular structures
Adaptive molecular structures
Merger of bio and non-bio structures
Synthetic biology
CS2204 Digital Logic &
State Machine Design
www.ibm.com
Nanocomputing
Spring 2014
Page 59
Future Directions : 2020 and Beyond
Will hardware and software be developed separately
like today ?
How will software be developed for nano systems ?
Quantum software ?
Molecular software ?
Biosoftware ?
How will hardware be developed for nano systems ?
VHDL or Verilog HDL or C or C++ or ?
Developing tools is critical
Simulation of
protein
molecules
folding on a
supercomputer
Iron atoms
on copper
with electron
movement
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Possible New Structures
Microelectromechanical systems, MEMS, with
computing elements
Microembedded systems
Smart Dust at UC Berkeley
Bio MEMS
UC Berkeley
Sensor &
Actuator
Center
Micro bio/chemistry lab on a chip ≡ Bio chip
Camera pill to make diagnosis in the body
Sugar level detector in bloodstream
Optical sensor in the retina to restore vision
Biochip ≡ Lab-on-a-chip ≡ Microfluidic array
The Biochip
Group at Mesa+
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State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
Medical and Biology fields use electronic devices with or without
software today
In future, these devices will be hybrid, i.e. electronic and bio/chemical !
Beam of light to reveal
disease/virus markers
IBM lab-on-a-chip to test
diseases and viruses
Biochips
Lung-on-a-chip : Harvard University
Organ on a chip !!!
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Possible New Structures
Microelectromechanical systems, MEMS, with computing elements
Other structures that can be used for a number of different applications with
or without computing elements
Micromotors
Microcameras
Micromirrors
Microlenses
Microsensors
Micromachines
An all-optical computing chip with micromirrors and microlenses ?
3-D nano-printing
www.microfabrica.com
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Possible New Structures
• Nanotechnology
• Bio NEMS
NYU-Poly Research on Protein nanofibers
• Nano medicine
• Smart drugs
Jin Montclare of Chemical &
Biological Sciences with her
colleagues
Bio-degradable microprocessors
Protein nanofibers can
• Improve drug delivery to treat cancers, heart disorders and Alzheimer's
• Aid in the regeneration of human tissue, bone and cartilage
Protein nanofibers could point way to tinier and more powerful microprocessors
Protein-based microprocessors
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Possible New Structures
Smart drugs
Nano medicine
Nanomotors
Could Churn Inside of
Cancer Cells to Mush :
Penn State
Human body : New frontier
Small antennas on a microchip
receive magnetic fields that propel
chip through blood stream :
Stanford
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State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
1) Nanotube transistor will help bond people with devices
•
Seamless bioelectronic communication between living organisms and devices
2) Part-bio, part-electronic transistor devised
 A nano-sized transistor in a cell-like membrane powered by cell
 In future, transistor can monitor and treat diseases
 It can relay information about disease-related proteins inside cell membrane
 It can lead to new ways to read and influence brain or nerve cells
Seamless marriage of biological and electronic structures
Many medical applications !
Nanotechnology will help improve our lives !
Help for people with disabilities !
But, many ethical issues will emerge
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
Scientist infects himself with a computer virus
A radio frequency ID (RFID) chip implanted into his left wrist
RFID chip gave him secure access to buildings and his mobile phone
He then introduced a computer virus into the RFID chip
The virus contaminated system that was used to communicate with it
This is a software virus !
There will be hardware viruses when we use programmable chips !
Experiment provides a glimpse at the problems of tomorrow
Such implants will be used to increase
the memory capacity or IQ of people !
Nano Bio Machinery will be a new cross-disciplinary field !
Biology, Chem/ChemE, CS/CompE/EE, ME, Medicine !
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
Off the shelf, on the skin : Stick-on electronic patches
for health monitoring
IEEE Spectrum April 2014
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
Demonstration of some of the smallest moving parts
could lead to molecular-scale switches
Molecular-scale machines
IEEE Spectrum April 2014
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State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
A lab-on-a-chip could quickly tell if an infection is the
dreaded antibiotic-resistant MRSA
Molecular diagnostic methods
Food Safety
Medical Diagnostics
Environmental Testing
Eliminating expensive & complicated laboratories
Company : F3
Microfluidics
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
Shrinking Chemical Labs Onto Optical Fibers
Lab-on-fiber sensors could monitor the environment and hunt for
disease inside your body
IEEE Spectrum April 2014
Lab-on-a-chip sensors are ideal for use in rural clinics or
at a patient’s bedside. But their widespread use for other
tasks has long been stalled by seemingly insurmountable
obstacles. For example, in wet environments—such as
inside the body or outdoors—a chip’s metal conductors
easily corrode or short, making the sensor unreliable.
Many chips also contain materials such as arsenic that are
toxic to humans. Their biggest drawback, though, is size.
Today’s power sources, processors, and transmitters take
up at least a few square centimeters—too big to squeeze
through blood vessels.
To overcome many of these problems, some researchers
are seeking to replace a chip’s electronic circuits with
optical ones. By using light rather than current to read
chemical reactions, a photonic chip works reliably in
aqueous solutions, is immune to electromagnetic radiation,
tolerates a wide range of temperatures, and poses fewer
risks to biological tissues.
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Medicine and Biology
Neuromorphic Computing 'Roadmap' Envisions Analog Path to Simulating
Human Brain
Neuromorphic computing
FPAAs
Professor Jennifer Hasler displays a field
programmable analog array (FPAA) board
that includes an integrated circuit with
biological-based neuron structures for
power-efficient calculation.
Hasler’s research indicates that this type of
board, which is programmable but has low
power requirements, could play an important
role in advancing neuromorphic computing.
ACM TechNews April 21, 2014
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State Machine Design
Spring 2014
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Future Directions : Longer Term Predictions
By 2019 a $1000 computer will match the processing
power of the human brain
Raymond Kurzweil, KurzweilAI.net, 9/1/1999
His keynote speech at the Supercomputing Conference (SC06) in
November 2006
The title of his talk is “The Coming Merger of Biological and Non-Biological
Intelligence”
 Singularity point ?
Brain downloads possible by 2050
Ian Pearson, Head of British Telecom’s futurology unit,
CNN.com, 5/23/2005
Computers will be used as virtual brain extensions ?
Direct brain - Internet link ?
CS2204 Digital Logic &
State Machine Design
Spring 2014
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Future Directions : Longer Term Predictions
Hans Moravec, 1998
Many ethical issues will be facing you ! Being prepared will help !
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State Machine Design
Spring 2014
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