XST Synthesis Options
Welcome
If you are new to FPGA design, this module will help you use
XST to synthesize your design optimally
These synthesis techniques promote fast and efficient FPGA
design development
Objectives
After completing this module, you will be able to:
Describe an approach to using XST synthesis options to obtain
higher performance and gain timing closure
Use XST to get the most out of your HDL
Timing Closure
Synthesis Options
These are the most helpful XST synthesis options that can help
you obtain your performance and area objectives
– Synthesis Constraints (Timing-driven synthesis)
– FSM Encoding
– Register Balancing
– Register Duplication
– Keep Hierarchy
– Resource Sharing
These options were covered in the Synthesis Options Video
Synthesis Options
Synthesis Options
– Most common options
HDL Options
– Coding style dependent options
Xilinx Specific Options
– Architecture specific options
XCF Timing Constraints
The XCF file should be placed in your project directory and the
location specified
– Note…if you are not going to use timing constraints for synthesis, it is
recommended that you use the Global Optimization setting
• All Clock Nets…optimizes paths between registers
• Offset In Before…input paths
• Offset Out After…output paths
• Input to Output Pad…combinatorial paths
• Max Delay…(all of the above)
XCF Timing Constraints
Period
– NET netname PERIOD = value [{HIGH | LOW} value];
Offset In/Out
– OFFSET = {IN | OUT} offset_time [units] {BEFORE | AFTER}
clk_name
[TIMEGRP group_name];
For more information about the basics of timing constraints,
refer to the Global Timing Constraints Video
Do not over-constrain your design
XST Switches
LUT Combining
– Recall that the 6-input LUT is actually two 5-input LUTs
– XST looks for functions that use the same five inputs and tries to pair them
– Recommended for Virtex-5, Spartan-6, and Virtex-6 architectures
Reduce Control Sets
– XST will use LUT resources instead of CE and synchronous SET/RESET
– All four flip-flops in one slice share the same CE, SET, and RESET (control set)
– Too many different control sets limits packing
– Recommended for Virtex-5, Spartan-6, and Virtex-6 architectures
XST Features
Inference of SRL for shift register with set/reset
– XST uses SRL resources if the HDL description contains a single
asynchronous, synchronous set, or synchronous reset signal
– This will require extra logic, because SRL does not support a set or reset
functionality
– Inference is done if the shift register has at least four stages
For more information about properly coding your control signals
to get optimum results, please review the Virtex-6 and Spartan-6
HDL Coding Techniques Video
XST Synthesis Options
Optimization Goal
Optimization Effort
Use Synthesis
Constraints File
– Specify constraint
filename
Optimization Goal
Write Timing
Constraints (Export
Constraints)
XST HDL Options
FSM Encoding
Algorithm and Safe
Implementation
Case Implementation
Style
RAM, ROM, and
Multiplexer Extraction
and Style
Shift Register and
Logical Shifter
Extraction
Resource Sharing
XST Xilinx Specific Options
Add I/O Buffers
Max Fanout and
Register Duplication
Equivalent Register
Removal
Register Balancing
Move First and Last
Flip-Flop Stage
Pack Registers into
IOBs
Design Goals and Strategies
Easy way to set multiple synthesis
properties
Choose a design goal and strategy
which maps to a collection of
settings*
– Balanced, Minimum Run-time, Power
Optimization, Timing Performance
A strategy is a specific set of
settings associated with a goal
Some settings are fixed within a
strategy and others can be altered
Effects of Design Goals
Note the Lock symbol
– Indicates that this setting
is governed by the
Design Goal and
Strategy settings and
cannot be changed
without changing the
Strategy
Unlocked settings can
be changed
Notice that the property
display level is set to
Advanced
Best Strategy
(1)
Use the standard XST Synthesis Options that best suit your design
(2)
Use XCF Timing Constraints during synthesis
(3)
Enable packing registers into IOB
– Best aid for I/O timing
(4)
Use the Reduce Control Sets option
− Requires optimum HDL coding
− Supports Virtex-6 and Spartan-6
(5) Use the Design Goals and Strategy
Summary
The basics still apply
– Your HDL coding style can affect synthesis results
– Infer resources whenever possible
– Use synchronous design techniques
– Don’t forget to analyze each synthesis result for logic inference and timing
Take advantage of the synthesis options provided to help you
meet your timing objectives
– Just like we covered in the Synthesis Options Video
Use timing constraints during synthesis to achieve higher
performance
Use the Reduce Control Sets option
Pack registers into IOBs
Last option to consider is the Design Goals and Strategies
Where Can I Learn More?
Software Manuals
– Start  Xilinx ISE Design Suite 12.1 ISE Design Tools 
Documentation  Software Manuals
– This includes the Synthesis & Simulation Design Guide
• This guide has example inferences of many architectural resources
– XST User Guide
• HDL language constructs, coding recommendations, and synthesis options
– Constraints Guide
• All Synthesis and Implementation constraints
Xilinx Education Services courses
– www.xilinx.com/training
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic HDL Coding Techniques, Spartan-6 and Virtex-6 Coding Techniques and
other Free Videos!
Recommended REL Modules
Additional FREE video-based trainings are available for you to
improve your HDL coding style
– Basic HDL Coding Techniques
• Design guidelines (good design practices)
• Best ways to pipeline your design
• Finite State Machine design
– Virtex-6 and Spartan-6 HDL Coding Techniques
• Coding for hardware resources
 SRL, multiplexers, carry logic, and GSR
• Coding to reduce your design size and improve your speed
 Managing your control signals (sets, resets, clocks, clock enables)
 Block RAM and DSP slice
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