Mahalingam Venkataraman (V. Mahalingam)
Address: 12701, N. 50th St, Apt G-11, Tampa, FL-33617
Email: mvenkata@csee.usf.edu
Phone: 1-813-817-0847
Homepage: www.cse.usf.edu/~mvenkata
Objective
Seeking summer internship opportunity in the VLSI Design area.
Academic Qualification
Currently pursuing Ph.D in Computer Science & Engg at Univ of South Florida Expected Graduation May 2008.
Masters of Science in Computer Engineering, 2003-2005, Univ of South Florida, USA, GPA:4.0/4.0
Bachelor of Engineering (CSE) 1999-2003, Sri Venkateswara College of Engg, Univ of Madras, India. Grade: 80%
Areas of Interest
VLSI Design, Statistical Optimization and Computer Arithmetic
TOOLS AND PROGRAMMING SKILLS
Languages: C, C++, VHDL and Verilog HDL; Operating System: Windows and Sun-Solaris
Design Tools: Cadence-Virtuoso, BuildGates, Encounter, Nclaunch, Synopsys Design Compiler, ASTRO, Floorplan
compiler, H-spice, Pathmill, Nanosim and SIS; Others: Latex, Office suites, web design tools, basics of SQL
Work Experience
Teaching assistant, University of South Florida, Tampa, 2004 - 2006.
Research assistant at VCAPP, University of South Florida, Tampa, summer 2004 and summer 2005
Part time research assistant at Waran Research FoundaTion (WARFT), India, 2003
Relevant Graduate Courses
CMOS VLSI, Introduction to VHDL, Computer Architecture, Digital Circuit Synthesis, Modern Processor Design, VLSI
Algorithms & Architectures, Operating Systems, Integer and Nonlinear Programming, Probability Theory, Fuzzy
Logic, Combinatorics Graph Theory and Computer Algorithms
Brief Project Descriptions
1. Variation Aware Design using Fuzzy Programming: Proposed the use of fuzzy mathematical programming for
optimization in the presence of process variations for VLSI design automation problems like gate sizing, clock skew
optimization and other physical design problem with a mathematical programming structure.
2. Efficient and Accurate Logarithmic multiplier design: Proposed the use of operand decomposition to improve the
accuracy of Mitchell’s algorithm based logarithmic multiplication.
3. Superscalar ASIC Architecture for Test Vector Design: Investigated an application specific architecture usage for
test vector generation and fault simulation, to improve the speed and quality of testing DSM designs.
4. Crosstalk Fault tolerant Processor Design: Investigated possible extensions of coding and compression theory
into the processor design, in a bid to eliminate crosstalk noise in multi GHz processing environments.
Peer Reviewed Research Publications
1. V. Mahalingam and N. Ranganathan, “Improving Accuracy in Mitchell’s Logarithmic Multiplication using Operand
Decomposition”, to appear in IEEE transactions on Computers Dec 2006.
2. V. Mahalingam, N. Ranganathan and Justin E. Harlow, “A Novel Approach for Variation Aware Power Minimization
during Gate Sizing”, International Symposium on Low Power Electronic Design, Oct 2006.
3. V. Mahalingam and N. Ranganathan, “An Efficient and Accurate Logarithmic Multiplier based on Operand
Decomposition”. IEEE International Conference on VLSI Design, Jan 2006
4. V. Mahalingam and N. Ranganathan, “A Nonlinear Programming Based Power Optimization Methodology for
Gate Sizing and Voltage Selection”, IEEE International Symposium on VLSI, May 2005
5. N.Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V.Balaji, V.Mahalingam, T.L.
Rajaprabhu, “Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design, 2nd IEEE Workshop on
Electronic Design, Test and Applications (DELTA), Jan 2004
6. N.Venkateswaran, V.Balaji, V.Mahalingam, T.L.Rajaprabhu, "Super Scalar Architecture for Billion Device
Combinational and Sequential Circuit Test Design", 39th IEEE AUTOTESTCON SEP 2003.
7. N.Venkateswaran, V.Balaji, V.Mahalingam, T.L.Rajaprabhu, "Analysis of Bit Transition Count for EDAC Encoded
FSM", 9th IEEE International Online Testing Symposium July 2003.
8. N.Venkateswaran, V. Balaji, V. Mahalingam, T.L. Rajaprabhu, "An encoding scheme for instruction, data and
address in a multi-GHz processor for concurrent Cross-talk Fault detection", IEEE NATW, May 2003.
Scholarships and Awards
Best under Graduate Project award in Computer Science & Engineering Department, Sri Venkateswara College of
Engineering and in the State of Tamil Nadu (out of 227 colleges) awarded by DOTE, Govt. of India.
Fellowship to attend the IEEE VLSI design 2004 and Design Automation Summer School, at DAC 2005.
Awarded IEEE Richard E. Merwin Scholarship by IEEE Computer Society
President IEEE Computer Society, student chapter at USF
Reviewer for IEEE TVLSI, Design Automation Conference, VLSID, ISQED
Awarded merit scholarship for standing 0.1% of all students in 10 th grade mathematics by CBSE, India.
Others
Activities: Student Member of IEEE, ACM
Date of Birth: 12th June 1982
Citizenship: Indian
Visa type: Student F1
Location Preference: None