University Program
UP2 Education Board
Revision 1.0
1
Table of Content
No.
1.0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3.0
3.1
Description
Introduction
UP2 Education Board
UP 2 Education Board Description
EPM7064S Device
9V Battery Connector for battery operation
Centronics-36 Parallel Download Port
Source Power Input
On-Board Voltage Regulator
Oscillator (555 Astable Multivibrator)
EPM7064S Prototyping Header (P1)
DI0 to DI7 8-bit Dual-In-line-Package (DIP) Switch
DO0 to DO7 LEDs
EXPENSION PORT (J1)
Tutorial 1
Tutorial 2
Page
3
3
4
5
5
5
5
6
6
6
7
8
9
11
18
2
1.0
Introduction
The University Program Design Laboratory Package was designed to meet the
needs of universities teaching digital logic design with state-of-the-art development
tools and programmable logic device (PLDs). The package provides all of the
necessary tools for creating and implementing basic digital logic designs, including
the following features:




2.0
UP 2 Education Board
EPM7064S device in an 44-pin plastic J-lead chip carrier (PLCC) package
9V Battery Connector for battery operation
Centronics-36 parallel download port
UP2 Education Board
The UP2 Education Board is a stand-alone experiment board based on the Altera’s
leading device MAX7000S family. Its simple design, when used with the MAX+PLUS
II® software, provides a superior platform for learning digital logic design using highlevel development tools and PLD.
The UP2 Education Board was designed to meet the basic needs of the educator
and the design laboratory environment. The UP2 Education Board supports only
product-term based architecture in the MAX7064S PLD. The EPM7064S device can
be programmed in-system with only a parallel port printer cable.
3
2.1
UP 2 Education Board Description
The UP2 Education Board contains the elements described in this section. Figure 1
shows a block diagram of the UP2 Education Board.
Centronics-36 Parallel Download Port
A
B
C
D
E
F
G
H
I
EPM7064SLC44-10
ON
Figure 1. UP 2 Education Board Block Diagram.
4
2.2
EPM7064S Device
The EPM7064S device, a low-density member of the high-density, high-performance
MAX7000S family, is based on EEPROM elements. The EPM7064S device comes
in a socket-mounted 44-pin PLCC package and has 64 macrocells. Each macrocell
has a programmable-AND/fixed-OR array as well as a configurable register with
independently programmable clock, clock enable, clear, and preset functions. With a
capacity of 1,250 gates and a simple architecture, the EPM7064S device is ideal for
introductory designs as well as combinatorial and sequential logic functions.
For more information on MAX70000 devices, go to the MAX7000 Programmable
Logic Device Family Data Sheet.
2.3
9V Battery Connector for battery operation
To increase the portability of the UP 2 Education Board, a 9V-battery connector is
attached using a 2-pin IDE header labeled +9V. There is no polarity difference
between the two pins of this header. Both pins can accept different polarity from a
9V battery to avoid improper voltage supply connected to the UP 2 Education Board.
The internal rectifier will ensure correct polarity of the supply voltage is applied to the
on-board 5V-voltage regulator.
2.4
Centronics-36 Parallel Download Port
Designs can be easily and quickly downloaded into the UP2 Education Board using
Centronics-36 parallel download port, which can be hardware interfaced to a
standard parallel port using a standard printer cable from a personal computer.
Equivalent ByteBlasterMVTM driver is built on-board for the UP2 Education Board.
This port channels programming or configuration data between the MAX+PLUS II
software and the UP2 Education Board.
Due to design changes are downloaded directly to the devices in the board,
prototyping is easy and multiple design iterations can be accomplished in quick
succession.
2.5
Source Power Input
The Source power input accepts a 2.5-mm x 5.55-mm female connector. The
acceptable DC input is 7 to 37 V DC at a minimum of 350mA. It also accepts AC
power input range from 7 to 37V at a minimum of 350mA.
5
2.6
On-Board Voltage Regulator
The on-board voltage regulator, an LM340T (U3), regulated the source input at 5V.
A green light-emitting diode (LED) labeled POWER is illuminated when currents
flowing from the 5-V DC regulated power source. This indicates that the board is in
good power condition.
2.7
Oscillator (555 Astable Multivibrator)
The UP2 Education Board contains a 555 Timer (U2) operated as an astable
multivibrator. The frequency of the astable is variable which depends on the
requirement of the user. It can be varying from 0.1Hz to about 500KHz depending
on the different components (VR1 and C6) setting. User can vary VR1 or changing
the C6 to obtain the desired frequency. The output of the oscillator drives a global
clock input to the EPM7064S device (pin 43).
2.8
EPM7064S Prototyping Header (P1)
The EPM7064S prototyping header is female header that is located below of the
EPM7064S device of the UP2 Education Board. This header consists of 16-pin,
dual-row 0.1-inch female connectors to provide user to access the device’s signal
pins. The pin numbers for the EPM7064S device corresponding to the female
connectors are listed in Table-1 below:
Table-1. Pin Numbers for each Prototyping Header. Note (1)
Label of Pin Number of
Dedicated Function for
Header EPM7064SLC44-10
UP2 Education Board
0
17
I/O
1
16
I/O
2
18
I/O
3
19
I/O
4
20
I/O
5
21
I/O
6
24
I/O
7
25
I/O
8
26
I/O
9
27
I/O
10
28
I/O
11
36
I/O
Input (GCLRN)
EI1
1
Input (OE2/GCLK2)
EI2
2
VCC
VCC
+5V supply from the board
GND
GND
Board common.
Note:
(1)
EI1 and EI2 are dedicated input pins for EMP7064SLC44-10. These two pins
can only be used as input.
6
2.9
DI0 to DI7 8-bit Dual-In-line-Package (DIP) Switch
In this UP2 Education Board, an 8-bit DIP-switch labeled as S1 contains eight
switches that provides logic-level signals. These switches are pulled-up by 10-K
resistors. Connections to these signals are hard-wired to the EPM7064SLC44-10
chip. The switch output is set to logic 1 when the switch is open and set to logic 0
when the switch is closed (at “ON” position, see Figure-1). The 8 BITS INPUTS
labeled DI0..DI7 corresponding to the pin number of EPM7064SLC44-10 are listed in
Table-2.
Table-2. Pin Numbers for each Dedicated Input. Note (2)
Dedicated Function
Label of
Pin Number of
for UP2 Education
each input EPM7064SLC44-10
Board
DI0
29
Input
DI1
31
Input
DI2
33
Input
DI3
34
Input
DI4
37
Input
DI5
39
Input
DI6
41
Input
DI7
40
Input
Note:
(2)
Warning!! DI0 to DI7 are dedicated as input pins for EMP7064SLC44-10 in
UP2 Education Board. These pins can only be used as input, if either one or
more of these inputs is/are assigned as output and switched to “ON” position,
it can adversely cause malfunction or even cause damage to that particular
pin(s) of EMP7064SLC44-10.
7
2.10
DO0 to DO7 LEDs
The UP2 Education Board contains 8 LEDs that are pulled-up with a 330- resistor
used as dedicated output indicators. An LED is illuminated when logic 0 is applied to
the LED. Table-3 shows the outputs of DO0..DO7 corresponding to the pin number
of EPM7064SLC44-10 on UP2 Education Board.
Table-3. Pin Numbers for each Dedicated Output. Note (3)
Label of
Pin Number of
Dedicated Function for
Each output EPM7064SLC44-10 UP2 Education Board
DO0
14
Output
DO1
12
Output
DO2
11
Output
DO3
9
Output
DO4
8
Output
DO5
6
Output
DO6
5
Output
DO7
4
Output
Note:
(3)
DO0 to DO7 are dedicated output pins for EMP7064SLC44-10 in UP2
Education Board. These outputs can only be driven with logic 0 (active-low)
to turn on the LEDs.
8
2.11
EXPENSION PORT (J1)
EXPENSION PORT J1 is a single row of 0.1-inch spaced holes for accessing signal I/O pins
on the EPM7064S device and ground. This port serves as additional outputs which are
directly connected to the on board DO0 to DO7. Users can use these outputs for any other
applications, for eg., to connect them to external driver(s) such as Darlington-pair drivers to
turn on Relay or Motor. Table 4 shows the labeling convention for the holes.
Table-4. Pin Numbers for each Expansion Port. Note (4)
Dedicated Function
Label of
Pin Number of
for UP2 Education
Hole
EPM7064SLC44-10
Board
A
4
Output
B
5
Output
C
6
Output
D
8
Output
E
9
Output
F
11
Output
G
12
Output
H
14
Output
I
GND
Board common.
Note:
(4)
EXPENSION PORT (J1) consists of holes labeled A to I are dedicated
expansion ports for additional outputs from EMP7064SLC44-10 in UP2
Education Board. These outputs are in true-logic, which logic 0 is applied to
this hole when the corresponding indicator (DO0 through DO7) is turned “ON”.
E.g. logic level at A is the same as logic level at DO7, see Table 3 & 4.
9
University Program
Tutorials using UP2 Education Board
Designing with
MAX+PLUS II
Application Examples
10
3.0
Tutorial 1
3.1(a) Using the GDF design to draw the following 2-to1 Multiplexer. Compile and
simulate its result. Compare the simulation result with 3.1(c)
Figure 1. Equivalent 2-to-1 multiplexer using Graphic Design File (GDF entry).
3.1(b) Repeat the design of 2-to1 Multiplexer using VHDL entry below. Compare the
simulation result with 3.1(c)
ENTITY condsig IS
PORT
(
input0, input1, sel
output
);
END condsig;
: IN BIT;
: OUT BIT
ARCHITECTURE maxpld OF condsig IS
BEGIN
output <= input0 WHEN sel = '0' ELSE input1;
END maxpld;
11
3.1(c) Simulation result for 2-to1 Multiplexer
3.2(a) Using the GDF design to draw the following Single-bit Adder. Compare your
simulation with 3.2(c).
Figure 2. Single-bit Adder using GDF entry.
12
3.2(b) Repeat the design entry using VHDL code below for Single-bit Adder. Compare your
simulation result with 3.2(c)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY vhdl_adder IS
PORT (
Cin, D0, D1
Sum, Cout
END vhdl_adder ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE LogicFunc OF vhdl_adder IS
BEGIN
Sum <= D0 XOR D1 XOR Cin ;
Cout <= (D0 AND D1) OR ((D0 XOR D1) AND Cin) ;
END LogicFunc ;
3.2(c) Simulation result for Single-bit Adder
13
3.3(a) Using the GDF design to draw the following 4-bit Full Adder. Compare your
simulation result with 3.3(b)
Figure 3. 4-bit Full adder using single-bit adder as leaf-cell in GDF format.
3.3(b) Simulation result for 4-bit Full Adder.
14
3.4(a) Using the GDF design to draw the following 4-Bit Multiplier. Compare your
simulation result with 3.4(b).
Figure 4. 4-bit unsigned multiplier using GDF entry.
3.4(b) Simulation Result for 4-bit Unsigned Multiplier.
15
3.5(a) Using the GDF design to draw the following 4-bit Subtractor. Compare your
simulation result with 3.5(b)
Figure 5. 4-bit subtractor using GDF entry
3.5(b) Simulation Result for 4-bit Subtractor.
16
3.6(a) Design a 4-bit Behavioral Counter using Verilog HDL below. Compare your
simulation result with 3.6(b)
module fourbit_behav_counter( d, clk, clear, load, up_down, qd);
// Port
input
input
input
input
input
output
Declaration
[3:0] d;
clk;
clear;
load;
up_down;
[3:0] qd;
reg
[3:0] cnt;
assign qd = cnt;
always @ (posedge clk)
begin
if (!clear)
cnt = 4'h0;
else if (load)
cnt = d;
if (up_down)
cnt = cnt + 1;
else
cnt = cnt - 1;
end
endmodule
3.6(b) Simulation Result for 4-bit Behavioral Counter
17
4.0
Tutorial 2 (Third Brake Light System)
In this tutorial, you will implement a Third Brake Light System using 8 BITS OUTPUT DO0
to DO7 and 8 BITS INPUT DI0 to DI7 of UP2 Education Board.
You need three signals, e.g. DI1, DI3 and DI7 for the Light to operate in one of the following
modes:
(i)
Turn Right
(ii)
Turn Left
(iii) Brake On
(iv)
Idle
Use the following table for each of the operating Modes.
1.1 Turn Right.
Table-1. Turn Right Mode.
Sequence DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
1
1
1
1
1
0
1
1
1
2
1
1
1
1
1
0
1
1
3
1
1
1
1
1
1
0
1
4
1
1
1
1
1
1
1
0
1
Repeat Sequence [1]
1.2 Turn Left.
Table-2. Turn Left Mode.
Sequence DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
5
1
1
1
0
1
1
1
1
6
1
1
0
1
1
1
1
1
7
1
0
1
1
1
1
1
1
8
0
1
1
1
1
1
1
1
5
Repeat Sequence [5]
Note: Since DO0 to DO7 is active-low. Logic ‘0’ applied to these outputs will cause the
LED to be illuminated.
18
Exercise 1 - GDF Entry Design for 2-to-4 Decoder with Active Low Enable
–
–
–
–
Implement a 2-to-4 decoder using GDF Entry for DO4 to DO7 for Table 1 and can be
used for Table 2 for DO0 to DO3 in the reverse order.
Your 2-to-4 decoder should include an Active-Low enable input, when this enable is not
activated, all outputs should be at “1111”.
Create a Symbol for the 2-to-4 decoder.
Simulate your design to get the waveform as shown in Figure-1.
Figure-1 Expected simulation result for 2-to-4 decoder with Active-Low Enable (NENA).
19
Exercise 2 – Design a 4-bit Johnson Counter with Active-Low Preset and Clear.
–
Implement a 4-bit Johnson counter using GDF Entry for DO4 to DO7 as shown in Table3. Notice that DO0 to DO3 is just the image of DO4 to DO7.
–
The expected simulation result is as shown in Figure 2.
Figure-2 Expected simulation result for 4-bit Johnson Counter with active-low Clear and
Preset.
20
1.3
Brake On.
Table-3. Brake-On Mode.
Sequence DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
9
1
1
1
0
0
1
1
1
10
1
1
0
0
0
0
1
1
11
1
0
0
0
0
0
0
1
12
0
0
0
0
0
0
0
0
13
0
0
0
1
1
0
0
0
14
0
0
1
1
1
1
0
0
15
0
1
1
1
1
1
1
0
16
1
1
1
1
1
1
1
1
17
Repeat Sequence [9]
Exercise 3 – Enhance the 4-bit Johnson Counter
–
–
–
Implement the output of Table-3 above using one 4-bit Johnson counter with 8-output and
an Active-Low Enable named NBR using GDF Entry.
When NBR is not activated by logic ‘0’, all DO0 to DO7 should give ‘1111 1111’.
The simulated result for DO0 to DO7 should be as below:
Figure-3 Simulated result for Exercise 3 using a 4-bit Johnson Counter with Active-Low
Enable (NBR).
21
Exercise 4 – Text Entry Design
–
–
–
–
Implement a 2-bit counter using VHDL design entry
Use a VHDL template (look under Template menu while in Text Editor)
The counter must include a Active Low Enable and a Active-High Clear signal.
Create a symbol for this counter.
Sample answer for Exercise 4.
-- Comment for 2-bit Up-Counter.vhd
-- Clearable, and Active-Low Enablable Up Counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY twobitupcounter IS
PORT
(
clk
: IN
clr
: IN
nen
: IN
dataout
: OUT
);
END twobitupcounter;
std_logic;
std_logic;
std_logic;
-- Active-Low Enable
integer RANGE 0 to 3
ARCHITECTURE behaviour OF twobitupcounter IS
SIGNAL count : integer RANGE 0 to 3;
BEGIN
PROCESS (clk, clr)
BEGIN
IF clr = '1' THEN
count <= 0;
ELSIF (clk'event AND clk = '1') THEN
IF nen = '0' THEN
count <= count + 1;
END IF;
END IF;
END PROCESS;
dataout <= count;
END behaviour;
22
To verify your design using VHDL entry, you should get the following result:
Figure-4 Simulated result for 2-bit Up Counter active-low enable (nen) and Clear (clr).
-
Combine your 2-bit Up Counter with 2-to-4 decoder as in Exercise 1 as in Figure 4-1 and
create a symbol for this design.
Figure 4-1. Combination of 2-bit Up Counter and 2-to-4 Decoder.
23
Exercise–5. Implement the Third Brake-Light System with Different Operating Modes.
Table-5. Operating mode for the Third Brake-Light system.
Inputs (S1)
Outputs
Function Mode
DI0 DI3 DI7 NTL NBR NTR
0
0
0
1
1
1
Idle
0
0
1
1
1
0
Turn Right
0
1
0
1
0
1
Brake-On
0
1
1
1
0
1
Brake-On AND Turn Right, Brake-On is selected
1
0
0
0
1
1
Turn-Left
Turn-Left AND Turn-Right, this is an emergency sign, Both
1
0
1
0
1
0
Turn-Left and Turn-Right are selected.
1
1
0
1
0
1
Brake-On AND Turn Left, Brake-On is selected
Turn-Left AND Turn-Right AND Brake-On, again, this is an
1
1
1
0
1
0
emergency sign, Both Turn-Left and Turn-Right are selected.
Note: DI0, DI3 and DI7 will be used to simulate Turn-Left, Turn-Right and Brake-On modes
for Tutorial-1.
-
You may either use three truth tables to implement outputs NTL, NBR and NTR or using
AHDL to implement these outputs.
Create a symbol for this implementation.
Sample Answer for Exercise 5.
SUBDESIGN OP_MODES
(
DI0, DI3, DI7
NTL, NBR, NTR
)
: INPUT;
: OUTPUT;
BEGIN
TABLE
DI0,DI3,DI7
=>
NTL,NBR,NTR; -- Operating
----------0,
0,
0
0,
0,
1
0,
1,
0
0,
1,
1
1,
0,
0
1,
0,
1
1,
1,
0
1,
1,
1
=>
=>
=>
=>
=>
=>
=>
=>
----------1,
1,
1;
1,
1,
0;
1,
0,
1;
1,
0,
1;
0,
1,
1;
0,
1,
0;
1,
0,
1;
0,
1,
0;
Modes
END TABLE;
END;
24
Exercise 6. Combine all Exercises to form a Third Brake Light System.
-
-
In this exercise, you will combine all previous exercises (Exercise 1 to 5) to make a
complete Third Brake Light for a car. The modes of operation for the system will be as
shown in Table-5.
You may use 2 Quad 2-to-1 Multiplexers Package (74157) to select either Turn Left or
Right mode or Brake-On Mode.
Figure 6 shows the example of successful implementation for the Third Brake Lights
System using the combination from Exercise 1 to Exercise 5 above.
Figure 6-1 shows example of GDF entry for the complete Third Brake Lights System.
The simulation result in Figure-6 is based on this design.
Figure 6. Example of simulation result for the complete Third Brake Lights System.
Note: (i)
(ii)
(iii)
(iv)
Turn-Right Mode is based on the sequence in Table-1.
Turn-Left Mode is based on the sequence in Table-2.
Brake-On Mode is based on the sequence in Table-3.
Emergency mode is the combination of Turn-Left AND Turn Right Mode.
25
Figure 6-1. Overview of the Third Brake Light System using GDF design entry.
26
Exercise 7 – Prepare UP2 board for simulation
-
-
Pin assignment (refer to the UP2 Design Laboratory Package User Guide page 5 and 6) is
required before you can have your Third Brake Light System programmed into the UP2
Education Board.
Give the appropriate pin assignment for the 8 LEDs (DO0 to DO7) and DIP switches DI0,
DI3 and DI7 after successful compilation of Figure 6-1.
Click on Assign  Pin/Location/Chip and Figure 7 below will be shown.
Click on Search  LIST and select the signals you wish to assign.
Enter Pin
number
here
Click
Add
here
Figure 7. Assign Pin/Location/Chip for UP2 Education Board.
27
Exercise 7.1. Verify for Pin Assignment.
-
-
Pin assignment is very important to ensure that your design is successfully programmed
into the Altera EPM7064SLC44-10 chip without causing any disruption to the chip and
ensure proper functionality of the design into UP2 Education Board.
After you have finish all pins assignment, go to hierarchy Viewer and look for the ACF
file, e.g. 3rdbrake.acf and you should get the following contents:
CHIP 3rdbrake
BEGIN
|DO6 :
OUTPUT_PIN = 5;
|DO5 :
OUTPUT_PIN = 6;
|DO4 :
OUTPUT_PIN = 8;
|DO3 :
OUTPUT_PIN = 9;
|DO2 :
OUTPUT_PIN = 11;
|DO1 :
OUTPUT_PIN = 12;
|DO0 :
OUTPUT_PIN = 14;
|DI7 :
INPUT_PIN = 40;
|DI3 :
INPUT_PIN = 34;
|DI0 :
INPUT_PIN = 29;
|CLK :
INPUT_PIN = 43;
DEVICE = EPM7064SLC44-10;
END;
-
After completed the pins assignment above, you can recompile your design and open the
Floor Plan Editor to verify for correct pin assignments. Click on this icon
, click on
the Layout menu and select Device View. You will see the device view of the
EPM7064SLC44-10 as in Figure 7-1.
Figure 7-1. Device View of EPM7064SLC44-10 after correct pin assignment is
completed.
28
Exercise 7.2 Programming the UP2 Education Board.
-
After finished assigning the signals to the correct pins of EPM7064SLC44-10, you can
proceed to download your design into the UP2 Education Board.
-
Click on the Device Programming icon
Click Program to start.
and Figure 7-2 will appear as below:
Figure 7-2. Device Programming for the Third Brake Lights System into UP2 Education Board.
29
Exercise 7-3. Examine Results of the Compilation Process.
-
After finished compiling your design, correct any errors associated with the design and
make sure there is no error after recompiling.
-
Click on the Hierarchy Display icon
and open the report files (rpt file), Figure 7-3
will appear; answer the questions in Table 7-3.
Click
here to
read
rpt file
Figure 7-3. Hierarchy Display for the Third Brake Lights System.
Table 7-3. Examine additional Information.
Question
Total flipflops required
Total product terms used
Total shareable expanders used for the design
How many Logic Cells (LC) are used?
How many I/O pins are used?
Input =
What was the Total Compilation time?
What was the Peak memory allocated?
Answer
Output =
30
Exercise 8 – Additional Ideas
Based on your current design, you may do some modification for the
following:
(i) Use more outputs, current design is 8 LEDs of DO0 to DO7, you may use the
Prototyping Header (P1) of UP2 Education Board to make another 12 extra outputs.
(ii) Modify the Brake-On LEDs sequence, current design is based on Johnson Counter.
You may use AHDL design entry and Table as in Exercise 5 to achieve this.
(iii) You may use only one Counter-Decoder block instead of two (see Figure 6-1) to switch
between Turn-Left, Turn-Right and Emergency (Turn Left & Right modes asserted
simultaneously) and use Quad 2-to-1 Multiplexer to switch among the operating modes.
If only one Counter-Decoder is used, you can synchronize Turn-Left & Turn Right
sequence in Emergency Modes. [The only way to synchronize these two modes now is
to assert Brake-On mode, and asserts Turn-Left and Turn Right Modes simultaneously].
Sample Answer.
31
Exercise 1.
Exercise 2. (Refer to simulation result of Figure-2).
Exercise 3. 4-bit Dual Johnson Counter (Refer to simulation result of Figure-3).
32