15. Control Unit
True or False:
1. T/F – The control unit supervises the process of an micro-code moving through the
pipeline.
ANS : T
2. T/F – The fetch, decode, execute etc form the micro-code of a program.
ANS : T
3. T/F – Micro-operation that occur out-of-order can be grouped.
ANS : F
4. T/F – The PC is loaded with address in the IR register for the interrupt-processing step.
ANS : F
5. T/F – Only indirect addressing mode instructions can trigger an extra cycle between
fetch and execution cycles.
ANS : T
6. T/F – Transfer of data between registers is also a type of micro-operation.
ANS : T
7. T/F – Control also involves execution.
ANS : T
8. T/F – The ALU and the data path are controlled by separate control units.
ANS : F
9. T/F – The system bus also has control inputs to monitor the bus.
ANS : T
10. T/F – The number of cycles for all instructions is fixed for a given architecture.
ANS : F
11. T/F – Control signals are Boolean expressions of control inputs.
ANS : T
12. T/F – Control signals to registers are an example of signals within the processor.
ANS : T
13. T/F – The arithmetic and logic operation can cause exceptions that transfer control to
the control unit.
ANS : T
14. T/F – The more complex the architecture is, the more complex is the control unit.
ANS : T
15. T/F – Execution under a condition can be executed in one cycle.
ANS : T
16. T/F – Microprogramming is another version of implementing control signals.
ANS : T
Multiple Choice Questions:
1. The I/O and Memory interfaces are typically defined by
A. Memory unit
B. Control unit
C. System bus
D. None of the above
ANS : C
2. The fetch unit does not keep track of this register
A. MAR
B. MBR
C. Arithmetic registers
D. Program counter
ANS : C
3. Interrupt check test is performed only after
A. Decode stage
B. Fetch stage
C. Execute stage
D. Writeback stage.
ANS : C
4. The first step in an interrupt cycle involves the transfer between
A. PC and MBR
B. MBR and IR
C. IR and PC
D. None of the above
ANS : A
5. This cycle changes with the opcode of the instruction issued.
A. Fetch
B. Indirect
C. Load
D. Execute
ANS : D
6. This register indicates the stage of instruction processing
A. Fetch register
B. Instruction cycle code
C. Condition code D. None of the above
ANS : B
7. This always follows the execution cycle
A. Instruction cycle
B. Commit stage
C. Interrupt cycle
D. Indirect cycle
ANS : D
8. ALU function are activated by
A. ALU unit
B. Register banks
C. Data bus
D. Control unit
ANS : D
9. What signals are used by the control unit to perform non-scheduled operations
A. Clock
B. Commit
C. Flags
D. None of the above
ANS : C
10. This module interfaces to external devices
A. Interrupt module
B. Serial connection module
C. Serial I/O module
D. None of the above
ANS : C
11. The control unit must keep in its control, the stage of
A. Registers
B. Resources
C. All of the above
D. Instruction cycle
ANS : D
12. The disadvantage of hardwired approach is
A. Increase control signals
B. Decrease of number of control bits
C. Boolean functions
D. None of the above
ANS : A
13. The processor decodes the instruction during
A. Bus idle state
B. End of fetch stage
C. Beginning of execution D. None of the above
ANS : A
14. SID signals of Intel 8085 accommodates devices that transmit
A. Serially 1 bit at a time B. In Parallel
C. Sequentially
D. Randomly
ANS : A
15. Control unit has a direct access to this register
A. Architectural registers B. Symbolic registers
C. Instruction register
D. None of the above
ANS : C
16. Decoding is performed for the instruction register to connect to
A. System bus
B. Data bus
C. All of the above
D. Control unit
ANS : D
Fill up the blanks:
1. _______________ are steps of execution of an instruction.
ANS : Cycles
2. The ______________ causes instructions to be fetched from the memory.
ANS : Fetch unit
3. Reading and writing to/from a register cannot happen in the ___________.
ANS : Decode stage
4. In _________________ cycles, the same procedure is repeated every cycle.
ANS : Fetch, Indirect and Interrupt
5. The _______________ cycle always happens after the interrupt cycle.
ANS : Fetch
6. __________ control signal keeps track of the execution time/cycle time.
ANS : Clock
7. The instruction register is also a ______________ input.
ANS : Control
8. _____________ and ____________ are two major components of the control unit.
ANS : , Transfer and control
9. _____________ are handled by the interrupt control module.
ANS : Interrupts
10. _______________ is used to covert the encoded signal for implementation of the
control signal.
ANS : Decoder
11. Control signals between __________ and the processor are sent through the control
bus.
ANS : Registers
12. The ______________ unit takes action based on the result of arithmetic operations.
ANS : Control
13. The ______________signals the start of each machine cycle from the control unit.
ANS : Address Latch Enable
14. The timing of the clock is ______________ by the control unit.
ANS : monitored
15. ALUs can be avoided for ________________.
ANS : Control
16. __________________ involves the control unit to step through the execution of each
program.
ANS : Sequencing