SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
DESIGN A SIMPLE CALCULATOR USING
FPGA
STUDENT
: ANISH PETER (N0704982)
SUPERVISOR
: MAK LIN SENG
PROJECT CODE : JAN2010/ENG/0076
A project report submitted to SIM University
in partial fulfillment of the requirements for the degree of
Bachelor of Engineering
November 2010
Simple calculator using FPGA
Anish Peter
N0704982
TABLE OF CONTENTS
Page
ABSTRACT
4
ACKNOWLEDGEMENT
5
LISTS OF FIGURES
6
LIST OF TABLES
7
CHAPTER 1
INTRODUCTION
8
1.1
Project Background
8
1.2
Project Objectives
8
1.3
Scope of Project
9
CHAPTER 2
LITERATURE REVIEW
11
2.1
Investigation of Project Background
11
2.2
FPGA Overview
11
2.2.1
Principle of FPGA
11
2.2.2
Advantages of FPGA
12
2.3
Selection of Hardware Components
13
2.3.1
Input Device
13
2.3.2
FPGA processing unit
14
2.3.3
Output device
17
2.4
HDL overview and selection
18
2.5
Software selection
19
CHAPTER 3
PROJECT MANAGEMENT
20
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3.1
Initial tasks and schedule
20
3.2
Proposed and actual schedule
21
CHAPTER 4
DESIGN AND IMPLEMENTATION OF SYSTEM
23
4.1
Hardware and tools used in the design
23
4.1.1
FPGA development kit – Xilinx Spartan 3A starter kit
23
4.1.2
PS-2 port and numeric keypad
24
4.1.3
LCD display
25
4.1.4
VHDL
26
4.2
Program design overview
28
4.3
Program modules
30
4.3.1
Top level behavioral
30
4.3.2
PS-2 controller – PS2_ctrl
32
4.3.3
Operator/Operand selection module – Op_sel
36
4.3.4
Calculator module – Calc_unit
39
4.3.5
LCD controller – LCD_control
43
4.3.6
Signal generator - Ce_generator
48
CHAPTER 5
TESTING AND FINALIZATION
49
5.1
LCD controller
49
5.2
Keyboard testbench
49
5.3
Compiling and targeting of VHDL code
50
5.4
Testing the program on the target board
53
CHAPTER 6
CONCLUSIONS AND RECOMMENDATIONS
2
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6.1
Conclusions
55
6.2
Recommendations
55
CHAPTER 7
REFLECTION
56
REFERENCES
58
GLOSSARY
60
APPENDICES
62
APPENDIX 1 – top_level.vhd
62
APPENDIX 2 – calc_unit.vhd
66
APPENDIX 3 – ce_generator.vhd
71
APPENDIX 4 – LCD_control.vhd
72
APPENDIX 5 – op_sel.vhd
86
APPENDIX 6 – ps2_ctrl.vhd
91
APPENDIX 7 – s3astarter.ucf
94
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ABSTRACT
FPGA (Field Programmable Gate Array) is one of the most powerful and successful tools
for the development of real time systems. It is also one of the most widely used. A
calculator is an example of such a real time system. This project aims to design a simple
calculator using FPGA. The calculator would be able to perform basic calculations such
as addition, subtraction, multiplication and division. The system was designed using
VHDL (Very high speed integrated circuit Hardware Description Language). The target
board used was a Xilinx Spartan 3A series, the VHDL codes were targeted to the board
using Xilinx ISE. A numeric keypad was used as the input device and the onboard LCD of
the target board was used as the output device.
The whole system design was divided into 3 phases. The first phase included capturing of
the user inputs, in this case numbers and operators, entered via the numeric keypad. The
second phase would then use the user inputs and perform the requested calculations. The
third phase would display the captured user inputs as well as the calculated results on the
onboard LCD of the target board.
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ACKNOWLEDGEMENT
First of all, I would like to express my sincere gratitude to Mr. Mak Lin Seng, the project
supervisor, for his guidance throughout the development of this project. His
understanding of the problems faced by a part time student and his encouragement made
helped this project to move forward.
Special thanks to Xilinx’s field engineer Mr. Felix Keng in favour of helping to acquire
the necessary hardware for the project.
I would like to thank my family, friends and colleagues for all their support throughout
this project. Thanks to all those who have provided valuable advises and comments during
this project.
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LIST OF FIGURES
Figure 2.2.1: Simplified version of FPGA internal architecture
12
Figure 2.3.1: A PS2 keyboard and a PS2 Numeric Keypad
14
Figure 2.3.2: Spartan 3A and Cyclone 2 target board
16
Figure 2.3.3: Spartan 3A inbuilt LCD
17
Figure 2.5: Xilinx ISE project navigator.
19
Figure 3.1: Initial tasks and schedule
20
Figure 3.2.1: Gantt chart – Introduction and research phase
21
Figure 3.2.2: Gantt chart – Design and development phase
21
Figure 3.2.3: Gantt chart – Troubleshooting and finalization phase
22
Figure 4.1.1: Xilinx Spartan 3A starter kit peripherals
23
Figure 4.1.2.1: PS2 Connector Location and Signals on Spartan 3A board
24
Figure 4.1.2.2: PS2 Keyboard Scan Codes.
25
Figure 4.1.3: Character LCD Interface
25
Figure 4.1.4.1: HDL Modeling Capability
26
Figure 4.1.4.2: VHDL Simulation Modeling
27
Figure 4.2.1: Program flow chart
28
Figure 4.2.2: Block Diagram of the simple calculator
29
Figure 4.3: Program modules
30
Figure 4.3.1: Program modules top-level design
31
Figure 4.3.2.1: Graphic symbol of PS-2 controller
32
Figure 4.3.2.2: PS-2 bus timing waveforms
33
Figure 4.3.2.3: PS-2 UCF location constraints for Spartan 3A
34
Figure 4.3.2.4: PS2_ctrl module program flow
35
Figure 4.3.3: Operand/Operator Selection module
36
Figure 4.3.4.1: Calculator module
39
Figure 4.3.4.2: Calculator module program flow chart
41
Figure 4.3.4.3: Divider core generator IP
42
Figure 4.3.5.1: LCD controller module
43
Figure 4.3.5.2: UCF location constraints for the character LCD
45
Figure 4.3.5.3: LCD character display command set for four-bit mode
46
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Figure 4.3.5.4: DD RAM Hexadecimal Addresses
46
Figure 4.3.5.5: LCD Character set
47
Figure 4.3.5.6: Character LCD interface timing
47
Figure 4.3.6: ce_generator
48
Figure 5.1: LCD simulation testbench
49
Figure 5.2: PS-2 controller testbench
49
Figure 5.3.1: ISE design properties
50
Figure 5.3.2: Hierarchy of sources
51
Figure 5.3.3: Hardware setup
51
Figure 5.3.4: Generation of programming file
52
Figure 5.3.5: iMPACT program succeeded.
53
Figure 5.4: LCD glitch encountered.
54
LIST OF TABLES
Table 2.2.2: Comparison of various platforms
13
Table 2.3.2: Comparison of FPGA Processing Units.
15
Table 2.4: Comparison of Hardware description Languages
18
Table 4.3.3.1: Table 4.3.3.1: Operator selection
37
Table 4.3.3.2: Scan codes used in the ‘Op_sel’ module.
38
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CHAPTER 1
INTRODUCTION
1.1.
Project background
FPGA’s (Field Programmable Gate Arrays) are becoming widely popular due to its ability
to provide solutions that are easily customizable for various platforms and devices. FPGA
is one of the most powerful and successful tools for the development of real time systems.
It is also one of the most widely used. A calculator is an example of such a real time
system. This project aims to study the customizable nature of FPGA’s with the design of a
simple calculator. The simple calculator would be able to perform basic arithmetic
operations. This project looks to explore the various features and advantages of FPGA’s
in the design of platform specific devices.
Throughout history humans have looked for ways to increase and improve their
productivity. One such example is the invention, development and improvement of the
calculator. From mechanical calculators to the latest scientific calculators, all of them
have a most important and unavoidable function. They are all able to perform the four
basic arithmetic operations namely addition, subtraction, multiplication and division. The
project aims at developing such a basic calculator design using one of the latest
technologies available, FPGA.
1.2.
Project Objectives
The objective of this project is to develop a simple FPGA based calculator. The calculator
should be able to perform basic calculations such as addition, subtraction, multiplication
and division. The numbers are punched in via a numerical keypad and the answer is
displayed on the on-board LCD.
The overall objectives of the project includes the evaluation of different types of FPGA
prototyping boards on the market and choose one as a platform to design a simple
calculator that is able to perform basic calculations such as addition, subtraction,
multiplication and division. A selection is to be made from the two available
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programming languages for FPGA, which are VHDL and Verilog Hardware Description
Language. The FPGA development software that comes along with the FPGA board is to
be used to configure the FPGA chip. Usually all development software have option to
program in both VHDL and Verilog.
1.3.
Scope of Project
For the successful completion of the project, different skills were required. Various skills
required were tested during the course of the project.

The project required the acquiring of important ideas and information through
research and analysis. Availability of a lot of reference books based on VHDL and
FPGA helped in the understanding and planning of project deliverables. The
guidelines given by the project supervisor were helpful in finding the right
resources.

Project Management Skills are required for successfully accessing and evaluating
project progress. Setting targets and efficient management of time and resources
are required for the successful completion of the project.

Since there were a lot of documentation to be done during the project, skills on
report writing were also critical. Oral presentation skills would be required during
the final project presentation.

After the selection of the hardware components for this project, it was pretty clear
that Knowledge in Hardware Description Language was the major skill required
for the successful completion of this project. The Hardware Description Language
used in this case was VHDL (Very high speed integrated circuit Hardware
Description Language).
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There was also a need of understanding the different functional blocks and I/O
ports in the Xilinx Spartan 3A target board, as it would be necessary during the
programming phase.

The project also required the thorough understanding of the software used to
program the Spartan 3A target board. In this case it was the Xilinx ISE Design
Suite 11.1.
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CHAPTER 2
LITERATURE REVIEW
2.1
Investigation of project background
The FPGA based calculator required a thorough study and understanding of various
systems included. A basic study of FPGA based systems was a must for developing an
understanding of FPGA’s. The input device, the development board and the output device
used were to be researched and their specs and working understood for the successful
development of the project.
A research and analysis on the different methods and Parts that could be used for the
development of the project was done. Important data and specs about the different
methods and parts that can be used were collected. A final decision was made on the
different methods and parts that were to be used based on the data collected.
2.2
FPGA Overview
System designs using FPGAs (Field Programmable Gate Arrays) is significantly different
from typical ASIC/Processor based system design. Higher density programmable logic
device such as FPGA can be used to integrate large amounts of logic in a single IC. FPGA
has become one of the most successful of technologies for developing systems that
require a real time operation. FPGA logic cells can be used as building blocks to
implement any kind of functionality desired, from low-complexity state machines to
complete microprocessors.
2.2.1 Principle of FPGA
FPGA are two-dimensional arrays of logic blocks and flip-flops with an electrically
programmable interconnection between logic blocks. What makes FPGA different from a
custom IC is that these interconnections consist of electrically programmable switches.
Integrated circuit fabrication technology is used to form metal interconnections between
logic blocks in the case of an IC whereas an FPGA uses multiple level low fan in gates,
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which gives it a more compact design compared to an implementation with two-level
AND-OR logic. Customization and configuration are the abilities that make FPGA stand
out among its competitors. Logic block of an FPGA can be configured in such a way that
it can provide functionality as simple as that of transistor or as complex as that of a
microprocessor. It can used to implement different combinations of combinational and
sequential logic functions. Logic blocks of an FPGA can be implemented by any of the
following: [1]
1. Transistor pairs.
2. Combinational gates like basic NAND gates or XOR gates.
3. N-input Lookup tables.
4. Multiplexers.
5. Wide fan in And-OR structure.
Routing in FPGA’s consists of wire segments of varying lengths that can be
interconnected via electrically programmable switches. Density of logic block used in an
FPGA depends on length and number of wire segments used for routing.[1]
Figure 2.2.1: Simplified version of FPGA internal architecture. [1]
2.2.2 Advantages of FPGA
FPGA’s have many advantages over other platforms. They are flexible, easily
customizable and provide a low cost option [5]. Table 1 shows the comparison of FPGA
with other important platforms in market today.
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Table 2.2.2: Comparison of various platforms
2.3
Selection of hardware components
Research and analysis on the different methods and Parts that can be used for the
development of the project was done. Important data and specs about the different
methods and parts were collected. A final decision was made on the different methods and
parts to be used based on the data collected.
A simple calculator will involve the following three hardware units
1. Input Device
2. FPGA Processing Unit
3. Output Device
2.3.1 Input device
As the project was to design a simple calculator, the user should be able to enter the
numbers and arithmetic operators easily. The best way to do this was to provide with a
keypad or a keyboard. Most of the keypads and keyboards available were using either an
USB interface or a PS-2 interface. This was also a criterion taken into account while
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choosing the FPGA Processing unit for this project. A PS-2 interface keypad or keyboard
proved to be the best option since most of the major FPGA boards were compatible with
it.
Figure 2.3.1: A PS2 keyboard and a PS2 Numeric Keypad
2.3.2 FPGA processing unit
Various FPGA boards and development kits were available in the market. Xilinx and
Altera were two of the major FPGA board vendors. There were various models in the
market ranging from those for high-end applications to those for normal low-end
applications. The simple calculator project does not require those expensive high-end
boards. Two development kits were short listed after a thorough research. They were,

Xilinx Spartan-3A Starter Kit

Altera Cyclone II FPGA Starter Development Kit
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Comparisons of the important features of these development kits are shown in Table 2.
Development
Xilinx Spartan-3A Starter Kit
Kit
Memory
Altera Cyclone II FPGA
Starter Development Kit
4 Mbit Platform Flash PROM,
8-MbyteSDRAM, 512-Kbit
32Mx16 DDR2 SDRAM, 32 Mbit
SRAM, 4-Mbyte flash
parallel Flash, 2-16 Mbit SPI Flash
Devices
Connectors
Ethernet 10/100 PHY, JTAG USB
VGA, RS-232, and PS/2 ports
download port, two 9- pin RS-232
Two 40-pin expansion ports
Serial Port, PS/2-style
SD/MMC socket
mouse/keyboard port, 15-pin VGA
connector capable of 4,096 colors,
one FX2 100-pin and two 6-pin
expansion connectors, 20 user I/O
available on standard header pins,
stereo mini-jack for PWM audio.
Rotary/push button function switch,
eight individual LED outputs, four
slider switches, four push- button
switches.
Cost (US $)
$189
$150
Clock Speed
50 Mhz
50 Mhz
Display
16 character, 2-Line LCD
Four 7-segment displays Ten
red and eight green LED’s
Table 2.3.2: Comparison of FPGA Processing Units.
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Figure 2.3.2: Spartan 3A and Cyclone 2 target boards.
The Xilinx board was selected based on the comparison and project requirements. Even
though the Xilinx board fares well in most aspects, the major aspect for its selection was
the inbuilt LCD. The Altera board does not have any inbuilt LCD display which is the
output device for the simple Calculator. The Spartan 3A starter kit includes the following
[15] :
▪
Development board
▪
Power supply 100-240V, 50/60 Hz with universal plug adaptors
▪
Xilinx ISE® WebPACK™ or ISE Foundation™ evaluation software
▪
Quick start guide, product collateral and programming cable
The key features of the development board are:
▪
Xilinx Devices
Spartan-3A (XC3S700A-FG484)
Platform Flash (XCF04S-VOG20C)
▪
Clocks
50 MHz crystal oscillator on-board
Open slot for optional user-installed clock
▪
Memory
4 Mbit Platform Flash PROM
32M x 16 DDR2 SDRAM
32 Mbit parallel Flash
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2-16 Mbit SPI Flash devices
▪
Analog Interface Devices
4-channel D/A converter
2-channel A/D converter
Signal amplifier
▪
Connectors and Interfaces
Ethernet 10/100 PHY
JTAG USB download port
Two 9-pin RS-232 serial port
PS/2-style mouse/keyboard port
15-pin VGA connector capable of 4,096 colors
One FX2 100-pin and two 6-pin expansion connectors
20 user I/O available on standard header pins
Stereo mini-jack for PWM audio
Rotary/push button function switch
Eight individual LED outputs
Four slider switches
Four push-button switches
▪
Display
16 character, 2-Line LCD
2.3.3 Output device
There was a great advantage in choosing the Xilinx Spartan-3A Starter Kit. It has an
inbuilt LCD display, which meant there was no need to interface any external output
device to the board. The inbuilt LCD would serve as the output device for this project.
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Figure 2.3.3: Spartan 3A inbuilt LCD
2.4
HDL overview and selection
Hardware description language (HDL) is a kind of language used for the conceptual
design of integrated circuits [3]. There are now two industry standard hardware
description languages, VHDL and Verilog. Either of them could be used to write the
coding for the calculator. A comparison and contrast of the major features of these
languages is shown in the Table 3.
Hardware
Description VHDL
Verilog
language
Data Types
A multitude of language or All data types used are
user defined data types can defined by the Verilog and
be used.
Design Reusability
not by the user.
Procedures and functions There is no concept of
may be placed in a package packages
in
Verilog.
so that they are available to Functions and procedures
any design-unit that wishes used within a model must
to use them.[2]
Managing Large designs
Configuration,
generic
and
be defined in the module.
generate, There are no statements in
package Verilog that help manage
statements all help manage large designs.
large design structures.
Libraries
A library is a store for There is no concept of a
compiled
entities, library in Verilog. This is
architectures, packages and due to it's origins as an
configurations. Useful for interpretive language.
managing multiple design
projects.
Procedures and Tasks
Allows
concurrent Does not allow concurrent
procedure calls.
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task calls.
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Table 2.4: Comparison of Hardware description Languages
VHDL has been more commonly used in this geographical area (Singapore). A lot of
resources and examples are available for VHDL in this area than Verilog. VHDL was
chosen as the development language for the Simple Calculator project.
2.5
Software Selection
The Xilinx Spartan 3A starter kit comes with the ISE design suite for simulating and
targeting HDL codes. Xilinx ISE (integrated software environment) controls all aspects of
the development flow [7]. Project Navigator is a graphical interface allowing users to
access software tools and relevant files associated with the project. The figure below
shows the Xilinx ISE project navigator interface.
Figure 2.5: Xilinx ISE project navigator.
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CHAPTER 3
PROJECT MANAGEMENT
3.1 Initial tasks and schedule
A list of tasks and their schedule were drawn up at the start of the project. the project was
divided into three phases and the different phases were divided into tasks. The figure
below shows the various phases and tasks and their estimated time of completion. This
chart was drawn up at the start of the project.
Figure 3.1: Initial tasks and schedule
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3.2 Proposed and actual schedule
The project schedule did not go all the way as planned. A lot of problems were
encountered on the way which extended the task schedule. The below Gantt chart shows
the planned schedule and the actual time taken to complete these tasks. Overall the
planning did not meet the complete requirements. But most of the major tasks were
accomplished without much delay.
Figure 3.2.1: Gantt chart – Introduction and research phase
Figure 3.2.2: Gantt chart – Design and development phase
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Figure 3.2.3: Gantt chart – Troubleshooting and finalization phase
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CHAPTER 4
DESIGN AND IMPLEMENTATION OF SYSTEM
4.1
Hardware and tools used in the design
The selection of hardware and tools used in the design of the Simple calculator has been
shown in the literature review section. This section describes the hardware and tools used
and their configurations in detail.
4.1.1 FPGA Development Kit – Xilinx Spartan 3A Starter Kit
Figure 4.1.1: Xilinx Spartan 3A starter kit peripherals [ ]
As seen in the earlier section in Table 2.4, the obvious selection for this project is the
Xilinx Spartan 3A Starter Kit. Applications can generally be classified in two categories:
low-cost applications, where the cost of the device is most important; and highperformance applications, where getting the highest bandwidth is paramount. The simple
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calculator project is a low cost application with low bandwidth requirements.
The figure above shows a Spartan 3A board with all its ports and peripherals. As seen
from the figure, the Spartan 3A board has an inbuilt LCD display, which can be used as
the output device and a PS2 port to which the input device can be connected. VHDL
coding was done to access these peripherals and provide the necessary input output
requirements for the project. To access these peripherals, the PS-2 port and the LCD were
studied in detail.
4.1.2 PS-2 port and numeric keypad
As an input to the simple calculator design, the input device should be able to allow the
user to enter numbers and basic arithmetic operators.
Figure 4.1.2.1: PS2 Connector Location and Signals on Spartan 3A board [15].
The keyboard uses open-collector drivers so that either the device or the host can drive the
two-wire bus [13]. If the host never sends data, then the host can use simple input pins. A
PS-2 style keyboard uses scan codes to communicate key-press data. Each key has a
single, unique scan code that is sent whenever the corresponding key is pressed. The scan
codes for most keys are shown in the figure below.
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Figure 4.1.2.2: PS2 Keyboard Scan Codes[15]
4.1.3 LCD display
As Discussed before, the inbuilt LCD on the board is used as the output device for the
calculator system. The Spartan-3A Starter Kit board prominently features a 2-line by 16character liquid crystal display (LCD). The FPGA controls the LCD via the eight-bit data
interface shown in Figure 7. The LCD is a practical way to display a variety of
information using standard ASCII and custom characters.[15] However, these displays are
not fast. Scrolling the display at half-second intervals tests the practical limit for clarity.
Compared with the 50 MHz clock available on the board, the display is slow [15].
Figure 4.1.3: Character LCD Interface
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The controller has three internal memory regions, each with a specific purpose: DD RAM,
CG ROM, and CG RAM. The display must be initialized before accessing any of these
memory regions.[15]

DD RAM: The Display Data RAM (DD RAM) stores the character code to be
displayed on the screen. Most applications interact primarily with DD RAM.

CG ROM: The Character Generator ROM (CG ROM) contains the font bitmap for
each of the predefined characters that the LCD screen can display

CG RAM: The Character Generator RAM (CG RAM) provides space to create
eight custom character bitmaps.
4.1.4 VHDL
Digital designs can be easily described using VHDL. The advantage of VHDL over
Verilog is its Modeling capability. The modeling constructs of VHDL and Verilog cover a
slightly different spectrum across the levels of behavioral abstraction [3].
Figure 4.1.4.1: HDL Modeling Capability [3]
VHDL programs describe the generation of events in digital systems. Firstly, it allows
description of the structure of a design, showing how it is decomposed into sub-designs,
and how those sub-designs are interconnected. Secondly, it allows the specification of the
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function of designs using familiar programming language forms. Thirdly, as a result, it
allows a design to be simulated before being manufactured, so that designers can quickly
compare alternatives and test for correctness without the delay and expense of hardware
prototyping.[1]
Figure 4.1.4.2: VHDL Simulation Modeling.
VHDL has the language constructs for key attributes [9]
 Propagation delays, events and concurrency
 Waveforms and timing
 Use of multiple drivers for a signal and Signal values.
The features of the VHDL simulation model include
 Good management of events and progression of time.
 Signals are used to model the generation of events.
 The designer just needs to provide accurate descriptions.
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Program Design overview
The design of the simple calculator started with the creation of a program flowchart. The
chart is shown in the figure below.
Figure 4.2.1: Program flow chart
The flow of the program is as follows:

The program starts and waits for the user input

The user entry is checked whether it is an operand or an operator.

When the first operand is entered, it is displayed on the LCD in real time, the first
operand is saved and the system waits for the operator.

When the operator is pressed, the LCD is cleared and the system waits for the
second operand.

When the second operand is entered, it is displayed on the LCD in real time, the
second operator is saved and the system waits to perform the calculation.
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When the enter button is pressed, the calculation is performed, and the result is
displayed on the LCD.

When enter button is pressed, the LCD is cleared and the system goes back to its
initial state.
Figure 4.2.2: Block Diagram of the simple calculator
The figure above shows a block diagram of the simple calculator design. The system
would be able to handle up to 4 digit operands. Floating point would not be supported.
Without the implementation of floating points, the division operation would turn out to be
problematic. A Xilinx IP core was used for the division process. The different modules
used in the system are discussed in the program modules section of the report. As the scan
codes of a commercially available PS-2 numeric keypad are the same as that of a
keyboard, the keypad was used as the input device for the system. This eliminated the
unused keys and makes the design more compact.
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Program Modules
The realization of the program design flow chart was done using VHDL codes. The
design must be able to capture the user input, perform the necessary calculations and
display the result with minimum delay. The VHDL coding for the simple calculator
system was divided into 6 main modules namely:

Top level

PS-2 controller

Operator/operand selector

Calculator unit

LCD controller
 Ce generator
Figure 4.3: Program modules
4.3.1 Top level behavioral
The function of the top-level module is to initialize and combine all the modules of the
design. The figure below shows the top-level design of the system.
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Figure 4.3.1: Program modules top-level design
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As seen from the figure above, a common clock signal (clk) and reset signal (reset) are
supplied to all the individual modules. Detailed descriptions of the other signals supplied
to or generated by the individual modules are shown in the following sections of this
report. The port mapping of the various signals used in the individual modules are shown
in the top-level behavioral.
4.3.2 PS-2 Controller – PS2_ctrl
The VHDL module used for controlling the PS-2 keypad/keyboard is named ‘PS2_Ctrl’.
This module initializes and receives data from the input device of the simple calculator
system, the PS-2 numeric keypad. The keyboard uses scan codes to send data to other
devices. The module identifies the scan codes and sends the data to the ‘operator/operand
selector’ module. The simple calculator only uses numbers, the four operators and the
enter key for its operation. As such the scan codes for all the other keys were ignored. The
figure below shows the graphic symbol of a PS-2 controller with the inputs on the left and
the outputs on the right.
Figure 4.3.2.1: Graphic symbol of PS-2 controller
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As seen from the above figure, the inputs to the PS-2 controller are

Clk:
It is the sole clocking source for all the Flip-Flops (fully synchronous
design).

Reset:

PS2_Clk & PS2_Data: They are the two signal lines of the PS-2 interface. They
It is used inside the module as an asynchronous global reset.
act as the inputs to the module. The keyboard sends commands or data to the host
only when both the data and clock lines are high. This is the idle state. The clock
and data signals are driven only when data transfer occurs. The timing diagram
below shows the signal requirements for keyboard communications. The keyboard
sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight
bits of scan code (LSB first), followed by an odd parity bit and terminated with a
‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions and
data is valid on the falling edge of the clock as shown in the figure below. [ ]
Figure 4.3.2.2: PS-2 bus timing waveforms [15 ]
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DoRead:
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The signal arrives from the output ‘ReadDone’ of the Op_sel module.
It is an input pulsed by the user when a data out code is read. This clears the
‘Scan_DAV’ bit.
The outputs are:

Scan_DAV:
When a word has been received, this signal goes to 1. It remains at
that state until the ‘DoRead’ signal from the Op_sel is asserted and then goes low
at the next clock cycle.

Scan_Err:
This is set when the data received is incorrect due to parity or stop
error. It is also set when there is an overflow due to the previous code not read in
time. When the reception of a new character begins, this flag is automatically
cleared.

Scan_Code:
It is the 8-bit data word that is received. Every character on the
keypad/keyboard has different scan codes. Its value remains same until the next
word is received
The UCF location constraints for the PS-2 port connecting, including the input/output pin
assignment and standard used are shown in the diagram below. In the design of the simple
calculator project only the primary connection is used.
Figure 4.3.2.3: PS-2 UCF location constraints for Spartan 3A [15]
The basic program flow of the PS2_ctrl module is shown in the figure below. The various
input and output signals used in the module are shown in the module flow chart.
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Figure 4.3.2.4: PS2_ctrl module program flow.

The cycle starts with the system in idle state where the ‘PS2_Clk’ and ‘PS2_Data’
signals are high. When the data transfer starts these signals are driven.

The data transfer starts. If there is a parity or stop error, the ‘Scan_Err’ signal is
driven and is cleared when the when the new character is received.

When the ‘Scan_Code’ is received, the ‘Scan_DAV’ signal is driven to high and
the scan code is send to the ‘OP_sel’ module.

When the ‘Op_sel’ module receives the scan code, the ‘Read_Done’ signal from
the ‘Op_sel’ module drives the ‘Do_Read’ signal.

The ‘Do_Read’ signal resets the ‘Scan_DAV’ and the module waits for the next
data.
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4.3.3 Operator/Operand selection module – Op_sel
Figure 4.3.3: Operand/Operator Selection module
The main function of this module is to differentiate between the numeric values and the
operators. A secondary task of this module is to decode the keypad make, break and scan
codes. The various input and output signals of the module are shown in the figure above.
The input signals to the Op_sel module are:

Clk:
It is the sole clocking source for all the Flip-Flops (fully synchronous
design).

Reset:

Scan_DAV: This signal comes from the PS2_ctrl module. This signal determines
It is used inside the module as an asynchronous global reset.
the word has been received by the PS2_ctrl module and the scan code is valid.

Scan_Code: This signal comes from the PS2_ctrl module. It is the 8-bit data word
that is received. Every character on the keypad/keyboard has different scan codes.
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Its value remains same until the next word is received. The scan code is send by
the PS2_ctrl module only if it is valid.
The output signals from the Op_sel module are:

Num(3:0): If the scan code received is a number, it is saved to ‘Num’ and
transmitted to the ‘Calc_unit’ module. Each number entered is identified as a 4 bit
number and the operand is derived by combining the 4 bit numbers. As discussed
above, the simple calculator design would be able to handle a maximum of four
digits per operand.

Op(1:0): As there are four possible operators to be used in the simple calculator
design, the module needs to differentiate between them and send the right signal to
the ‘Calc_unit’ module. This two bit variable is used to send the operator signal to
the ‘Calc_unit’ module. The table below shows how it differentiates between the
different operators.
Op(1:0)
Operator
00
+
01
-
10
*
11
/
Table 4.3.3.1: Operator selection

calc_flag: When the scan code received is that of the ‘ENTER’ button, the
‘calc_flag’ becomes valid and is sent to the ‘calc_unit’ module.

num_flag: When the scan code received is that of a numeric value, the ‘num_flag’
becomes valid and is sent to the ‘calc_unit’ module.

op_flag: When the scan code received is that of an operator, the ‘op_flag’ becomes
valid and is sent to the ‘calc_unit’ module.

ReadDone:
When the scan code has been successfully read. This clears the
‘Scan_DAV’ bit and the ‘PS2_ctrl’ module waits for the next user input.
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The scan code data used in this module are the numeric values, the operators and the
‘ENTER’ button. A case structure is used to compare the scan codes arriving to the
‘Op_sel’ module. The table below shows the different scan codes used in the module.
These scan codes correspond to those of the numeric keypad used.
Scan code arrived
Corresponding value
F0
Break Code
5A
Enter Button
79
Addition
7B
Subtraction
7C
Multiplication
4A
Division
70
0
69
1
72
2
7A
3
6B
4
73
5
74
6
6C
7
75
8
7D
9
Table 4.3.3.2: Scan codes used in the ‘Op_sel’ module.
A process in the module selects the arrived scan code. If the scan code that arrives is a
numeric value, then the ‘num_flag’ is activated. If the scan code that arrives is that of an
operator, then the op_flag is activated. If the scan code that arrives is that of the ‘ENTER’
button, then the calc_flag is activated. This data is then send to the ‘calc_unit’ to perform
the arithmetic operations.
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4.3.4 Calculator module – Calc_unit
Figure 4.3.4.1: Calculator module
This module receives the numeric values and the operators from the ‘Op_sel’ module. It
performs the desired arithmetic operation on the values received. The numeric values and
the results are send to the ‘LCD_control’ module to be displayed.
The input signals to the ‘Calc_unit’ module are:

Clk: It is the sole clocking source for all the Flip-Flops (fully synchronous design).

Reset: It is used inside the module as an asynchronous global reset.

Num(3:0): This input signal comes from the ‘Op_sel’ module. It contains the
numeric value entered by the user. The module determines whether it is the first or
the second operand and performs the necessary calculations.

Op(1:0): This input signal comes from the ‘Op_sel’ module. It contains the
operator entered by the user. The operator is then used by the calculator module
and the requested arithmetic operation is performed.
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calc_flag: This signal coming from the ‘Op_sel’ module tells the calculator
module that the user has pressed the ‘ENTER’ button. The calculator module then
performs the requested operations and the result is send to the LCD module.

num_flag: This signal coming from the ‘Op_sel’ module tells the calculator
module that the user has entered an operand. The calculator module then receives
the operand and determines whether it is the first or the second operand.

op_flag: This signal coming from the ‘Op_sel’ module tells the calculator module
that the user has entered an operator. The calculator module then takes the
operator from the ‘Op (1:0)’ signal and waits for the next operand to perform the
requested operation.
The output signals to the ‘Calc_unit’ module are:

dig1 (3:0): This output signal from the calculator unit carries the first digit of the
operand or the result. The signal is in Binary-coded decimal (BCD) format so that
the LCD would be able to display the number. It contains the information of how
many thousands are in the number.

dig2 (3:0): This output signal from the calculator unit carries the second digit of
the operand or the result. The signal is in Binary-coded decimal (BCD) format so
that the LCD would be able to display the number. It contains the information of
how many hundreds are in the number.

dig3 (3:0): This output signal from the calculator unit carries the third digit of the
operand or the result. The signal is in Binary-coded decimal (BCD) format so that
the LCD would be able to display the number. It contains the information of how
many tens are in the number.

dig4 (3:0): This output signal from the calculator unit carries the fourth digit of the
operand or the result. The signal is in Binary-coded decimal (BCD) format so that
the LCD would be able to display the number. It contains the information of how
many ones are in the number.
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Figure 4.3.4.2: Calculator module program flow chart
The figure above shows the basic program flow of the calculator module.

The module checks for the status of the three flags (num_flag, op_flag and
calc_flag) to determine whether the ‘Op_sel’ module is sending the operands,
operators or the ‘ENTER’ signal.

When the num_flag is activated, the module checks whether the number received
from ‘Num(3:0)’ is the first operand or the second.

When the first operand is received, the number is converted to BCD format and
send to the LCD in real time. The module then waits for the operator.

When the second operand is received, the number is converted to BCD format and
send to the LCD in real time. The module then waits for the ‘calc_flag’ to perform
the requested operation.
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When the ‘op_flag’ is activated, the module checks the ‘Op(1:0)’ to determine the
operator requested by the user. The module then waits for the second operand and
the ‘calc_flag’ to perform the requested operation.

When the ‘calc_flag’ is activated, the module performs the requested operation.
The result is then converted to BCD and send to the LCD for display.
As the design only caters for integers, the division part becomes a problem. This problem
is solved by using the divider core generator IP from Xilinx. The figure below shows the
divider core generator used in the design. The core generator enables the division while
using the integer values.
Figure 4.3.4.3: Divider core generator IP
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4.3.5 LCD Controller – LCD_control
Figure 4.3.5.1: LCD controller module
The function of this module is to initialize the LCD and display the operands and the
calculated results. The module allows the design to display the 4 digit operands or results.
The above figure shows the various inputs and outputs of the LCD controller module.
The input signals to the ‘LCD_control’ module are:

Clk: It is the sole clocking source for all the Flip-Flops (fully synchronous design).

Reset: It is used inside the module as an asynchronous global reset.

Ce: The LCD controller module contains a shadow memory that copies data into
the LCD memory every 0.1 seconds. The ‘ce_generator’ module generates the ‘ce’
signal every 0.1 seconds and sends it to the LCD controller module.

dig1 (3:0): This Binary-coded decimal (BCD) input signal comes from the
calculator unit and carries the first digit of the operand or the result. It contains the
information of how many thousands are in the number.

dig2 (3:0): This Binary-coded decimal (BCD) input signal comes from the
calculator unit and carries the second digit of the operand or the result. It contains
the information of how many hundreds are in the number.
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dig3 (3:0): This Binary-coded decimal (BCD) input signal comes from the
calculator unit and carries the third digit of the operand or the result. It contains
the information of how many tens are in the number.

dig4 (3:0): This Binary-coded decimal (BCD) input signal comes from the
calculator unit and carries the last digit of the operand or the result. It contains the
information of how many ones are in the number.
The output signals from the ‘LCD_control’ module are:

db(3:0): It is the four-bit data interface used that is connected to the LCD. It allows
writing the data to the LCD.

e: This signal sends the read/write enable pulse to the LCD. When the signal is
driven high, the read/write operation of the LCD is enabled. Driving the signal low
would disable the character LCD.

rs: the function of this signal is to select the required register in the LCD. When
driven high, the data register is selected for read/write operations. When driven
low, instruction register is selected during write operations.

rw : This signal controls the read/write operations of the LCD. When driven to
high, the LCD presents its data and when driven to low, the LCD accepts data. The
signal is driven to low as the data is only to be written to the LCD.
After the system is powered on the LCD display must be initialized to establish the
required communication protocol. The calculator project uses the four-bit data interface to
the LCD display. The LCD controller module contains a shadow memory that copies data
into the LCD memory every 0.1 seconds. The UCF location constraints for the character
LCD in the Spartan 3A board is shown in the figure below.
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Figure 4.3.5.2: UCF location constraints for the character LCD [15 ]
Several counters are used in the module to achieve the delay implementation. The poweron initialization sequence for the four-bit data interface to the LCD is as follows:[ ]
1. Wait 50ms or longer, although the display is generally ready when the FPGA
finishes configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
2. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
3. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
4. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
5. Wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
6. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
7. Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
8. Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles.
9. Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
The four bit interface is established after the power-on initialization is complete. The next
step is to configure the display for operation. The configuration is done as follows:[ ]
1. Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3A/3AN Starter Kit board.
2. Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
3. Issue a Display On/Off command, 0x0C to turn the display on and disable the
cursor and blinking.
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4. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock
cycles) after issuing this command.
The figure below shows the LCD character display command set for four-bit mode used
for the Spartan 3A board.
Figure 4.3.5.3: LCD character display command set for four-bit mode. [15 ]
The process of writing data to the display includes specifying the start address first,
followed by one or more of the data values. Before any data is written to the LCD, a Set
DD RAM Address command is issued to specify the initial seven-bit address in the DD
RAM. The figure below shows the various DD RAM hexadecimal addresses.
Figure 4.3.5.4: DD RAM Hexadecimal Addresses. [15 ]
The data is written to the display using a Write Data to CG RAM or DD RAM command.
The eight-bit data value represents the look-up address into the CG RAM or CG ROM.
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The look-up addresses for the CG RAM and CG ROM are shown in the figure below. The
stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to represent the
associated character.
Figure 4.3.5.5: LCD Character set. [ 15]
Figure 4.3.5.5: Character LCD interface timing [15]
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The module is able to sequentially write up to four digits to the LCD. The above figure
shows a typical write operation to the LCD for the Spartan 3A board, showing the
minimum times allowed for setup, hold, and enables pulse length relative to the 50 MHz
clock (20 ns period) provided on the board.
4.3.6 Signal generator - Ce_Generator
Figure 4.3.6: ce_generator
The LCD controller module contains a shadow memory that copies data into the LCD
memory every 0.1 seconds. The function of the ‘ce_generator’ module is to generate the
‘ce’ signal every 0.1 seconds and send it to the LCD controller module.
The input signals to the ‘ce_generator’ module are:

Clk: It is the sole clocking source for all the Flip-Flops (fully synchronous design).

Reset: It is used inside the module as an asynchronous global reset.
The output signal from the ‘ce_generator’ module is

ce: this signal is generated every 0.1 seconds and send to the ‘LCD_control’
module.
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CHAPTER 5
TESTING AND FINALISATION
5.1 LCD Controller
A testbench was created to test the LCD controller. Though the LCD display part of the
project was not working correctly, testing was done to test the basic structure. The figure
below shows the simulation results of the LCD testbench.
Figure 5.1: LCD simulation testbench
5.2 Keyboard testbench
A testbench was created to test the PS-2 controller. The figure below shows the
simulation results of the PS-2 controller testbench.
Figure 5.2: PS-2 controller testbench
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5.3 Compiling and targeting of VHDL code
The VHDL codes written for the various modules needed to be compiled and targeted to
the Spartan 3A target board. The Xilinx ISE design suite was used to compile and target
the codes to the target board. First of all, the design properties of the project were set
according to the target board used. The figure below shows how the design properties
were set for the project.
Figure 5.3.1: ISE design properties
The next step is to add the various modules to the project based on their hierarchy. The
figure below shows how the various modules were added to the project navigator based
on the hierarchy. The figure also shows how to implement the design on to the board or
simulate by choosing the required option from the drop down menu.
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Figure 5.3.2: Hierarchy of sources
After the implementation option was selected, the target board was connected to the PC
via the USB Type A/Type B cable. The target board also had the PS-2 keypad connected
before being power on. The figure below shows the hardware setup.
Figure 5.3.3: Hardware setup
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Once connected the process of generating the programming file can begin. The top level
module of the hierarchy is selected and command to generate the programming file is
given. The Project navigator then synthesizes, translates, maps, places and routes the
design. The programming file is then generated after all the processes are finished. The
figure below shows the processes involved in the generation of the programming file.
Figure 5.3.4: Generation of programming file
After the successful generation of the programming file based on the design properties, an
ISE iMPACT window is opened which allows the user to target the generated
programming file on to the target board. The launch wizard in the software performs a
boundary scan and automatically detects the attached board and shows the various
programmable sources on the board. In this project the program is directly targeted to the
Xilinx FPGA, xc3s700a. The rest of the devices are bypassed.
The xc3s700a is set and the target device and programmed. Successful programming will
show a ‘program succeeded’ prompt and the board will be ready to use with the codes
loaded. The figure below shows the successful programming of the target board.
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Figure 5.3.5: iMPACT program succeeded.
5.4
Testing the Program on the target board
The program was targeted on to the board for testing during various phases of the project.
The final program including all the modules was successfully targeted on to the target
board. But the LCD remained unresponsive after repeated attempts. Troubleshooting was
still on progress during the completion of this report.
Testing was also done during an earlier part of the development phase where the division
process was not included. The LCD was displaying the numbers and the results but was
behaving strangely. There was some king of glitch in the LCD module. The code for the
LCD module was reconsidered and some changes were made. Once the division process
was implemented using the divider core generator, the LCD has become completely
unresponsive. The figure below shows the LCD glitch during the earlier phase of the
project.
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Figure 5.4: LCD glitch encountered.
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CHAPTER 6
CONCLUSIONS AND RECOMMENDATIONS
6.1 Conclusions
The objectives for the project were not completely met. The initial objective of the project
was to design a simple calculator able to perform the four basic arithmetic operations
namely addition, subtraction, division and multiplication. The final product had all the
four modules for performing these four operations. But the LCD driver design had some
problems and the display was not shown correctly. After the first three arithmetic
operations excluding division were integrated and tested there was an LCD glitch showing
unintended characters along with the number. After the division process was
implemented, the LCD was unresponsive. Even though the project was not a complete
success, a lot of knowledge about FPGA and VHDL systems were acquired during the
course of the project. Good project management and report writing skils were acquired
during the course of the project.
6.2 Recommendations
There is still room for a lot of improvement for the simple calculator project. As the
project is not a fully working prototype, troubleshooting could be done to find the root
cause of the problems and make the project working. The calculator could include other
functions like calculating percentage, trigonometric values, squares or roots. It would also
be advantageous if the programming data could be stored on to the FLASH memory
available in the Spartan 3A board. The simple calculator design also does not support
floating point operands. It would be an added advantage to include floating point support
for the simple calculator system.
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CHAPTER 7
REFLECTION
Many problems were encountered during the course of this project. The biggest one was
during the start of the project. I realized I had a few weaknesses which needed to be
immediately improved upon if the project needed to be completed. The weaknesses
included.

No previous experience in using any hardware description language.

No Previous experience in developing FPGA based systems.

Slow learner of software skills.
As such a lot of time was spend in researching about the FPGA and VHDL. The lack of
experience made it very difficult to understand the concepts and basics of VHDL and
FPGA. The acquiring of the target board also took a lot of time from the project. The
board was not locally available and had to be ordered from abroad. The total process of
acquiring the board took about 2 months. This took a lot of time away from the initial
planning of the project schedule. In the mean time i had an opportunity to learn more
about VHDL and Xilinx ISE design suite which were to be used for the project. Literature
review and researching skills were improved during the course of this phase.
I also managed to improve my project and time management skills throughout the course
of this project. As I was also working and had other modules to take at college, the time
management skills proved to be very difficult. The heavy workload had taken a toll on
me. The project gave me an experience in time management which has helped me a lot in
improving my management skills.
The project also encountered many technical problems and this helped me improve my
troubleshooting skills. The technical problem included understanding the target board
fundamentals and programming the target boards LCD and PS-2 interfaces. Programming
the LCD and PS-2 interfaces consumed a fair amount of time allotted for the project.
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The LCD part of the project was the toughest. A lot of time was spend on solving the
problems caused due to this. It gave me a good understanding of the various peripherals in
the Spartan 3A board and how to utilise them. At this stage the project, the LCD still has
some glitches and troubleshooting is still going on. Starting with zero knowledge on
FPGA and VHDL, it was a difficult time for me during the initial phases of the project.
My supervisor and friends helped me a lot during this time of the project. Even though i
had some draw backs, there were some skills i could put to use in the development of this
project. They included:

Previous experience in Programming of PIC microcontrollers.

Good project and time management skills.

Good documentation and report writing skills.
These skills helped me a lot during the course of the project. Overall the project greatly
improved my troubleshooting, technical, research, project and time management skills.
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REFERENCES
[1] REAL TIME IMPLEMENTATION OF A FUZZY LOGIC CONTROLLER ON
FPGA USING VHDL FOR DC MOTOR SPEED CONTROL, G.Sakthivel et. al. /
International journal of Engineering Science and Technology Vol. 2(9), 2010, 4511-4519
[2] Dr. Subbarao Wunnava and Jaime Marcelo Montenegro, 2004. “Tutorial on VHDL
and Verilog Applications", Second LACCEI International Latin American and Caribbean
Conference for Engineering and Technology (LACCEI’2004).
[3] Sudhakar Yalamanchili, “VHDL – A Starters Guide, Second Edition, 2005”
[4] Dorf, R.C., 2000. "The Electrical Engineering Handbook", CRC Press LLC.
[5] Olaf O. Storaasli, 2007. “Exploring Accelerating Science Applications with FPGAs”
Oak Ridge National Laboratory, Cray Inc.
[6] Tom Van Court and Martin C. Herbordt “Requirements for any HPC/FPGA
Application Development Tool Flow”
[7] Xilinx, ISE In-Depth Tutorial, Xilinx, Inc.
[8] C. M. Maxfield, The Design Warrior’s Guide to FPGAs, Newnes, 2004.
[9] P. J. Ashenden, The Designer’s Guide to VHDL, 2nd ed., Morgan Kaufmann, 2001.
[10]
A.
Chapweske,
“PSI2
MouseIKeyboard
Protocol,”
http://www.computer-
engineering.org.
[11] IEEE, IEEE Standard VHDL Language Reference Manual (IEEE Srd 1076-2001),
Institute of Electrical and Electronics Engineers, 2001.
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[12] W. Wolf, FPGA-Based System Design, Prentice Hall, 2004.
[13] FPGA Prototyping by VHDl Examples, Xilinx Spartan-3 Version, Pong P.Chu,
Cleveland State University.
[14] Stephan Brown and Jonathan Rose, Architecture of FPGAs and CPLDs : A Tutorial,
University of Toronto, P7.
[15] Spartan-3A/3AN FPGA Starter Kit Board User Guide, UG334 (v1.1) June 19, 2008
www.xilinx.com/support/documentation/user_guides/ug332.pdf
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GLOSSARY
Altera Cyclone – Highly successful series of FPGA boards Altera and devices developed
for low cost applications
ASCII - The American Standard Code for Information Interchange. These odes represent
text in computers, communication equipment and other devices that uses text.
ASIC - An application-specific integrated circuit is an integrated circuit (IC) customized
for a particular use, rather than intended for general-purpose use.
BCD - binary-coded decimal is an encoding for decimal numbers in which each digit is
represented by its own binary sequence.
FPGA - A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by the customer or designer after manufacturing.
HDL - In electronics, a hardware description language or HDL is any language from a
class of computer languages or programming languages for formal description of
electronic circuits, and more specifically, digital logic. It can describe the circuit's
operation, its design and organization, and tests to verify its operation by means of
simulation.
LCD - A liquid crystal display (LCD) is a thin, flat electronic visual display that uses the
light modulating properties of liquid crystals (LCs). LCs do not emit light directly.
LSB - In computing, the least significant bit (LSB) is the bit position in a binary integer
giving the units value, that is, determining whether the number is even or odd.
RAM - Random-access memory (RAM) is a form of computer data storage. Today, it
takes the form of integrated circuits that allow stored data to be accessed in any order (i.e.,
at random). "Random" refers to the idea that any piece of data can be returned in a
constant time, regardless of its physical location and whether it is related to the previous
piece of data.
ROM - Read-only memory (ROM) is a class of storage media used in computers and
other electronic devices. Data stored in ROM cannot be modified, or can be modified only
slowly or with difficulty, so it is mainly used to distribute firmware.
SPARTAN 3A - Highly successful series of FPGA boards and devices from Xilinx
developed for low cost applications
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UCF - The user constraints file (.ucf) is an ASCII file that holds timing and location
constraints.
VERILOG - In the semiconductor and electronic design industry, Verilog is a hardware
description language (HDL) used to model electronic systems.
VHDL - VHDL (VHSIC hardware description language; VHSIC: very-high-speed
integrated circuit) is a hardware description language used in electronic design
automation to describe digital and mixed-signal systems such as field-programmable gate
arrays and integrated circuits.
XILINX ISE - Design software with fully featured front-to-back FPGA design solution
for Linux, Windows XP, and Windows Vista. ISE WebPACK is the ideal downloadable
solution for FPGA and CPLD design offering HDL synthesis and simulation,
implementation, device fitting, and JTAG programming.
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APPENDICES
APPENDIX 1 – top_level.vhd
-----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top_level is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
PS2_Clk : in STD_LOGIC;
PS2_Data : in STD_LOGIC;
SF_CE : out STD_LOGIC;
db : out STD_LOGIC_VECTOR (3 downto 0);
e : out STD_LOGIC;
rs : out STD_LOGIC;
rw : out STD_LOGIC );
end top_level;
architecture Behavioral of top_level is
component LCD_control
port ( clk : in STD_LOGIC;
reset :in std_logic;
ce : in std_logic; -- signal 10Hz 0.1s
dig1 : in STD_LOGIC_VECTOR (3 downto 0);
dig2 : in STD_LOGIC_VECTOR (3 downto 0);
dig3 : in STD_LOGIC_VECTOR (3 downto 0);
dig4 : in STD_LOGIC_VECTOR (3 downto 0);
db : out STD_LOGIC_VECTOR (3 downto 0);
e : out STD_LOGIC;
rs : out STD_LOGIC;
rw : out STD_LOGIC ) ;
end component ;
component PS2_ctrl
port (
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Clk : in std_logic; -- System Clock
Reset : in std_logic; -- System Reset
PS2_Clk : in std_logic; -- Keyboard Clock Line
PS2_Data : in std_logic; -- Keyboard Data Line
DoRead : in std_logic; -- From outside when reading the scan code
Scan_Err : out std_logic; -- To outside : Parity or Overflow error
Scan_DAV : out std_logic; -- To outside when a scan code has arrived
Scan_Code : out std_logic_vector(7 downto 0) -- Eight bits Data Out
);
end component ;
component Op_sel
port (
clk : in std_logic;
reset : in std_logic;
Scan_DAV : in STD_LOGIC;-- scan code valid
Scan_Code : in STD_LOGIC_VECTOR (7 downto 0);
op_flag : out STD_LOGIC;-- if the scan code is an operation then it's valid
num_flag : out STD_LOGIC;--when scan code is a number then valid
calc_flag : out STD_LOGIC;-- when scan code is Enter it is valid
Op : out STD_LOGIC_VECTOR (1 downto 0);--operator 0 = +; 1 = -; 2 = *; 3 =
/;
Num : out STD_LOGIC_VECTOR (3 downto 0);--numric value
ReadDone : out std_logic -- response signal for the Scan_DAV signal
);
end component ;
component Calc_unit
port (
clk : in std_logic;
reset : in std_logic;
op_flag : in std_logic;
num_flag : in std_logic;
calc_flag : in std_logic;
Op: in std_logic_vector (1 downto 0);
Num : in std_logic_vector (3 downto 0);
dig1 : inout std_logic_vector (3 downto 0);
dig2 : inout std_logic_vector (3 downto 0);
dig3 : inout std_logic_vector (3 downto 0);
dig4 : inout std_logic_vector (3 downto 0)
);
end component ;
component ce_generator
port (
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clk : in std_logic;
reset : in std_logic;
ce : out std_logic
);
end component ;
signal dig1s: std_logic_vector (3 downto 0);
signal dig2s: std_logic_vector (3 downto 0);
signal dig3s: std_logic_vector (3 downto 0);
signal dig4s: std_logic_vector (3 downto 0);
signal Scan_DAVs : STD_LOGIC;-- scan code valid
signal Scan_Codes : STD_LOGIC_VECTOR (7 downto 0);
signal ReadDones: std_logic;
signal op_flags : std_logic;
signal num_flags : std_logic;
signal calc_flags : std_logic;
signal Ops: std_logic_vector (1 downto 0);
signal Nums : std_logic_vector (3 downto 0);
signal ces: std_logic;
begin
PS2_ctrli : PS2_ctrl
port map (
Clk => clk,
Reset => reset,
PS2_Clk => PS2_Clk,
PS2_Data => PS2_Data,
Scan_DAV => Scan_DAVs,
Scan_Code => Scan_Codes,
DoRead => ReadDones
);
Op_seli : Op_sel
port map (
clk => clk,
reset => reset,
Scan_DAV => Scan_DAVs,
Scan_Code => Scan_Codes,
ReadDone => ReadDones,
op_flag => op_flags,
num_flag => num_flags,
calc_flag => calc_flags,
Op => Ops,
Num => Nums
);
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Calc_uniti : Calc_unit
port map (
clk => clk,
reset => reset,
op_flag => op_flags,
num_flag => num_flags,
calc_flag => calc_flags,
Op => Ops,
Num => Nums,
dig1 => dig1s,
dig2 => dig2s,
dig3 => dig3s,
dig4 => dig4s
);
ce_generatori : ce_generator
port map (
clk => clk,
reset => reset,
ce => ces
);
LCD_controli : LCD_control
port map (
clk => clk,
reset => reset,
ce => ces,
dig1 => dig1s,
dig2 => dig2s,
dig3 => dig3s,
dig4 => dig4s,
db => db,
e => e,
rs => rs,
rw => rw
);
SF_CE <= '1';
end Behavioral;
------------------------------------------------------------------------------------------------------------
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Appendix 2 – calc_unit.vhd
------------------------------------------------------------------------------------------------------------- this module recives the numreic values and the operator; computes the result; the output
is dig1 to dig4 will be displayed by the lcd controller
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity calc_unit is
port (
clk : in std_logic;
reset : in std_logic;
op_flag : in std_logic;
num_flag : in std_logic;
calc_flag : in std_logic;
Op: in std_logic_vector (1 downto 0);
Num : in std_logic_vector (3 downto 0);
dig1 : inout std_logic_vector (3 downto 0);
dig2 : inout std_logic_vector (3 downto 0);
dig3 : inout std_logic_vector (3 downto 0);
dig4 : inout std_logic_vector (3 downto 0)
);
end entity;
architecture Behavioral of calc_unit is
component div
port (
clk: IN std_logic;
rfd: OUT std_logic;
dividend: IN std_logic_VECTOR(31 downto 0);
divisor: IN std_logic_VECTOR(31 downto 0);
quotient: OUT std_logic_VECTOR(31 downto 0);
fractional: OUT std_logic_VECTOR(31 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
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attribute syn_black_box of div: component is true;
signal operand1: integer;
signal operand2: integer;
signal displayed: integer;
signal dividend: std_logic_vector(31 downto 0);
signal divisor: std_logic_vector(31 downto 0);
signal quotient: std_logic_vector(31 downto 0);
signal res_reg: integer;
signal op1: boolean;
signal op_reg: std_logic_vector (1 downto 0);
begin
divi : div
port map (
clk => clk,
--rfd => rfd,
dividend => dividend,
divisor => divisor,
quotient => quotient);
dividend <=
divisor <=
conv_std_logic_vector(operand1,32);
conv_std_logic_vector(operand2,32);
-- variable op1 is a flag to select if the first operand or the second operand is introduced
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
-- Asynchronous reset code
op1 <= true;
elsif CLK='1' and CLK'event then
-- synchronous code
if op_flag = '1' then
op1 <= false;
elsif calc_flag = '1' then
op1 <= true;
end if;
end if;
end process;
-- as the numeric values are received from the keypad the value of the operand is
computed
process (CLK, RESET)
-- declarations
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begin
if RESET = '1' then
-- Asynchronous reset code
operand1<=0;
operand2<=0;
elsif CLK='1' and CLK'event then
-- synchronous code
if num_flag = '1' then
if op1 then
operand1 <= operand1*10 + conv_integer(Num);
else
operand2 <= operand2*10 + conv_integer(Num);
end if;
elsif calc_flag = '1' then
operand1<=0;
operand2<=0;
end if;
end if;
end process;
-- register the requested operation
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
-- Asynchronous reset code
op_reg <= "00";
elsif CLK='1' and CLK'event then
-- synchronous code
if op_flag = '1' then
op_reg<=op;
end if;
end if;
end process;
-- when calc flag is active the operation is executed; the result in saved into signal
"displayed"
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
-- Asynchronous reset code
displayed<=0;
elsif CLK='1' and CLK'event then
-- synchronous code
if num_flag = '1' then
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if op1 then
displayed <= operand1*10+conv_integer(Num)+1;
else
displayed <= operand2*10+conv_integer(Num)+1;
end if;
elsif calc_flag = '1' then
case op_reg is
when "00" => -- addition
displayed <= operand1 + operand2 + 1;
when "01" => -- substraction
displayed <= operand1 - operand2 + 1;
when "10" => -- multiplication
displayed <= operand1 * operand2 + 1;
when "11" => -- division
displayed <= conv_integer(quotient);
when others =>
-- the "/" operator is not synthesized
end case;
end if;
end if;
end process;
-- the signal "displayed" should be converted into to binary coded decimal
-- four digits can be displayed by the LCD controller
-- these for digits are dig1, .. dig4;
-- dig1 - thousands
-- dig2 - hundreds
-- dig3 - tens
-- dig4 - ones
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
-- Asynchronous reset code
dig1<="0000";
dig2<="0000";
dig3<="0000";
dig4<="0000";
res_reg<=0;
elsif CLK='1' and CLK'event then
-- set all values to 0 when a new conversion is desired to be made
if calc_flag = '1' or num_flag = '1' then
dig1<="0000";
dig2<="0000";
dig3<="0000";
dig4<="0000";
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res_reg<=0;
else
-- conversion
-- the idea is to count how many thousands, hundreds, tens and ones
are in the "displayed"
if displayed > (res_reg + 1000) then
dig1 <= dig1+"0001";
res_reg <= res_reg + 1000;
elsif displayed > (res_reg + 100) then
dig2 <= dig2+"0001";
res_reg <= res_reg + 100;
elsif displayed > (res_reg + 10) then
dig3 <= dig3+"1";
res_reg <= res_reg + 10;
elsif displayed > (res_reg + 1) then
dig4 <= dig4+"1";
res_reg <= res_reg + 1;
end if;
end if;
end if;
end process;
end Behavioral;
------------------------------------------------------------------------------------------------------------
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Appendix 3 – ce_generator.vhd
-----------------------------------------------------------------------------------------------------------library IEEE;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ce_generator is
port (
clk : in std_logic;
reset : in std_logic;
ce : out std_logic
);
end ce_generator;
architecture Behavioral of ce_generator is
signal count: integer;
begin
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
-- Asynchronous reset code
count <= 0;
ce <= '0';
elsif CLK='1' and CLK'event then
-- synchronous code
if count = 5000000 then
count <= 0;
ce <= '1';
else
count <= count + 1;
ce <= '0';
end if;
end if;
end process;
end Behavioral;
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Appendix 4 – LCD_control.vhd
------------------------------------------------------------------------------------------------------------- the LCD controller module
-- 1. initialize the LCD
-- 2. contains a shadow memory that copies every 0.1s into the LCD memory
-- 3. it displays 4 digits that is on dig1 to dig3 signals
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if insantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LCD_control is
generic (
frequency : integer := 50000000
);
Port ( clk : in STD_LOGIC;
reset :in std_logic;
ce : in std_logic; -- 10hz signal 0.1s
dig1 : in STD_LOGIC_VECTOR (3 downto 0);
dig2 : in STD_LOGIC_VECTOR (3 downto 0);
dig3 : in STD_LOGIC_VECTOR (3 downto 0);
dig4 : in STD_LOGIC_VECTOR (3 downto 0);
db : out STD_LOGIC_VECTOR (3 downto 0);
e : out STD_LOGIC;
rs : out STD_LOGIC;
rw : out STD_LOGIC);
end LCD_control ;
architecture Behavioral of LCD_control is
constant number_15ms: integer := frequency*15/1000;
constant number_4_1ms: integer := frequency/10000*41;
constant number_100us: integer := frequency/1000000*100;
constant number_40us: integer := frequency/1000000*40;
constant number_40ns: integer := frequency*4/100000000;
constant number_230ns: integer := frequency*23/100000000;
constant number_strobe: integer := 14;
constant number_1us: integer := frequency/1000000;
constant number_1_64ms: integer := frequency/100000*164;
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-- state name declaration for initializing the LCD
type state is (idle, wait_15ms, write_SF1, wait_4_1ms, write_SF2, wait_100us,
write_SF3, wait_40us1,
write_SF4, wait_40us2, function_set_upper, delay1,
function_set_lower, wait_40us3,
entry_mode_set_upper, delay2,
entry_mode_set_lower, wait_40us4,
display_on_off_upper, delay3,
display_on_off_lower, wait_40us5, endless_loop);
-- state machine variables; cstate - current state; nstate - next state
signal cstate,nstate : state;
-- state name declarations for write state mashine
type wrState is ( start, upper, delay, lower, wait_state, stop );
-- state machine variables
signal wr_cs, wr_ns: wrState;
-- state name declarations
type updateState is ( startUpdate, cursor, wait_cursor, data, wait_data);
signal update_cs, update_ns: updateState;
-- data counter
signal data_cnt : integer range 0 to 16;
-- for delay implemenattion several counters are implied
signal cnt1: integer range 0 to number_15ms; -- counter for 15ms delay
signal cnt2: integer range 0 to number_strobe;
signal cnt3: integer range 0 to number_100us; -- counter for 100us delay
signal cnt4: integer range 0 to number_1us;
signal cnt5: integer range 0 to number_1_64ms;
-- shadow memory for LCD. Data in this memory is copied to the LCD data memory
type mem24x8 is array (0 to 15) of std_logic_vector(7 downto 0);
signal mem: mem24x8;
signal ce1, ce2: std_logic;
begin
------------- power on initialization state machine ---------------------------- process to register the next state
process (CLK, RESET)
begin
if RESET = '1' then
cstate <= idle;
elsif CLK='1' and CLK'event then
cstate <= nstate;
end if;
end process;
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-- process to select next state
process (reset, cstate, cnt1, cnt2, cnt3, cnt4)
begin
if RESET = '1' then
nstate <= idle;
else
case (cstate) is
when idle => nstate<= wait_15ms;
when wait_15ms =>
if cnt1 = number_15ms then
nstate<=write_SF1;
else
nstate<= wait_15ms;
end if;
when write_SF1 =>
if cnt2 = number_strobe then
nstate<=wait_4_1ms;
else
nstate<= write_SF1;
end if;
when wait_4_1ms =>
if cnt1 = number_4_1ms then
nstate<=write_SF2;
else
nstate<= wait_4_1ms;
end if;
when write_SF2 =>
if cnt2 = number_strobe then
nstate<=wait_100us;
else
nstate<= write_SF2;
end if;
when wait_100us =>
if cnt3 = number_100us then
nstate<=write_SF3;
else
nstate<= wait_100us;
end if;
when write_SF3 =>
if cnt2 = number_strobe then
nstate<=wait_40us1;
else
nstate<= write_SF3;
end if;
when wait_40us1 =>
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if cnt3 = number_40us then
nstate<=write_SF4;
else
nstate<= wait_40us1;
end if;
when write_SF4 =>
if cnt2 = number_strobe then
nstate<=wait_40us2;
else
nstate<= write_SF4;
end if;
when wait_40us2 =>
if cnt3 = number_40us then
nstate<=function_set_upper;
else
nstate<= wait_40us2;
end if;
when function_set_upper =>
if cnt2 = number_strobe then
nstate<=delay1;
else
nstate<= function_set_upper;
end if;
when delay1 =>
if cnt4 = number_1us then
nstate <= function_set_lower;
else
nstate <= delay1;
end if;
when function_set_lower =>
if cnt2 = number_strobe then
nstate<=wait_40us3;
else
nstate<= function_set_lower;
end if;
when wait_40us3 =>
if cnt3 = number_40us then
nstate<=entry_mode_set_upper;
else
nstate<= wait_40us3;
end if;
when entry_mode_set_upper =>
if cnt2 = number_strobe then
nstate<=delay2;
else
nstate<= entry_mode_set_upper;
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end if;
when delay2 =>
if cnt4 = number_1us then
nstate <= entry_mode_set_lower;
else
nstate <= delay2;
end if;
when entry_mode_set_lower =>
if cnt2 = number_strobe then
nstate<=wait_40us4;
else
nstate<= entry_mode_set_lower;
end if;
when wait_40us4 =>
if cnt3 = number_40us then
nstate<=display_on_off_upper;
else
nstate<= wait_40us4;
end if;
when display_on_off_upper =>
if cnt2 = number_strobe then
nstate<=delay3;
else
nstate<= display_on_off_upper;
end if;
when delay3 =>
if cnt4 = number_1us then
nstate <= display_on_off_lower;
else
nstate <= delay3;
end if;
when display_on_off_lower =>
if cnt2 = number_strobe then
nstate<=wait_40us5;
else
nstate<= display_on_off_lower;
end if;
when wait_40us5 =>
if cnt3 = number_40us then
nstate<=endless_loop;
else
nstate<= wait_40us5;
end if;
when endless_loop => nstate <= endless_loop;
when others => nstate <= idle;
end case;
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end if;
end process;
-- process for cnt1 used by the initializatio state machine
process (CLK, RESET)
begin
if RESET = '1' then
cnt1<= 0;
elsif CLK='1' and CLK'event then
if cnt1 = number_15ms then
cnt1<=0;
elsif cstate = wait_15ms or cstate = wait_4_1ms then
cnt1<=cnt1+1;
else
cnt1<=0;
end if;
end if;
end process;
-- process for cnt2 used by the initializatio state machine
process (CLK, RESET)
begin
if RESET = '1' then
cnt2<= 0;
elsif CLK='1' and CLK'event then
if cnt2 = number_strobe then
cnt2<=0;
elsif cstate = write_SF1 or cstate = write_SF2 or cstate = write_SF3 or cstate =
write_SF4 or
cstate = function_set_upper or cstate = function_set_lower or cstate =
entry_mode_set_upper or
cstate = entry_mode_set_lower or cstate = display_on_off_upper or cstate =
display_on_off_lower --or cstate = endless_loop
or wr_cs = lower or wr_cs = upper then
cnt2<=cnt2+1;
else
cnt2<=0;
end if;
end if;
end process;
-- process for cnt3 used by the initializatio state machine
process (CLK, RESET)
begin
if RESET = '1' then
cnt3<= 0;
elsif CLK='1' and CLK'event then
if cnt3 = number_100us then
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cnt3<=0;
elsif cstate = wait_100us or cstate = wait_40us1 or cstate = wait_40us2 or cstate =
wait_40us3 or cstate = wait_40us4 or
cstate = wait_40us5 or wr_cs = wait_state then
cnt3<=cnt3+1;
else
cnt3<=0;
end if;
end if;
end process;
-- process for cnt4 used by the initializatio state machine
process (CLK, RESET)
begin
if RESET = '1' then
cnt4<= 0;
elsif CLK='1' and CLK'event then
if cnt4 = number_1us then
cnt4<=0;
elsif cstate = delay1 or cstate = delay2 or cstate = delay3 or wr_cs = delay then
cnt4<=cnt4+1;
else
cnt4<=0;
end if;
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
cnt5<=0;
elsif clk='1' and clk'event then
if cnt5 = number_1_64ms then
cnt5<=0;
elsif update_cs = wait_cursor then
cnt5 <= cnt5 + 1;
else
cnt5 <= 0;
end if;
end if;
end process;
-- process to generate the db signal
process (RESET, CLK)
begin
if RESET = '1' then
db <= "ZZZZ";
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elsif CLK='1' and CLK'event then
case cstate is
when write_SF1 => db<="0011";
when write_SF2 => db<="0011";
when write_SF3 => db<="0011";
when write_SF4 => db<="0010";
when function_set_upper => db <= "0010";
when function_set_lower => db <= "1000";
when entry_mode_set_upper => db <= "0000";
when entry_mode_set_lower => db <= "0110";
when display_on_off_upper => db <= "0000";
when display_on_off_lower => db <= "1101";
when endless_loop =>
case wr_cs is
when upper =>
if update_cs = wait_cursor then
db<="0000";
else
db <= mem(data_cnt)(7 downto 4);
end if;
when lower =>
if update_cs = wait_cursor then
db<="0001";
else
db <= mem(data_cnt)(3 downto 0);
end if;
when others => db <= "ZZZZ";
end case;
when others => db <= "ZZZZ";
end case;
end if;
end process;
-- process to geerate the rw signal
--process (CLK, RESET)
--begin
-- if RESET = '1' then
-rw<= '1';
-- elsif CLK='1' and CLK'event then
-case cstate is
-when write_SF1 => rw<='0';
-when write_SF2 => rw<='0';
-when write_SF3 => rw<='0';
-when write_SF4 => rw<='0';
-when function_set_upper => rw<='0';
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-when function_set_lower => rw<='0';
-when entry_mode_set_upper => rw<='0';
-when entry_mode_set_lower => rw<='0';
-when display_on_off_upper => rw<='0';
-when display_on_off_lower => rw<='0';
-when endless_loop =>
-case wr_cs is
-when upper => rw<='0';
-when lower => rw<='0';
-when others => rw<='1';
-end case;
-when others => rw <= '1';
-end case;
-- end if;
--end process;
rw <= '0';
-- process to generate the rs signal
process (CLK, RESET)
begin
if RESET = '1' then
rs<= '0';
elsif CLK='1' and CLK'event then
case cstate is
-when write_SF1 => rs<='0';
-when write_SF2 => rs<='0';
-when write_SF3 => rs<='0';
-when write_SF4 => rs<='0';
when function_set_upper => rs<='0';
when function_set_lower => rs<='0';
when entry_mode_set_upper => rs<='0';
when entry_mode_set_lower => rs<='0';
when display_on_off_upper => rs<='0';
when display_on_off_lower => rs<='0';
when endless_loop =>
case wr_cs is
when upper =>
if update_cs = wait_cursor then
rs<='0';
else
rs<='1';
end if;
when lower =>
if update_cs = wait_cursor then
rs<='0';
else
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rs<='1';
end if;
when others => rs<='0';
end case;
when others => rs <= '0';
end case;
end if;
end process;
-- process to generate the e signal
process (CLK, RESET)
begin
if RESET = '1' then
E <= '0';
elsif CLK='1' and CLK'event then
if cnt2 >= 2 and cnt2 <= number_strobe then
case cstate is
when write_SF1 => e<='1';
when write_SF2 => e<='1';
when write_SF3 => e<='1';
when write_SF4 => e<='1';
when function_set_upper => e<='1';
when function_set_lower => e<='1';
when entry_mode_set_upper => e<='1';
when entry_mode_set_lower => e<='1';
when display_on_off_upper => e<='1';
when display_on_off_lower => e<='1';
when endless_loop =>
case wr_cs is
when upper => e<='1';
when lower => e<='1';
when others => e<='0';
end case;
when others => e <= '0';
end case;
else
E<='0';
end if;
end if;
end process;
-- process the regsiter the digits into the shedow memory
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
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for I in 0 to 15 loop
mem(i) <=x"00";
end loop;
elsif CLK='1' and CLK'event then
mem(0)<=dig1 + x"30";
mem(1)<=dig2 + x"30";
mem(2)<=dig3 + x"30";
mem(3)<=dig4 + x"30";
mem(4)<=x"20";
mem(5)<=x"20";
mem(6)<=x"20";
mem(7)<=x"20";
mem(8)<=x"20";
mem(9)<=x"20";
mem(10)<=x"20";
mem(11)<=x"20";
mem(12)<=x"20";
mem(13)<=x"20";
mem(14)<=x"20";
mem(15)<=x"20";
end if;
end process;
------------- memory content copy state machine -------------------------- registrig the next state
process (CLK, RESET)
begin
if RESET = '1' then
wr_cs<=start;
elsif CLK='1' and CLK'event then
wr_cs<=wr_ns;
end if;
end process;
-- selectig the next state
process (RESET,wr_cs, update_cs, cnt2, cnt3, cnt4)
begin
if RESET = '1' then
wr_ns<=start;
else
case wr_cs is
when start =>
if update_cs = cursor or update_cs = data then
wr_ns <= upper;
else
wr_ns<=start;
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end if;
when upper =>
if cnt2 = number_strobe then
wr_ns<=delay;
else
wr_ns<= upper;
end if;
when delay =>
if cnt4 = number_1us then
wr_ns <= lower;
else
wr_ns <= delay;
end if;
when lower =>
if cnt2 = number_strobe then
wr_ns<=wait_state;
else
wr_ns<= lower;
end if;
when wait_state =>
if cnt3 = number_40us then
wr_ns<=stop;
else
wr_ns<= wait_state;
end if;
when stop => wr_ns<=start;
when others => wr_ns<=start;
end case;
end if;
end process;
process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
ce1<='0';
ce2<='0';
elsif CLK='1' and CLK'event then
ce1<=ce;
ce2<=ce1;
end if;
end process;
-------------------------- update state machine --------------------------- register the next state
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process (CLK, RESET)
begin
if RESET = '1' then
update_cs<=startUpdate;
elsif CLK='1' and CLK'event then
update_cs<=update_ns;
end if;
end process;
-- select th next state
process (RESET,update_cs, ce1, ce2, data_cnt, cstate, wr_cs)
begin
if RESET = '1' then
update_ns <= startUpdate;
else
case update_cs is
when startUpdate =>
if ce1='1' and ce2='0' and cstate = endless_loop then
update_ns <= cursor;
else
update_ns <= startUpdate;
end if;
when cursor => update_ns <= wait_cursor;
when wait_cursor =>
if cnt5 = number_1_64ms then
update_ns <= data;
else
update_ns <= wait_cursor;
end if;
when data => update_ns <= wait_data;
when wait_data =>
if wr_cs = stop then
if data_cnt = 3 then
update_ns <= startUpdate;
else
update_ns <= data;
end if;
else
update_ns <= wait_data;
end if;
when others => update_ns <= startUpdate;
end case;
end if;
end process;
-- process for data_cnt signal used in the below process
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process (CLK, RESET)
-- declarations
begin
if RESET = '1' then
data_cnt<=0;
elsif CLK='1' and CLK'event then
if update_cs = startUpdate then
data_cnt<=0;
elsif update_cs = wait_data and wr_cs = stop then
data_cnt<=data_cnt + 1;
end if;
end if;
end process;
end Behavioral;
------------------------------------------------------------------------------------------------------------
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Appendix 5 – op_sel.vhd
------------------------------------------------------------------------------------------------------------- module to select between numeric values and operators
-- a secondary task of the module is to decode the keypad make and break codes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Op_Sel is
Port ( clk : in STD_LOGIC;
-- system clock
reset : in STD_LOGIC;
-- system reset
Scan_DAV : in STD_LOGIC;-- scan code valid
Scan_Code : in STD_LOGIC_VECTOR (7 downto 0);
op_flag : out STD_LOGIC;-- if the scan code is an operation then it's valid
num_flag : out STD_LOGIC;--when scan code is a number then valid
calc_flag : out STD_LOGIC;-- when scan code is Enter it is valid
Op : out STD_LOGIC_VECTOR (1 downto 0);--operator 0 <= +; 1 <= -; 2 <= *;
3 <= /;
Num : out STD_LOGIC_VECTOR (3 downto 0);--numric value
ReadDone: out std_logic);
end Op_Sel;
architecture Behavioral of Op_Sel is
signal break: boolean;
signal break_logic: boolean;
signal op_flag_logic: std_logic;
signal num_flag_logic : STD_LOGIC;
signal calc_flag_logic : STD_LOGIC;
signal Op_logic : STD_LOGIC_VECTOR (1 downto 0);
signal Num_logic : STD_LOGIC_VECTOR (3 downto 0);
begin
process (clk, reset)
-- declarations
begin
if reset = '1' then
ReadDone <= '0';
elsif clk='1' and clk'event then
ReadDone <= Scan_DAV;
end if;
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end process;
-- process to select the arrived scan code; if the scan code is a numeric value the num_flag
is strobed;
-- if the scan code of an operation then the op_code is strobed; if the enter was pressed
then the calc_flag is strobed
-- decoding the numric value attached to the keypad or the operation
process (Scan_DAV,Scan_Code,break)
-- declarations
begin
op_flag_logic <= '0';
num_flag_logic <= '0';
calc_flag_logic <= '0';
Op_logic <= "00";
Num_logic <= "0000";
break_logic <= break;
if Scan_DAV = '1' then
case Scan_Code is
when x"F0" => -- break code is received
break_logic <= true;
when x"5A" => -- enter is pressed
if break then
calc_flag_logic <= '1';
break_logic <= false;
end if;
when x"79" => -- addition
if break then
Op_logic <= "00";
op_flag_logic <= '1';
break_logic <= false;
end if;
when x"7b" => -- substraction
if break then
Op_logic <= "01";
op_flag_logic <= '1';
break_logic <= false;
end if;
when x"7c" => -- multiplication
if break then
Op_logic <= "10";
op_flag_logic <= '1';
break_logic <= false;
end if;
when x"4a" => -- division
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if break then
Op_logic <= "11";
op_flag_logic <= '1';
break_logic <= false;
end if;
when x"70" => -- keypad '0'
if break then
Num_logic <= "0000";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"69" => -- keypad '1'
if break then
Num_logic <= "0001";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"72" => -- keypad '2'
if break then
Num_logic <= "0010";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"7A" => -- keypad '3'
if break then
Num_logic <= "0011";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"6B" => -- keypad '4'
if break then
Num_logic <= "0100";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"73" => -- keypad '5'
if break then
Num_logic <= "0101";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"74" => -- keypad '6'
if break then
Num_logic <= "0110";
num_flag_logic <= '1';
break_logic <= false;
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end if;
when x"6C" => -- keypad '7'
if break then
Num_logic <= "0111";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"75" => -- keypad '8'
if break then
Num_logic <= "1000";
num_flag_logic <= '1';
break_logic <= false;
end if;
when x"7D" => -- keypad '9'
if break then
Num_logic <= "1001";
num_flag_logic <= '1';
break_logic <= false;
end if;
when others => -- discard other key
op_flag_logic <= '0';
num_flag_logic <= '0';
calc_flag_logic <= '0';
Op_logic <= "00";
Num_logic <= "0000";
end case;
end if;
end process;
process (clk, reset)
-- declarations
begin
if reset = '1' then
-- Asynchronous reset code
op_flag <= '0';
num_flag <= '0';
calc_flag <= '0';
Op <= "00";
Num <= "0000";
break <= false;
elsif clk='1' and clk'event then
-- synchronous code
op_flag <= op_flag_logic;
num_flag <= num_flag_logic;
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calc_flag <= calc_flag_logic;
Op <= Op_logic;
Num <= Num_logic;
break <= break_logic;
end if;
end process;
end Behavioral;
------------------------------------------------------------------------------------------------------------
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Appendix 6 – ps2_ctrl.vhd
------------------------------------------------------------------------------------------------------------- Only the Receive function is implemented !
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_std.all;
-- -------------------------------------Entity PS2_Ctrl is
-- -------------------------------------generic (FilterSize : positive := 8);
port( Clk : in std_logic; -- System Clock
Reset : in std_logic; -- System Reset
PS2_Clk : in std_logic; -- Keyboard Clock Line
PS2_Data : in std_logic; -- Keyboard Data Line
DoRead : in std_logic; -- From outside when reading the scan code
Scan_Err : out std_logic; -- To outside : Parity or Overflow error
Scan_DAV : out std_logic; -- To outside when a scan code has arrived
Scan_Code : out std_logic_vector(7 downto 0) -- Eight bits Data Out
);
end PS2_Ctrl;
-- -------------------------------------Architecture RTL of PS2_Ctrl is
-- --------------------------------------- Fully synchronous solution, same Filter on PS2_Clk.
-- Note: PS2_Data is resynchronized though this should not be
-- necessary (qualified by Fall_Clk and does not change at that time).
-- Note the tricks to correctly interpret 'H' as '1' in RTL simulation.
signal PS2_Datr : std_logic;
subtype Filter_t is std_logic_vector(FilterSize-1 downto 0);
signal Filter : Filter_t;
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned (3 downto 0);
signal Parity : std_logic;
signal Scan_DAVi : std_logic;
signal S_Reg : std_logic_vector(8 downto 0);
signal PS2_Clk_f : std_logic;
Type State_t is (Idle, Shifting);
signal State : State_t;
begin
Scan_DAV <= Scan_DAVi;
-- This filters digitally the raw clock signal coming from the keyboard :
-- * Eight consecutive PS2_Clk=1 makes the filtered_clock go high
-- * Eight consecutive PS2_Clk=0 makes the filtered_clock go low
-- Implies a (FilterSize+1) x Tsys_clock delay on Fall_Clk wrt Data
-- Also in charge of the re-synchronization of PS2_Data
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process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = (FilterSize-1 downto 0 => '1') then
PS2_Clk_f <= '1';
elsif Filter = (FilterSize-1 downto 0 => '0') then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
-- This simple State Machine reads in the Serial Data
-- coming from the PS/2 peripheral.
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Parity <= '0';
Scan_Davi <= '0';
Scan_Err <= '0';
elsif rising_edge (Clk) then
if DoRead='1' then
Scan_Davi <= '0'; -- note: this assignmnt can be overriden
end if;
case State is
when Idle =>
Parity <= '0';
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
Scan_Err <= '0';
State <= Shifting;
end if;
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when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
-- Error is (wrong Parity) or (Stop='0') or Overflow
Scan_Err <= (not Parity) or (not PS2_Datr) or Scan_DAVi;
Scan_Davi <= '1';
Scan_Code <= S_Reg(7 downto 0);
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -Shift right
Parity <= Parity xor PS2_Datr;
end if;
when others => -- never reached
State <= Idle;
end case;
end if;
end process;
end RTL;
------------------------------------------------------------------------------------------------------------
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Appendix 7 – s3astarter.ucf
-----------------------------------------------------------------------------------------------------------##############################################################################
## Copyright (c) 2006, 2007 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
##############################################################################
##
____ ____
## / /\/ /
## /___/ \ / Vendor:
Xilinx
## \ \ \/
Version:
1.0.1
## \ \
Filename:
starter_kit_constraints.ucf
## / /
Date Created: December 25, 2006
## /___/ /\
Last Modified: April 1, 2007
## \ \ / \
## \___\/\___\
##
## Devices: Spartan-3 Generation FPGA
## Purpose: Complete constraint file for Spartan-3A(N) Starter Kit
## Contact: crabill@xilinx.com
## Reference: None
##
## Revision History:
##
Rev 1.0.0 - (crabill) Created December 25, 2006 for PCB revision C.
##
Rev 1.0.1 - (crabill) Modified April 1, 2007 to mention revision D
##
of the PCB and applicability to Spartan-3AN.
##
##############################################################################
##
## LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".
## Xilinx and its licensors make and you receive no warranties or conditions,
## express, implied, statutory or otherwise, and Xilinx specifically disclaims
## any implied warranties of merchantability, non-infringement, or fitness for
## a particular purpose. Xilinx does not warrant that the functions contained
## in these designs will meet your requirements, or that the operation of
## these designs will be uninterrupted or error free, or that defects in the
## designs will be corrected. Furthermore, Xilinx does not warrant or make any
## representations regarding use or the results of the use of the designs in
## terms of correctness, accuracy, reliability, or otherwise.
##
## LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable
## for any loss of data, lost profits, cost or procurement of substitute goods
## or services, or for any special, incidental, consequential, or indirect
## damages arising from the use or operation of the designs or accompanying
## documentation, however caused and on any theory of liability. This
## limitation will apply even if Xilinx has been advised of the possibility
## of such damage. This limitation shall apply not-withstanding the failure
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## of the essential purpose of any limited remedies herein.
##
##############################################################################
## Copyright (c) 2006, 2007 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
##############################################################################
# On this board, VCCAUX is 3.3 volts.
CONFIG VCCAUX = "3.3" ;
# Configure SUSPEND mode options.
CONFIG ENABLE_SUSPEND = "FILTERED" ;
# FILTERED is appropriate for use with the switch on this board. Other allowed
# settings are NO or UNFILTERED. If set NO, the AWAKE pin becomes general I/O.
# Please read the FPGA User Guide for more information.
# Configure POST_CRC options.
CONFIG POST_CRC = "DISABLE" ;
#
#
#
#
DISABLE the post-configuration CRC checking so INIT_B is available for
general I/O after configuration is done. On this board, INIT_B is used
after configuration to control the Platform Flash device. Other allowed
settings are ENABLE. Please read the FPGA User Guide for more information.
##############################################################################
# These are sample constraints for the three clock inputs. You will need
# to change these constraints to suit your application. Please read the
# FPGA Development System Reference Guide for more information on expressing
# timing constraints for your design.
##############################################################################
NET "CLK"
LOC = "E12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
#OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_50M" ;
#OFFSET = OUT 20.000 AFTER "CLK_50M" ;
#
#NET "CLK_AUX"
LOC = "V12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
#OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_AUX" ;
#OFFSET = OUT 20.000 AFTER "CLK_AUX" ;
#
#NET "CLK_SMA"
LOC = "U12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
#OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_SMA" ;
#OFFSET = OUT 20.000 AFTER "CLK_SMA" ;
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##############################################################################
# Discrete Indicators (LED)
##############################################################################
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"LED<0>"
;
"LED<1>"
;
"LED<2>"
;
"LED<3>"
;
"LED<4>"
;
"LED<5>"
;
"LED<6>"
;
"LED<7>"
;
LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "T19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "U20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "U19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "V19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "V20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "Y22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "W21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
##############################################################################
# Character Display (LCD)
##############################################################################
#NET "LCD_DB<0>"
SLOW ;
#NET "LCD_DB<1>"
SLOW ;
#NET "LCD_DB<2>"
SLOW ;
#NET "LCD_DB<3>"
SLOW ;
NET "DB<0>"
LOC
NET "DB<1>"
LOC
NET "DB<2>"
LOC
NET "DB<3>"
LOC
NET "E"
LOC
NET "RS"
LOC
NET "RW"
LOC
LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
=
=
=
=
=
=
=
"Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
"AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
"AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
"AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
"AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
"Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
"W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
##############################################################################
# Stereo Audio Output (AUD)
##############################################################################
#NET "AUD_L"
SLOW ;
LOC = "Y10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
96
Simple calculator using FPGA
#NET "AUD_R"
SLOW ;
Anish Peter
N0704982
LOC = "V10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
##############################################################################
# Video Output Port (VGA)
##############################################################################
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
"VGA_B<0>"
;
"VGA_B<1>"
;
"VGA_B<2>"
;
"VGA_B<3>"
;
"VGA_G<0>"
;
"VGA_G<1>"
;
"VGA_G<2>"
;
"VGA_G<3>"
;
"VGA_R<0>"
;
"VGA_R<1>"
;
"VGA_R<2>"
;
"VGA_R<3>"
;
"VGA_HSYNC"
;
"VGA_VSYNC"
;
LOC = "C7"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D7"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B9"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C9"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C5"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D5"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C6"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D6"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A3"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B3"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B8"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C8"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
##############################################################################
# Hirose Expansion Connector (FX2)
##############################################################################
#NET
SLOW
#NET
SLOW
#NET
SLOW
"FX2_IO<1>"
;
"FX2_IO<2>"
;
"FX2_IO<3>"
;
LOC = "A13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
97
Simple calculator using FPGA
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"FX2_IO<4>"
;
"FX2_IO<5>"
;
"FX2_IO<6>"
;
"FX2_IO<7>"
;
"FX2_IO<8>"
;
"FX2_IO<9>"
;
"FX2_IO<10>"
;
"FX2_IO<11>"
;
"FX2_IO<12>"
;
"FX2_IO<13>"
;
"FX2_IO<14>"
;
"FX2_IO<15>"
;
"FX2_IO<16>"
;
"FX2_IO<17>"
;
"FX2_IO<18>"
;
"FX2_IO<19>"
;
"FX2_IO<20>"
;
"FX2_IO<21>"
;
"FX2_IO<22>"
;
"FX2_IO<23>"
;
"FX2_IO<24>"
;
"FX2_IO<25>"
;
"FX2_IO<26>"
;
Anish Peter
N0704982
LOC = "B15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "A20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "B20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "F18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "F19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "F20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
98
Simple calculator using FPGA
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"FX2_IO<27>"
;
"FX2_IO<28>"
;
"FX2_IO<29>"
;
"FX2_IO<30>"
;
"FX2_IO<31>"
;
"FX2_IO<32>"
;
"FX2_IO<33>"
;
"FX2_IO<34>"
;
"FX2_IO<35>"
;
"FX2_IO<36>"
;
"FX2_IO<37>"
;
"FX2_IO<38>"
;
"FX2_IO<39>"
;
"FX2_IO<40>"
;
"FX2_CLKIN"
;
"FX2_CLKIO"
;
"FX2_CLKOUT"
;
Anish Peter
N0704982
LOC = "G20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "G19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "H19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "J18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "K18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "K17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "K19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "K20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "L19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "M20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "L20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "P20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "M22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "L21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "L22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
##############################################################################
# Accessory Headers (J18, J19, J20)
##############################################################################
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"J18_IO<1>"
;
"J18_IO<2>"
;
"J18_IO<3>"
;
"J18_IO<4>"
;
LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
99
Simple calculator using FPGA
Anish Peter
N0704982
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"J19_IO<1>"
;
"J19_IO<2>"
;
"J19_IO<3>"
;
"J19_IO<4>"
;
LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"J20_IO<1>"
;
"J20_IO<2>"
;
"J20_IO<3>"
;
"J20_IO<4>"
;
LOC = "V14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "W18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "V17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "W16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "V16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
##############################################################################
# Mouse and/or Keyboard Connector (PS2)
##############################################################################
# Primary connection, simply plug device into connector.
NET "PS2_CLK"
LOC = "W12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW
;
NET "PS2_DATA"
LOC = "V11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW
;
# Secondary connection, use requires a splitter cable.
#NET "PS2_CLK2"
LOC = "U11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "PS2_DATA2"
LOC = "Y12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
##############################################################################
# High-Speed LVDS Receiver Connector (RX)
##############################################################################
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
"RX_CLK_N"
"RX_CLK_P"
"RX_N<0>"
"RX_P<0>"
"RX_N<1>"
"RX_P<1>"
"RX_N<2>"
"RX_P<2>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
"A11"
"A12"
"B4"
"A4"
"A5"
"B6"
"A6"
"A7"
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
100
=
=
=
=
=
=
=
=
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
;
;
;
;
;
;
;
;
Simple calculator using FPGA
#NET
#NET
#NET
#NET
"RX_N<3>"
"RX_P<3>"
"RX_N<4>"
"RX_P<4>"
LOC
LOC
LOC
LOC
=
=
=
=
"A8"
"A9"
"C10"
"A10"
Anish Peter
N0704982
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVDS_33
LVDS_33
LVDS_33
LVDS_33
;
;
;
;
##############################################################################
# High-Speed LVDS Transmitter Connector (TX)
##############################################################################
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
"TX_CLK_N"
"TX_CLK_P"
"TX_N<0>"
"TX_P<0>"
"TX_N<1>"
"TX_P<1>"
"TX_N<2>"
"TX_P<2>"
"TX_N<3>"
"TX_P<3>"
"TX_N<4>"
"TX_P<4>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
"AB10"
"AA10"
"AA3"
"AB2"
"AA4"
"AB3"
"AB6"
"AA6"
"AB7"
"Y7"
"AB8"
"AA8"
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
;
;
;
;
;
;
;
;
;
;
;
;
##############################################################################
# Directional Push-Buttons (BTN)
##############################################################################
#NET
#NET
#NET
#NET
"BTN_EAST"
"BTN_NORTH"
"BTN_SOUTH"
"BTN_WEST"
LOC
LOC
LOC
LOC
=
=
=
=
"T16"
"T14"
"T15"
"U15"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
PULLDOWN
PULLDOWN
PULLDOWN
PULLDOWN
;
;
;
;
##############################################################################
# Rotary Knob (ROT)
##############################################################################
NET "RESET"
#NET "ROT_A"
#NET "ROT_B"
LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP ;
LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP ;
##############################################################################
# Mechanical Switches (SW)
##############################################################################
#NET
#NET
#NET
#NET
"SW<0>"
"SW<1>"
"SW<2>"
"SW<3>"
LOC
LOC
LOC
LOC
=
=
=
=
"V8"
"U10"
"U8"
"T9"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
101
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
;
;
;
;
Simple calculator using FPGA
Anish Peter
N0704982
##############################################################################
# Serial Ports (RS232)
##############################################################################
#NET
#NET
SLOW
#
#NET
#NET
SLOW
"RS232_DCE_RXD" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
"RS232_DCE_TXD" LOC = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
;
"RS232_DTE_RXD" LOC = "F16" | IOSTANDARD = LVCMOS33 ;
"RS232_DTE_TXD" LOC = "E15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
;
##############################################################################
# Regulator I2C Control (REG)
##############################################################################
# Controls VCCINT, VCCAUX, and VCCO_012 supply rails.
#NET "REG1_SCL"
LOC = "E13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "REG1_SDA"
LOC = "D13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
# Controls SDRAM, TERM, and VREF supply rails.
#NET "REG2_SCL"
LOC = "D11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "REG2_SDA"
LOC = "F13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
##############################################################################
# 10/100 Ethernet (E)
##############################################################################
#NET "E_TX_CLK"
#OFFSET = IN 5.000
#OFFSET = OUT 10.000
#
#NET "E_RX_CLK"
#OFFSET = IN 5.000
#OFFSET = OUT 10.000
#
#NET "E_NRST"
SLOW ;
#NET "E_MDC"
SLOW ;
#NET "E_MDIO"
SLOW ;
LOC = "E11" | IOSTANDARD = LVCMOS33 | PERIOD = 40.000 ;
VALID 10.000 BEFORE "E_TX_CLK" ;
AFTER "E_TX_CLK" ;
LOC = "C12" | IOSTANDARD = LVCMOS33 | PERIOD = 40.000 ;
VALID 10.000 BEFORE "E_RX_CLK" ;
AFTER "E_RX_CLK" ;
LOC = "D15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
102
Simple calculator using FPGA
#
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#NET
FAST
#
#NET
#NET
#NET
#NET
#NET
#
#NET
#NET
#NET
#NET
"E_TXD<0>"
;
"E_TXD<1>"
;
"E_TXD<2>"
;
"E_TXD<3>"
;
"E_TX_EN"
;
Anish Peter
N0704982
LOC = "F8"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E7"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E6"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "F7"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "D8"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
"E_RXD<0>"
"E_RXD<1>"
"E_RXD<2>"
"E_RXD<3>"
"E_RX_DV"
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
"G7"
"G8"
"G9"
"H9"
"H10"
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
;
"E_RX_ERR"
"E_NINT"
"E_CRS"
"E_COL"
LOC
LOC
LOC
LOC
=
=
=
=
"G10"
"B2"
"H12"
"G12"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
;
| PULLUP ;
| PULLDOWN ;
| PULLDOWN ;
PULLUP
PULLUP
PULLUP
PULLUP
;
;
;
;
##############################################################################
# Serial Peripheral System
##############################################################################
#
#NET "SPI_SCK"
LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#
#NET "SPI_MOSI"
LOC = "AB14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "SPI_MISO"
LOC = "AB20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "AMP_OUT"
LOC = "T7" | IOSTANDARD = LVCMOS33 ; # Private MISO for AMP
#NET "DAC_OUT"
LOC = "V7" | IOSTANDARD = LVCMOS33 ; # Private MISO for DAC
#NET "ADC_OUT"
LOC = "D16" | IOSTANDARD = LVCMOS33 ; # Private MISO for ADC
#
#NET "SPI_SS_B"
LOC = "Y4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "ALT_SS_B"
LOC = "Y5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "FPGA_INIT_B" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
#NET "AMP_CS"
LOC = "W6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
SLOW ;
103
Simple calculator using FPGA
#NET
SLOW
#NET
SLOW
#
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
Anish Peter
N0704982
"DAC_CS"
;
"AD_CONV"
;
LOC = "W7"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "Y6"
| IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
"AMP_SHDN"
;
"DAC_CLR"
;
"ST_SPI_WP"
;
"DATAFLASH_WP"
;
"DATAFLASH_RST"
;
LOC = "W15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AB13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
##############################################################################
# Parallel Flash (NF)
##############################################################################
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
#
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"NF_CE"
;
"NF_BYTE"
;
"NF_OE"
;
"NF_RP"
;
"NF_WE"
;
"NF_WP"
;
"NF_STS"
LOC = "W20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
"NF_A<1>"
;
"NF_A<2>"
;
"NF_A<3>"
;
"NF_A<4>"
;
"NF_A<5>"
;
"NF_A<6>"
;
LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "Y21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "W19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "R22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "AA22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "E14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "P22" | IOSTANDARD = LVCMOS33 ;
LOC = "R19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "N21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "N20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
104
Simple calculator using FPGA
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
#NET
SLOW
"NF_A<7>"
;
"NF_A<8>"
;
"NF_A<9>"
;
"NF_A<10>"
;
"NF_A<11>"
;
"NF_A<12>"
;
"NF_A<13>"
;
"NF_A<14>"
;
"NF_A<15>"
;
"NF_A<16>"
;
"NF_A<17>"
;
"NF_A<18>"
;
"NF_A<19>"
;
"NF_A<20>"
;
"NF_A<21>"
;
Anish Peter
N0704982
LOC = "N19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "N18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "N17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "K22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "J22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "J21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "J20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "H22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "G22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "H21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "H20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "F22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "F21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
LOC = "C21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
# Note: NF_D<0> pin is shared with SPI_MISO pin which was
#NET "NF_D<1>"
LOC = "Y17" | IOSTANDARD = LVCMOS33
SLOW ;
#NET "NF_D<2>"
LOC = "AA17" | IOSTANDARD = LVCMOS33
SLOW ;
#NET "NF_D<3>"
LOC = "U13" | IOSTANDARD = LVCMOS33
SLOW ;
#NET "NF_D<4>"
LOC = "AB11" | IOSTANDARD = LVCMOS33
SLOW ;
#NET "NF_D<5>"
LOC = "Y11" | IOSTANDARD = LVCMOS33
SLOW ;
#NET "NF_D<6>"
LOC = "AB9" | IOSTANDARD = LVCMOS33
SLOW ;
#NET "NF_D<7>"
LOC = "Y9" | IOSTANDARD = LVCMOS33
SLOW ;
105
previously declared.
| DRIVE = 8 | SLEW =
| DRIVE = 8 | SLEW =
| DRIVE = 8 | SLEW =
| DRIVE = 8 | SLEW =
| DRIVE = 8 | SLEW =
| DRIVE = 8 | SLEW =
| DRIVE = 8 | SLEW =
Simple calculator using FPGA
#NET "NF_D<8>"
LOC
SLOW ;
#NET "NF_D<9>"
LOC
SLOW ;
#NET "NF_D<10>"
LOC
SLOW ;
#NET "NF_D<11>"
LOC
SLOW ;
#NET "NF_D<12>"
LOC
SLOW ;
#NET "NF_D<13>"
LOC
SLOW ;
#NET "NF_D<14>"
LOC
SLOW ;
#NET "NF_D<15>"
LOC
SLOW ;
# Note: NF_D<15> becomes
Anish Peter
N0704982
= "T20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "W22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "V22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "U21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "U22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "T22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "R21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
= "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NF_A<0> when NF_BYTE is asserted (for 8-bit mode).
##############################################################################
# DDR2 SDRAM Device (SD)
##############################################################################
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#
#NET
#NET
#NET
#
#NET
#NET
#NET
#NET
"SD_A<0>"
"SD_A<1>"
"SD_A<2>"
"SD_A<3>"
"SD_A<4>"
"SD_A<5>"
"SD_A<6>"
"SD_A<7>"
"SD_A<8>"
"SD_A<9>"
"SD_A<10>"
"SD_A<11>"
"SD_A<12>"
"SD_A<13>"
"SD_A<14>"
"SD_A<15>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
"SD_BA<0>"
"SD_BA<1>"
"SD_BA<2>"
LOC = "P3"
LOC = "R3"
LOC = "P5"
| IOSTANDARD = SSTL18_I ;
| IOSTANDARD = SSTL18_I ;
| IOSTANDARD = SSTL18_I ;
"SD_RAS"
"SD_CAS"
"SD_CK_N"
"SD_CK_P"
LOC
LOC
LOC
LOC
|
|
|
|
=
=
=
=
"R2"
"T4"
"R1"
"U3"
"U2"
"U4"
"U1"
"Y1"
"W1"
"W2"
"T3"
"V1"
"Y2"
"V3"
"V4"
"W3"
"M3"
"M4"
"M2"
"M1"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
106
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Simple calculator using FPGA
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
#NET
Anish Peter
N0704982
"SD_CKE"
"SD_ODT"
"SD_CS"
"SD_WE"
"SD_LDM"
"SD_LDQS_N"
"SD_LDQS_P"
"SD_LOOP_IN"
"SD_LOOP_OUT"
"SD_UDM"
"SD_UDQS_N"
"SD_UDQS_P"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
"N3"
"P1"
"M5"
"N4"
"J3"
"K2"
"K3"
"H4"
"H3"
"E3"
"J5"
"K6"
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
;
;
;
;
;
;
;
;
"SD_DQ<0>"
"SD_DQ<1>"
"SD_DQ<2>"
"SD_DQ<3>"
"SD_DQ<4>"
"SD_DQ<5>"
"SD_DQ<6>"
"SD_DQ<7>"
"SD_DQ<8>"
"SD_DQ<9>"
"SD_DQ<10>"
"SD_DQ<11>"
"SD_DQ<12>"
"SD_DQ<13>"
"SD_DQ<14>"
"SD_DQ<15>"
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
"H1"
"K5"
"K1"
"L3"
"L5"
"L1"
"K4"
"H2"
"F2"
"G4"
"G1"
"H6"
"H5"
"F1"
"G3"
"F3"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
SSTL18_I
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
##############################################################################
------------------------------------------------------------------------------------------------------------
107