DESIGN AND DC ANALYSIS OF SRAM 6T CELL
INTERNSHIP REPORT
Submitted By
NISHA .P. JOSHI
Roll no. - 09307201(temporary)
Graduate Student
University Of Illinois, Chicago
njoshi7@uic.edu (UIN- 677316512)
Under the guidance of
Prof. Sachin B. Patkar
Department of Electrical Engineering
Indian Institute of Technology, Bombay
Mumbai-400076
May 20 – July 20, 2010
1
INDIAN INSTITUTE OF TECHNOLOGY BOMBAY, INDIA
CERTIFICATE
This is to certify that Ms. Nisha Joshi has successfully completed her Internship at IIT
Bombay, on Design and DC Analysis of SRAM 6T Cell, from 20th May-20th July.
IIT Bombay
Date:
Prof. Sachin Ptakar
2
ACKNOWLEDGEMENT
I would like to thank Professor Sachin B. Patkar, Professor Jayanta Mukherji and Rewati
Raman Raut for their reviews and invaluable comments and suggestions for the clarity of
this report. I would like to thank the VLSI Lab staff Marshnil, Vineeth, Ani Xavier,
Pallavi and Rajesh for helping me out with the Cadence 6.1 Tool issue and also for giving
me few designing tip. I would also like to thank HPC lab colleagues for giving me ideas
and helping me with my work.
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CONTENTS
1. Introduction To Memory ………………………………………………………. 5
a. Primary Storage…………………………………………………….........5
b. Secondary Storage……………………………………………………….5
c. Tertiary Storage………………………………………………………….5
d. Offline Storage…………………………………………………………..5
2. Classification of Memory ………………………………………………….........7
a. Volatile Memories……………………………………………………….7
i.
DRAM…………………………………………………………7
ii.
SRAM………………………………………………………….7
b. Non- Volatile Memories…………………………………………………8
i.
ROM…………………………………………………………...8
ii.
FLASH………………………………………………………...8
3. Static Random Access Memory…………………………………………………10
a. Row Decoder…………………………………………………………….10
b. 6T Bit Cell Array………………………………………………………..13
c. Sense Amplifier…………………………………………………………14
d. Control Circuit…………………………………………………………..15
4. Detailed Analysis of 6T Cell Read Operation…………………………………..17
5. Analog Analysis of 6T Cell Read Operation
a. DC Analysis of Read Zero…………………………………………........19
b. DC Analysis of Read One……………………………………………….23
6. Detailed Analysis of 6T Cell Write Operation…………………………………..26
7. Analog Analysis of 6T Cell Write Operation
a. DC Analysis of Write One……………………………………………….28
b. DC Analysis of Write Zero…………………………………………........31
8. Problems to be Solved…………………………………………………………...35
9. How to use Cadence 6.1…………………………………………………….........36
10. References………………………………………………………………………..51
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I. Introduction to Memory:
Computer data storage, often called storage or memory, refers to computer
components and recording media that retain digital data used for computing for some
interval of time. The main purpose of storage is that without a significant amount of
memory, a computer would merely be able to perform fixed operations and immediately
output the result. It has to be reconfigured every time an operation needs to be performed.
Hierarchy of storage is as shown in Figure 1.
1. Primary Storage:
Primary storage (or main memory or internal memory), often referred to simply as
memory, is the only one directly accessible to the CPU. The CPU continuously
reads instructions stored there and executes them as required. Any data actively
operated on is also stored there in uniform manner.
2. Secondary Storage:
Secondary storage (or external memory) differs from primary storage in that it is
not directly accessible by the CPU. The computer usually uses its input/output
channels to access secondary storage and transfers the desired data using
intermediate area in primary storage. Secondary storage does not lose the data
when the device is powered down—it is non-volatile. Per unit, it is typically also
two orders of magnitude less expensive than primary storage. Consequently,
modern computer systems typically have two orders of magnitude more
secondary storage than primary storage and data is kept for a longer time there.
3. Tertiary Storage:
Tertiary storage or tertiary memory provides a third level of storage. Typically it
involves a robotic mechanism which will mount (insert) and dismount removable
mass storage media into a storage device according to the system's demands; this
data is often copied to secondary storage before use.
4. Offline Storage:
Off-line storage is used to transfer information, since the detached medium can be
easily physically transported. Additionally, in case a disaster, for example a fire,
destroys the original data, a medium in a remote location will probably be
unaffected, enabling disaster recovery. Off-line storage increases general
information security.
5
Figure1. Types of Computer data storage
6
II. Classification of CMOS Memories:
CMOS MEMORIES
VOLATILE
DYNAMIC
RANDOM ACCESS
MEMORY (DRAM)
STATIC RANDOM
ACCESS MEMORY
(SRAM)
NON VOLATILE
READ ONLY
MEMORIES (ROM)
FLASH MEMORIES
The memory can be classified as volatile and non-volatile memories.
1) Volatile memories:
These are memories that require power to maintain the stored information. Randomaccess memory (RAM) is a form of computer data storage. It takes the form of
integrated circuits that allow stored data to be accessed in any order. "Random" refers
to the idea that any piece of data can be returned in a constant time, regardless of its
physical location and whether or not it is related to the previous piece of data.
a) Dynamic- Dynamic Random Access Memory (DRAM):
Dynamic random access memory (DRAM) is a type of random access memory that
stores each bit of data in a separate capacitor within an integrated circuit. Since real
capacitors leak charge, the information eventually fades unless the capacitor charge
is refreshed periodically. Because of this refresh requirement, it is a dynamic
memory as opposed to SRAM and other static memory. The advantage of DRAM is
its structural simplicity only one transistor and a capacitor are required per bit,
compared to six transistors in SRAM.
b) Static- Static Random Access Memory (SRAM):
Static Random Access Memory (SRAM) is a type of semiconductor memory where
the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be
periodically refreshed, as SRAM uses bistable latching circuitry to store each bit.
SRAM exhibits data reminisce but is still volatile in the conventional sense that data
is eventually lost when the memory is not powered.
2) Non- Volatile Memories:
7
Non-volatile memory, NVM or non-volatile storage, is computer memory that can
retain the stored information even when not powered. Examples of non-volatile
memory include read-only memory, flash memory and most types of magnetic
computer storage devices.
a) Read Only Memory (ROM): Is a class of storage which is fabricated with desired
data permanently fixed in it, thus it cannot be modified.
b) FLASH: Is a non-volatile computer storage technology that can be electrically
erased and reprogrammed. Since flash memory is non-volatile, no power is
needed to maintain the information stored in the chip.
Working of memory with processor:
The processor communicates with the memory system memory interface. The processor
sends the address over the address bus. For read, MemWrite is 0 and the memory returns
the data on the ReadData bus. For write, MemWrite is 1 and the memory returns the data
on the WriteData bus. The process is shown in the block diagram below.
Figure 2.1 Memory Interface
Computers store most commonly used instructions and data in faster but smaller memory
called cache. Cache is usually built out of SRAM on the same chip as the processor. If
the processor requests data that is available in the cache, it is returned quickly. This is
called cache hit. Otherwise, the processor retrieves the data from main memory (DRAM).
This is called cache miss.
Figure 2.2 Cache
The performance analysis i.e. the miss rate, the hit rate and average memory access time
(AMAT) where AMAT is the average time a processor must wait for memory per load or
store instruction.
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III. Static Random Access Memory (SRAM)
Random access memories which can retain their data content as long as electric power is
supplied to the memory device, and do not need any rewrite or refresh operation, are
called static random access memories.
The following elements are required to build a SRAM,
 Row Decoder & Column Decoder: The operation of the SRAM starts with the
detection of an address change in the address register, and the decoders select a
single memory cell.
 6T bit cell Array: is used as it has fixed cell size and easy to design as a logic
circuit. It consists of 6 CMOS transistor which performs read and write operation.
 Sense Amplifier: main function is to sense or detect stored data from a read
selected memory cell.
 Control Circuit: to access the bit cells the read/write circuitry is implemented to
control the data being read or written. This is achieved by control circuitry which
consists of tristate buffers.
Figure3.1 Typical Memory Architecture
1. Row Decoder:
SRAM adopts a multi-divided memory cell array structure to achieve high speed
word decoding and reduce column power dissipation. The multi-stage decoder circuit
technique is adopted as it has advantage over the one-stage decoder in reducing the
number transistors and fan-in. For column decoders, which select the desired bit pairs
out of the set of the sets of bit pairs in the selected row a typical dynamic and gate
could be used.
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Figure 3.2 Static CMOS AND Gate
Figure 3.3 Dynamic CMOS AND Gate
Digital Analysis of Row Decoder:
The address lines i.e. the word line is generated using this logic. For example, if we
have 1024*32 bit memory, we need a 10:1024 (2^10) decoder. Since to obtain such a
large decoder logic with and gates makes it slower, cascading of multiple smaller
decoders is done. Here, there are 2 approaches that were considered:
a. First we design 2:4 decoders  4:168:256, four of 8:256 and one 2:4 is
used to generate 10:1024. Care should be taken about the LSB and MSB
placement.
b. We use 2:4 decoders and 3:8 decoders  5:32, then 33 of them are used to
generate 10:1024 i.e. first 5:32 is used to generate the first stage and the
remaining 32 are used to generate the second stage of 1024 outputs.
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Figure 3.4 Decoders
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Table 3.1 Truth table for 5:32 decoder
C
D
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
E
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Output
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
12
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
D23
D24
D25
D26
D27
D28
D29
D30
D31
2. 6T Bit Cell Array:
The basic cell for static RAM consists of 6 transistors in which there are two pass
gates. We are using 2 inverters, which are cross coupled and they store the data being
read or written whereas the pass transistors purpose is to select the cell which the
word line activates and pass the data inputs to be read or written to the cross coupled
inverters. The circuit diagram of 6T bit cell is shown below.
Figure 3.5 6T SRAM Cell
Digital Analysis 6T SRAM Cell:
1. READ: Assume that the value of memory is 1 stored at Q. The read cycle is
started and the word line WL is asserted enabling both access transistors. Values
stored in Q and Qbar are transferred to the bit lines by leaving BL at its
precharged value and discharging BLbar through M1 and M5 to logical 0. On BL
side the transistors M4 and M6 pull the bit line toward Vdd a logical 1.
2. WRITE: Assume that the value of memory is 1 stored at Q. The value to be
written is placed on BL and BLbar. The write cycle is started and the word line
WL is asserted enabling both access transistors. Lets say, we want to write 0, BL
is equal to 0, Q is equal to 1 thus the transistors M6 and M5 change stage and the
value gets written.
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3. Sense Amplifier:
Sense amplifiers, in association with memory cells, are key elements in defining the
performance and environmental tolerance of CMOS memories. In an integrated
memory circuit sensing means the detection and determination of the data content of
a selected memory cell.
CMOS memories are required to increase speed, improve capacity and maintain low
power dissipation. These objectives are somewhat conflicting when it comes to
memory sense amplifier design. With increased memory capacity, usually comes an
increased bit-line parasitic capacitance. This increased bit line capacitance in turn
slows down voltage sensing and makes bit line voltage swings expensive.
Figure3.6 Typical Sense Amplifier
The main function of sense amplifier is to sense or detect stored data from a read
selected memory cell. The memory cell being read produces a current Idata that
removes some charge (dQ) stored on the pre-charged bit lines. Since bit lines are very
long and are shared by other similar cells, the parasitic resistance Rbl and capacitance
Cbl are large. Thus the resulting bit line voltage swing (dVbl) caused by removal of
dQ from the bit line is very small dVbl=dQ/Cbl. Sense amplifiers are used to translate
this small voltage signal to a full signal that can be further used by digital logic.
Positive Feedback Differential Voltage Sense Amplifier:
Figure3.7 Positive feedback voltage sense amplifier
14
Digital analysis of Positive Feedback Voltage Sense Amplifier:
The positive feedback amplifier has 2 data nodes Vin/out1 and Vin/out2 and 3 control
nodes SANen, SAPen and PRE. The data nodes act as input and output to the sense
amplifier and its operation is as follows:
1. The data nodes are equalized using PRE
2. The memory cell being read is asserted and a small voltage difference forms on
nodes Vin/out1 and Vin/out2
3. While M1 and M2 are biased to be operating in the saturation region M6 is turned
on by SANen
4. As both Vin/out1 and Vin/out2 are decreasing in voltage so is the difference
between them
5. One of them decreases much faster then the other and causes M1 or M2 to enter
cutoff while the other starts operating in linear region.
6. At this point M5 is turned on by SAPen which pulls the signal rapidly apart
7. At this point since Vin/out1 and Vin/out2 are directly connected to bit lines the
data is automatically written to the read memory cell.
Due to its positive feedback this voltage sensing amplifier achieves a very high
differential gain. This high gain minimizes sensing time by being able to sense small
voltage swings on the bit line.
4. Control Read/Write Circuit:
The write-in buffers are enabled in such a way as to have them control the bit lines.
More precisely, by setting WE and OE the data terminal D is made to drive one BL
and its conjugate BLB in direct and complemented form respectively.
Digital Analysis of Data Read:
This can be achieved by setting WE=0 which disables the write-in buffers, thereby
permitting the memory cell selected to exert control over bit lines BL and BLB.
Further by setting OE=1 propagates the state stored in that cell to the data terminal D
via the enabled output buffer.
Digital Analysis of Data Write:
This is achieved by setting WE=1 and OE=0 and the data terminal D drives the bit
lines. The word line is activated causing the cross-connected inverters in the selected
cell to assume the value of bit lines imposed externally. After the cell is deselected,
the positive feedback mechanism maintains that state indefinitely until the cell’s
content is overwritten or the supply voltage gets turned off.
15
Figure3.8 Read/Write Control Circuit
5. Tristate buffers:
Tristate buffers are the buffers which are used to control the read and write
operations. The write enable and output enable signals are generated through these
buffers.
Figure 3.9 CMOS Implementation of Tristate Buffer
16
IV. Detailed analysis of 6T Cell Read Operation
The figure given below shows a typical static memory cell. The circuit consists of a
flipflop comprising two cross-coupled inverters and two access transistors Q5 and Q6.
Figure 4.1 Typical Static Memory Cell
Prior to initiating a read operation, the bit lines are precharged to Vdd. The read
operation is initiated by enabling the word line and connecting bit lines, BL and BLB
to the internal nodes of the cell.
Assume that the cell is storing a 1. In this case Q will be at Vdd and Qbar will be at
0 V. When the word line is selected and access transistors are turned Q5 and Q6 are
turned on.
Figure 4.2 Operation performed during Read 1
From the above given figure, we see that current flows from Bbar line through Q5.
This current charges CQbar. Equilibrium is reached when CQbar is charged to VQbar
at which I1 equals I5. To provide a non destructive read operation, the following
design constraints are to be taken care of:
17
1. VQbar should be less than Vtn of the next inverter i.e. in the figure it should be
less than Vtn of Q3. Vtn is the threshold voltage of individual NMOS and is
process dependent.
2. a). Aspect ratio of pass transistor for read 1 is given below
…… for the above circuit
…………… general form
b). The aspect ratio for read 0 is same as above except for the fact that the access
transistors are different i.e. ratio if Q6/Q2 = Q5/Q1.
3. In read 1 operation, VBL is maintained at precharge voltage and VBLB is
discharged to ∆V.
Figure 4.3 Bit line voltage during Read 1 operation
Whereas in read 0 operation, VBLB is maintained at precharge voltage and VBL
is discharged to ∆V.
4. Time required for the bit line voltage to discharge to ∆V by capacitor CB is given
by the equation given below,
…… time delay to reach ∆V
18
V. Analog Analysis Of 6T Cell Read
For economic reasons, minimizing the die area becomes important in memory design as
the basic storage cell gets repeated over and over again. The circuit consists of latch
and pass-transistor switches. Depending on the preserved state of the inverters, data is
stored in cell. To access the cell, we need switches which are connected between cell
and bit line, which is controlled by read/write circuitry.
Design Strategy:
The most important and basic requirement for efficient 6T cell design is the aspect ratio
of the transistors which is calculated depending on the following requirements:
 The data read operation should not destroy stored information in SRAM cell.
 The latch should allow modification of stored information in write operation.
6T Cell Design & Analysis using Cadence Tools:
1) DC Analysis of Read Zero:
a) 6T Cell
From the above figure we see that the value initially stored is 0. Output Enable (OE) is
turned on and the word line is activated. The voltage then developed between BL and
BLbar with VBbar lower than VB when the stored value is 0 which is given by V21.
RESULTS:
VBL=747.7 mV and VBLB=913.7mV, Vtn =0.677 (process defined)
Step1: VQbar = 606.1mV, we see that is VQbar is less than Vtn.
Step2: ∆V= VBL (pre) –VBL (new) = 1.38-747.7mV=0.6323V, we see that ∆V<= Vtn
19
Step3: Aspect Ratio (W/L) m26/ (W/L) m4 = 5
Figure current in access transistor
Step4: Time delay, ∆t = (CBL * ∆V)/I26 = (110pF * 0.6323V)/138.4uA = 50.255usec.
b) Sense Amplifier:
20
c) Pre-charge Circuit
i) Before clock, WL and OE is activated
ii) After clock, WL and OE is activated
21
d) Control Circuit:
The aspect ratio of all the transistors used in this design is tabulated in the table shown
below:
Transistor
NMOS_VTG
PMOS_VTG
6T
6T
inverter1(BLbar) inverter2(BL)
45n/45n
90n/45n
102.5n/45n
102.5/45n
Access transistors
32.85u/45n(BLB)
225n/45n(BL)
-
Precharge
circuit
-
Sense
Amplifier
90n/45n
775n/45n-1
120u/45n-2
180n/45n
Table1. Aspect Ratio Read Zero (W/L)
22
2) DC ANALYSIS OF READ ONE:
a) 6T Cell:
From the above figure we see that the value initially stored is 1. Output Enable (OE) is
turned on and the word line is activated. The voltage then developed between BL and
BLbar with VB higher than VBbar when the stored value is 1 as given by V21.
RESULTS:
VB=1.208V and VBbar=827mV Vtn= 0.6777 (process dependant)
Step1: VQbar = 468.6mV, we see that is VQbar is less than Vtn.
Step2: ∆V= VBLB (pre) –VBLB (new) = 1.38-827mV=0.553V, ∆V<=Vtn
Step3: Aspect Ratio (W/L) m25/ (W/L) m0 = 730
Figure current in access transistor
Step4: Time delay, ∆t = (CBL * ∆V)/I25 = (110pF * 0.553V)/19.05uA = 3.1931usec
23
b) Sense Amplifier:
c) Pre-charge Circuit:
24
d) Control Circuit:
The aspect ratio of all the transistors used in this design is tabulated in the table shown
below
Transistor
NMOS_VTG
PMOS_VTG
6T
6T
inverter1(BLbar) inverter2(BL)
45n/45n
90n/45n
102.5n/45n
102.5/45n
Access transistors
32.85u/45n(BLB)
32.85u/45n(BL)
-
Precharge
circuit
-
Sense
Amplifier
90n/45n
775n/45n-1
120u/45n-2
180n/45n
Table2. Aspect Ratio Read One (W/L)
25
VI. Detailed Analysis Of Write Operation
Write Operation:
The figure given below is the circuit diagram of a basic 6T cell. We wish to write a
zero, the objective now is to pull down the node Q (as VQ= Vdd and VQbar= 0V) and
node Qbar up and have the voltages of at least one of these two nodes pass.
Figure 6.1 Typical Static Memory Cell
For read operation, the upper bound ensured that VQbar should not rise above Vtn.
But our write zero operation, will be accomplished by pulling node Q down in order
to initiate the regenerative action of the latch. The following figure illustrates the
write circuitry during write zero operation.
Figure 6.2 Write Zero operation
26
From the figure we see that initially VQ is at Vdd. When transistor Q6 is turned ON,
I6 quickly discharges CQ and VQ begins to fall. The important requirements for write
operation to be completed are as follows:
1. VQ should be below Vtn of Q1 for read zero and vice-versa.
2. The aspect ratio of access and P transistor is as follows; where µn/µp is process
dependent quantity.
… General form
27
VII. Analog Analysis Of 6T Cell Write
1) DC Analysis of Write One
a) 6T CELL :
From the above figure we see that the value stored is 1. Write Enable (WE) are turned
on and the word line is activated. The voltage then developed between BL and BLB
with VBL higher than VBLB when the value to be written is 1 as given by V21.
RESULTS:
VBL=1.001V and VBLB=836.6mV, Vtn= 0.6777 (process dependant)
Step1: VQ = 1 V, we see that is VQ is more than Vtn.
Step2: ∆V= VBL (pre) –VBL (new) = 1.38-1.001V=0.379V
Step3: Aspect Ratio (W/L) m26/ (W/L) m5 = 10
28
Figure current in access transistor during write 1
Step4: Time delay, ∆t = (CBL * ∆V)/I26 = (110pF * 0.379V)/13.4fA = 3111sec
b) Sense Amplifier:
29
c) Pre-charge Circuit:
d) Control Circuit:
30
The aspect ratio of all the transistors used in this design is tabulated in the table
shown below:
Transistor
NMOS
PMOS
6T
6T
inverter1(BLbar) inverter2(BL)
45n/45n
90n/45n
102.5n/45n
320.85u/45n
Access transistors
32.85u/45n(BLB)
32.85u/45n(BL)
-
Precharge
circuit
-
Sense
Amplifier
90n/45n
775n/45n-1
120u/45n-2
180n/45n
Table3. Aspect Ratio Write One (W/L)
2) DC Analysis of Write Zero
a) 6T Cell:
From the above figure we see that the value stored is 0. Write Enable (WE) are turned
on and the word line is activated. The voltage then developed between BL and BLB
with VBL lower than VBLB when the value to be written is 0.
31
RESULTS:
VBL=218.1mV and VBLB=927.8mV, Vtn= 0.6777 (process dependant)
Step1: VQ = 592.7m V, we see that is VQ is less than Vtn.
Step2: ∆V= VBL (pre) –VBL (new) = 1.38- 218.1mV=1.1619V
Step3: Aspect Ratio (W/L) m26/ (W/L) m5 = 10
Figure current in access transistor during write
Step4: Time delay, ∆t = (CBL * ∆V)/I26 = (110pF * 1.1619V)/13.15mA = 9.719nsec
b) Sense Amplifier:
32
c) Precharge Circuit:
d) Control Circuit:
33
The aspect ratio of all the transistors used in this design is tabulated in the table
shown below
Transistor
NMOS_VTG
PMOS_VTG
6T
6T
inverter1(BLbar) inverter2(BL)
45n/45n
90n/45n
102.5n/45n
320.85u/45n
Access transistors
32.85u/45n(BLB)
225n/45n(BL)
-
Precharge
circuit
-
Sense
Amplifier
90n/45n
775n/45n-1
120u/45n-2
180n/45n
Table4. Aspect Ratio Write Zero (W/L)
34
VIII. Problems to be solved
a. Full voltage Swing has to be provided by the sense amplifier during read/write
operations especially in read operations where the zero and one is not being
completely read.
b. Transient analysis of individual operation.
c. Area optimization of pre-charge and 6T cell has to be done as W/L ratio is too
large.
35
IX. How to use Cadence
 What is cadence?
Cadence is an electronic design automation (EDA) software and engineering
services company.
 How to open cadence?
Cadence can be opened from any operating system. From windows it can be
opened on Xmanager.
The Xterm window opens up as shown below,
36
After giving the icfb& command, the following window opens up

How to make new libraries in cadence?
After the virtuoso window opens up click on File NewLibrary
37
As the library window opens up, Namedo not need process information
Then go back to the virtuoso window FileNewCell. The following window
opens up. In the cell tag put in the name of the cell you want. Once the name is
given, the virtuoso schematic editor window opens up.

How to add libraries?
On your Xterm window type vi cds.lib as shown in the figure below then you
have to make changes in the library path to add it in your home directory.
38
The figure shown below is the Virtuoso Schematic Editor which opens when we
make a new library and cell view.
39

How to draw the schematic on Virtuoso Window?
LibraryBrowse the window below opens up. Select the component you want to
use.
40
The figures given below shows how to use wire, instance properties, move, copy,
delete, pin names, wire names.
41
Once the schematic is complete, you do check and save and no errors should be
there on the CIW window.
Fast keys which could be used during designing.
42

How to do the simulation?
Once the design is checked and saved with no errors, we have to perform the
simulation. That can be achieved by clicking on LaunchADE L. it would look
like the following two window as shown in the figure.
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Then we have to set the model libraries by selecting Setup model libraries as
shown in the figure given below.
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As the model library setup window opens as shown in the figure given below,
click on the grey tab to browse the libraries to be added.
The browser window opens up to choose the model file as shown in the figure
given below.
The steps are followed as
FreePDK45ncsu_basekitmodelshspicetran_modelsmodels_nom
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Once the model libraries are setup, we can choose the analyses we want to run by
clicking on Analyses.
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We choose the type of analyses whether it is transient or dc or ac.
Once the analyses are chosen we can plot the outputs by selecting the Outputto
be plottedSelect on Schematic. The parameters to be plotted are shown in the
figure given below
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Once all these things are taken care of then we can simulate it by clicking on
Netlist and Run
The following result window opens up .
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The CIW window showing that simulation is completed successfully.
Once the simulation is successful, the outputs to be plotted are displayed. To read
the output in more detail, few steps have to be followed. The figure given below
is the merged graph of the outputs to be plotted.
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To read in detail click on AxisStrips
The graph will show individual readings of each output. To read the value on a
particular point on graph, click on MarkerPlaceTrace Marker as shown
below.
The point at which you place the marker will show the x-axis and y-axis reading
at that particular point.
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X. References
[1] Sedra/ Smith, Microelectronic Circuit, chapter 15, 6th edition
[2] Wai-Kai-Chen, Memory, Microprocessor an ASIC, 2003
[3] Tegze P. Haraszti, CMOS Memory Circuits, Kluwer Publication, 2002
[4] David Money Harris & Sarah L. Harris, Digital Design and Computer
Architecture
[5] Mohammed Sharifkhani, Design and Analysis of low power Sram, thesis report,
Waterloo University, Canada
[6] Prof. Etienna Sicard and Asst Prof. Sonia Delmas Bendhia, INSA Electronic
Engineering School of Toulouse, France, Advanced CMOS Cell Design
[7] Randall L. Geiger, Phillip E. Allen and Noel R. Strider, VLSI Design Techniques
for Analog and Digital Circuits
[8] R. Jacob Baker, Harry W. Li and David E. Boyce, CMOS Circuit Design, Layout
and Simulation
[9] Neil Weste, CMOS VLSI Design: A Circuit and System Perspective, International
Edition
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