17. Parallel processing
True or False:
1. T/F – Parallelism in computers is exploited to increase performance of the system.
ANS : T
2. T/F – In a multiprocessor architecture, the memory is usually divided between the
processing units.
ANS : F
3. T/F – Vector arrays execute SIMD type of instructions.
ANS : T
4. T/F – Memory access time for shared memory architectures are the same.
ANS : F
5. T/F – I/O operation in SMP require arbitration and time sharing.
ANS : T
6. T/F – Synchronization of data and processes is important in SMP environment.
ANS : T
7. T/F – Cache coherency is a common issue when using multiple levels of memory.
ANS : T
8. T/F – Software based cache coherency maintenance techniques are more transparent
to the programmer.
ANS : F
9. T/F – MESI cache coherency cannot be extended to the L1 cache level due to its
complexity.
ANS : F
10. T/F – A process and thread switch incur the same amount of time/cost.
ANS : F
11. T/F – In superscalar, all available issue slots are filled for every issue.
ANS : F
12. T/F – NUMA and cluster architectures have shared memory that are similar in
configuration.
ANS : F
13. T/F – Clusters are much harder to control compared the SMP systems.
ANS : T
14. T/F – All parts of the memory has the same access time in UMA.
ANS : T
15. T/F – Graphics and signal processors are examples of vector processors.
ANS : T
16. T/F – Pipelined ALUs are a type of vector organization.
ANS : T
Multiple Choice Questions:
1. This is a shared memory architecture
A. CMP
B. SMP
C. NUMA
D. All of the above
ANS : D
2. SMP and NUMA are examples of
A. MIMD
B. SIMD
C. MISD
D. SISD
ANS : A
3. These requires multiple control units to operate
A. SIMD
B. SISD
C. NUMA
D. None of the above
ANS : C
4. This takes care of scheduling and synchronization between multiple processors
A. Control unit
C. Operating System
B. Hardwired Control
D. All of the above
ANS : C
5. Cache coherency is addressed in
A. Control unit
B. Hardware
C. Software
D. None of the above
ANS : B
6. Processor failures in a SMP system must be taken care by
A. Hardware
B. Memory
C. Operating system
D. Compiler
ANS : C
7. Shared L2 caches is common in
A. Uniprocessor
B. Workstation SMP
C. General SMP
D. None of the above
ANS : B
8. Cache coherency in general is less in this type of scheme
A. Write through
B. Write back
C. Write buffer
D. All of the above
ANS : A
9. MESI protocol is implemented in
A. Cache tag
B. Cache index
C. Cache Block
D. None of the above
ANS : A
10. A Process switch involves saving of
A. Variables
B. Status
C. Control data
D. All of the above
ANS : D
11. If two identical processors are used to execute different threads of the same process, it is
called
A. Multi-processing
B. Multi-programming
C. SMP
D. Multi-core
ANS : D
12. This is a compiler technique to perform multithreading
A. SMP
C. VLIW
B. CMP
D. None of the above
ANS : C
13. Each computer in a cluster is called
A. Unit
B. Edge
C. Node
D. All of the above
ANS : C
14. An important advantage of a clustered system is
A. Parallelism
B. Coherency
C. High availability
D. Fault tolerance
ANS : C
15. The function of switching a failed process to another node in a cluster is called
A. Failure rate
B. Failover
C. Failpush
D. None of the above
ANS : B
16. NUMA has the advantage over SMP in
A. Performance & Parallelism
B. Power
C. Cycle time
D. None of the above
ANS : A
17. Instructions in vector processors fall under
A. Parallel simulations
B. Random simulations
C. Continuous field simulation
D. None of the above
ANS : C
Fill up the blanks:
1. In the SMP & NUMA architecture, the memory is ____________ between the
processing units.
ANS : shared
2. ___________ instructions operate on data stored in a single memory.
ANS : Multi-programming
3. In ______________ memory access time is not constant for all regions of the memory.
ANS : NUMA
4. In a SMP environment the processor communicate with each other through messages
left in ______________.
ANS : Common areas in memory
5. Invalid data in individual caches of SMP system is due to ____________.
ANS : Cache incoherency
6. A ______________ SMP configuration uses point-to-point inter memory links.
ANS : Workstation
7. Hardware cache coherence approaches are called _______________.
ANS : Protocols
8. A ________________ is small unit of a process that can be dispatched separately.
ANS : Thread
9. Multithreading is not the same as multi-________________.
ANS : Programming
10. A single thread is executed until an exception occurs and it is called ______________.
ANS : Block level threading
11. _______________ is loss incurred when all issue slots cannot be filled in a superscalar
machine.
ANS : Horizontal loss
12. _________________ is the ability of the cluster to equally distribute the processes
among its nodes.
ANS : Load balancing
13. _______________ house multiple servers with power supply on a single chassis.
ANS : Blade servers
14. NUMA processor have shared memory that are ____________ coupled.
ANS : Tightly
15. NUMA without cache coherency is equal to a _____________.
ANS : Cluster
16. Data forwarding in vector processor is called ________________.
ANS : Chaining