THE UNIVERSITY OF THE WEST INDIES
EXAMINATION OF MAY 2005
Code and Name of Course: EE19D DIGITAL ELECTRONICS
Paper:1/1
Date and Time:
Duration: 3 hours
INSTRUCTIONS TO CANDIDATES: This paper has 10 pages and 5 questions.
ANSWER ALL QUESTIONS
DOCUMENTS ARE ALLOWED
NO CALCULATORS ALLOWED
Q1 Consider the VHDL Model of chipX given as follows:
end arch_chipX
The University of the West Indies
Course Code EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.…04../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 2
a) Draw the block diagram of chipX.
2 Marks
b) What is the logic function implemented by chipX?
4 Marks
c) In an attempt of checking the syntax of the VHDL code using Xilinx Project, the
following message is being displayed:
Q2
Correct the error in the VHDL code (one line of code is sufficient)
3 Marks
d) Completed the timing diagram of figure Q1d that shows the expected results
when chipX is simulated with Modelsim.
4 Marks
e) Show how to implement the full adder Sum(A, B, Cin) and Carry(A, B, Cin) in
terms of two chipX.
7 Marks
a) State De Morgan’s Theorem.
2 marks
b) Write the Boolean expression for output Y in Fig Q2a.
4 Marks
c) Using De Morgan’s Theorem, convert the expression in (b) to a SOP 2 Marks
expression. DO NOT MINIMIZE.
d) Hence, using K-Map minimization, obtain a minimal solution for Y. Show 4 Marks
ALL working.
e) What is a static-1 logic hazard and under what conditions do they occur?
4 Marks
f) Are there any static-1 hazards in the minimal solution for Y obtained in (d)?
If so, point them out and show how they can be eliminated.
4 Marks
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 3
Figure Q2a.
Q3
a) Complete the following table related to base conversion.
Base 2
Base 4
Base 16
11100001.0001
?
?
?
1132.2322
?
4 Marks
b) Prove the identity of the Boolean equation AB’ + A’C’D’ + A’B’D + A’B’CD’ = B’ +
4 Marks
A’C’D’ using:
i.
ii.
Boolean laws
K-map method
c) Consider the circuit diagram of the 74LS138 decoder with 3 enable inputs G1, 4Marks
G1A, and G2B (figure Q3c). Give the Boolean expressions of Y0, Y1, Y2, Y3, Y4,
Y5, Y6, and Y7 as combinational functions of G1, G2A, G2B, A, B, and C.
d) Write the VHDL Model of the 74LS74 DFF whose logic diagram and truth table 4 Marks
are given in figure Q3d.
4 Marks
e) Complete the timing diagram for the circuit of figure Q3e.
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 4
U4
1
2
3
A
B
C
6
4
5
G1
G2A
G2B
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
Figure Q3c
DFFA
2
3
1
4
D
CLK
Q
CLR
Q
5
6
PRE
7474
(a) Logic Symbol
Inputs
CLR=1, PRE = 0
CLR = 0, PRE = 1
CLR=PRE=1
CLR=PRE=0
DFF Behavior
Q=1, Q’ = 0 (set Operation)
Q = 0, Q’ = 1 (reset operation)
Normal DFF behavior (Qn+1 = D)
To avoid
(b) Truth Table
Figure Q3d
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 5
Q4
a) Give three physical parameters that can be used to define an integrated
circuit technology (i.e. CMOS).
2 Marks
b) A particular IC has a time propagation of 20 ns. What is the maximum
frequency at which it can be used?
2 Marks
c) The IC in (b) is a NOT gate. Sketch its output if its input is 100 MHz square
wave.
2 Marks
d) Describe briefly the different design methods commonly used in digital
electronics.
4 Marks
e) Explain with the aid of a diagram the structure and operation of a 4 x 8 ROM
device that employs 1-dimensional decoding to store the following
hexadecimal data: AB, 10, E1, 02.
5 Marks
f) Consider the CMOS circuit of figure Q4f (A, B are inputs and F output);
5 Marks
i.
Write the complete truth table of the circuit that shows also the
status of the different MOS transistors and the output.
ii.
What particular logic gate is implemented here? Give its logic
symbol.
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 6
5V
Q1 (NMOS)
Q2 (PMOS)
IRF150
A
IRF9140
Q4 (PMOS)
Q3 (NMOS)
B
IRF150
IRF9140
F
R1
1000k
Figure Q4f
Q5
A serial binary adder adds two binary numbers X1 and X2 of arbitrary length,
producing the numerical sum Z = X1 + X2. The input numbers are entered into the
adder serially, i.e., bit by bit, and the result is also sent out serially. In one clock
cycle corresponding to time t, the adder can receive 2 bits x1(t) and x2(t) of X1 and
X2 and compute 1 bit z(t) of Z. Clearly each 1-bit addition can produce a carry
signal c(t) which affect the addition to be done in the next clock period. Thus the
two possible circuit states can exist: S0 meaning no carry signal was produced in
the preceding clock cycle, i.e., c(t-1) = 0; and S1, meaning c(t-1) = 1. The addition
performed at each step must then take the form x1(t) + x2(t) + c(t-1), where c(t-1) is
determined from the present state at time t.
4 Marks
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 7
a) Complete the following state table of the circuit of figure Q5a ( to each entry
in row S(t) and column I(t) = x1(t)x2(t) correspond a cell (S(t+1), z(t)). S0, and
S1 represent the two possible output values of a DFF (Q = 0 for S0, and Q
=1 for S1).
4 Marks
4 Marks
4 Marks
b) Draw the state diagram of the serial adder.
c) Write the VHDL Model of the State diagram.
d) Complete the transition table of figure Q5c.
4 Marks
e) Use K-maps to find the minimized expressions of D and z.
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 8
“Detach this sheet for attachment to your answer script”
Input/output
signals
0000
Din
a
0001
01
0010
1001
00
0011
10
1001
11
0100
00
0101
1101
01
11
Y
time
Fig. Q1d
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)
page 9
“Detach this sheet for attachment to your answer script”
Fig. Q3e
State
Input x1x2
00
01
10
11
S0
S1
S(t): Present state
S(t+1): Next state
Fig. Q5a
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
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page 10
“Detach this sheet for attachment to your answer script”
Present State
(Q)
0
0
0
0
1
1
1
1
x1
x2
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D
z
Fig. Q5c
END OF QUESTION PAPER
The University of the West Indies
Course Code: EE19D
May 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005…../.04…../.…..
Date: 2005…../.…04../.…..
(where applicable)