4. Cache Memory
True or False:
1. T/F – The memory devices used in a computer form a hierarchy based on a set of
characteristics.
ANS: T
2. T/F – The lowest level of memory in the hierarchy is the closest to the processor.
ANS: F
3. T/F – External memory capacity is represented in bytes.
ANS: T
4. T/F – The size of a word is typically equal to the number of bits required to represent
an integer
ANS: T
5. T/F – Semiconductor ROM memory is a nonerasable but volatile type of memory
ANS: F
6. T/F – If the memory has faster access time, then the cost per bit is less.
ANS: F
7. T/F – A hit occurs when the word requested can be accessed from the lowest memory
in the hierarchy.
ANS: F
8. T/F – Data stored in secondary or auxiliary memory is represented in terms of files or
records.
ANS: T
9. T/F – Direct mapping implies that the number of lines in the cache must be equal to the
main memory.
ANS: F
10. T/F – The best among the three cache replacement algorithms is the least recently
used (LRU) algorithm.
ANS: T
11. T/F – The write back policy allows the new data to be written both in the cache and the
main memory.
ANS: F
12. T/F – Like the entire memory, the system can have multi-level caches.
ANS: T
13. T/F – Cache contention between units increases with the use of split caches.
ANS: F
14. T/F – A region of memory that is shared between two processors is copied into L1
caches of the processors.
ANS: F
15. T/F – The Pentium 4 architecture has a direct mapped L1 cache.
ANS: F
16. T/F – The ARM cache organization uses a write buffer to aid in the write through
operation.
ANS: F
Multiple Choice Questions:
1. How are data stored in the internal memory?
A. Bytes
B. Words
C. Pages
D. A or B
ANS: D
2. Which among the following is not as method of accessing data?
A. Sequential
B. Asynchronous
C. Random
D. None of the above
ANS: B
3. The unit of transfer between the levels of memory is defined by
A. Type of memory access
B. Number of electrical lines in and out
of memory
C. Distance between the memory and processor D. All of the above
ANS: B
4. Performance of the memory is decided by which of the following parameters
A. Transfer rate
B. Latency
C. Cycle time
D. All of the above
ANS: D
5. Which of the following memory types is visible to the user?
A. Main memory
B. Virtual Memory
C. Level 3 cache
D. None of the above
ANS: A
6. Which of the following is not included in each line of the cache
A. Tag
B. Valid bit
C. Flag
D. Dirty bit
ANS: C
7. Victim caching helps what type of cache architecture?
A. Fully-associative
B. Direct mapped
C. Set-Associative
D. None of the above
ANS: B
8. Memory address in set-associative cache is interpreted into the three fields namely;
A. tag, set and word
B. tag, set and byte
C. valid bits, set and byte
D. valid bits, set and word
ANS: A
9. Random cache line replacement policy performs close to which other policy
A. LRU
B. LFU
C. FIFO
D. All of the above
ANS: D
10. When is a cache block is written into the main memory
A. Valid bit is not set
B. Every cycle
C. Dirty bit is set
D. None of the above
ANS: C
11. Split caches indicate separate
A. L1 and L2 cache
C. Data and Instruction cache
ANS: C
B. L2 and L3 cache
D. None of the above
12. Where is each cache in the hierarchy in the processor
A. On-chip L1 and Off-chip L2,L3
B. Off-chip L1,L2 and L3
C. On-chip L1,L2 and L3
D. On-chip L1,L2 and Off-chip L3
ANS: C
13. The logical cache in the hierarchy is accessed using
A. Decimal numbers
B. Physical Address
C. Virtual address
D. None of the above
ANS: C
14. Prefetching can be done only in what type of cache
A. Fully-associative
B. Direct mapped
C. Unified cache
D. Split-cache
ANS: D
16. As you go down the hierarchy,
A. Latency increases
C. Capacity increases
B. Cost per bit reduces
D. All of the above
ANS: D
Fill up the blanks:
1. _____________ is the number of bits written into or read out of main memory at a
time.
ANS: Unit of transfer
2. In _______________ cache, data is retrieved based on its location rather its address.
ANS: Set-associative
3. __________________ is the physical arrangement of bits to form words.
ANS: Organization
4. __________________ is a type of non-erasable semiconductor memory.
ANS: ROM
5. When successive memory access locations are close to each other, it is termed as
___________.
ANS: Locality of reference or Spatial locality
6. _______ is used to identify which particular block stores the data.
ANS: Tag
7. To access memory locations, the processor converts __________ into ___________.
ANS: physical address, virtual address
8. _________ algorithm is the ideal type of replacement algorithm as it predicts what
cache blocks will be referenced in the future based on the history.
ANS: Optimal
9. When a line of cache is replaced every cycle, the phenomenon is called __________.
ANS: Thrashing
10. In direct mapped cache, a simple ___________ function is used for mapping blocks
into the cache.
ANS: Modulo
11. _______________ policy ensures that all blocks in the cache are valid.
ANS: Write-through
12. There is a complex relationship between line size and ____________ due to
__________.
ANS: hit ratio, spatial locality
13. When a ________ occurs, there is no traffic in the system bus.
ANS: Hit
14. Depending on resource availability, Pentium 4 allows _______________.
ANS: Out-of order execution
15. __________ is the tendency of the processor to access memory location that have
been accessed recently.
ANS: Temporal locality
16. Data written to _____________ are not available for reading until transferred to main
memory.
ANS: Write buffer